Page 1 :
SEVENTH EDITION, , ELECTRONIC DEVICES, AND CIRCUIT THEORY, ROBERT BOYLESTAD, LOUIS NASHELSKY, , PRENTICE HALL, Upper Saddle River, New Jersey, , Columbus, Ohio
Page 2 :
Contents, , 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 1.10, 1.11, 1.12, 1.13, 1.14, 1.15, 1.16, 1.17, , 2, 2.1, 2.2, 2.3, , PREFACE, , xiii, , ACKNOWLEDGMENTS, , xvii, , SEMICONDUCTOR DIODES, , 1, , Introduction 1, Ideal Diode 1, Semiconductor Materials 3, Energy Levels 6, Extrinsic Materials—n- and p-Type 7, Semiconductor Diode 10, Resistance Levels 17, Diode Equivalent Circuits 24, Diode Specification Sheets 27, Transition and Diffusion Capacitance 31, Reverse Recovery Time 32, Semiconductor Diode Notation 32, Diode Testing 33, Zener Diodes 35, Light-Emitting Diodes (LEDs) 38, Diode Arrays—Integrated Circuits 42, PSpice Windows 43, , DIODE APPLICATIONS, , 51, , Introduction 51, Load-Line Analysis 52, Diode Approximations 57, v
Page 3 :
2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 2.10, 2.11, 2.12, 2.13, , 3, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6, 3.7, 3.8, 3.9, 3.10, 3.11, 3.12, , 4, 4.1, 4.2, 4.3, 4.4, 4.5, 4.6, 4.7, 4.8, 4.9, 4.10, 4.11, 4.12, 4.13, , 5, 5.1, 5.2, 5.3, vi, , Contents, , Series Diode Configurations with DC Inputs 59, Parallel and Series-Parallel Configurations 64, AND/OR Gates 67, Sinusoidal Inputs; Half-Wave Rectification 69, Full-Wave Rectification 72, Clippers 76, Clampers 83, Zener Diodes 87, Voltage-Multiplier Circuits 94, PSpice Windows 97, , BIPOLAR JUNCTION TRANSISTORS, , 112, , Introduction 112, Transistor Construction 113, Transistor Operation 113, Common-Base Configuration 115, Transistor Amplifying Action 119, Common-Emitter Configuration 120, Common-Collector Configuration 127, Limits of Operation 128, Transistor Specification Sheet 130, Transistor Testing 134, Transistor Casing and Terminal Identification 136, PSpice Windows 138, , DC BIASING—BJTS, , 143, , Introduction 143, Operating Point 144, Fixed-Bias Circuit 146, Emitter-Stabilized Bias Circuit 153, Voltage-Divider Bias 157, DC Bias with Voltage Feedback 165, Miscellaneous Bias Configurations 168, Design Operations 174, Transistor Switching Networks 180, Troubleshooting Techniques 185, PNP Transistors 188, Bias Stabilization 190, PSpice Windows 199, , FIELD-EFFECT TRANSISTORS, Introduction 211, Construction and Characteristics of JFETs 212, Transfer Characteristics 219, , 211
Page 4 :
5.4, 5.5, 5.6, 5.7, 5.8, 5.9, 5.10, 5.11, 5.12, 5.13, , 6, 6.1, 6.2, 6.3, 6.4, 6.5, 6.6, 6.7, 6.8, 6.9, 6.10, 6.11, 6.12, 6.13, , 7, 7.1, 7.2, 7.3, 7.4, 7.5, 7.6, 7.7, 7.8, , 8, 8.1, 8.3, 8.3, 8.4, 8.3, 8.6, , Specification Sheets (JFETs) 223, Instrumentation 226, Important Relationships 227, Depletion-Type MOSFET 228, Enhancement-Type MOSFET 234, MOSFET Handling 242, VMOS 243, CMOS 244, Summary Table 246, PSpice Windows 247, , FET BIASING, , 253, , Introduction 253, Fixed-Bias Configuration 254, Self-Bias Configuration 258, Voltage-Divider Biasing 264, Depletion-Type MOSFETs 270, Enhancement-Type MOSFETs 274, Summary Table 280, Combination Networks 282, Design 285, Troubleshooting 287, P-Channel FETs 288, Universal JFET Bias Curve 291, PSpice Windows 294, , BJT TRANSISTOR MODELING, , 305, , Introduction 305, Amplification in the AC Domain 305, BJT Transistor Modeling 306, The Important Parameters: Zi, Zo, Av, Ai 308, The re Transistor Model 314, The Hybrid Equivalent Model 321, Graphical Determination of the h-parameters 327, Variations of Transistor Parameters 331, , BJT SMALL-SIGNAL ANALYSIS, , 338, , Introduction 338, Common-Emitter Fixed-Bias Configuration 338, Voltage-Divider Bias 342, CE Emitter-Bias Configuration 345, Emitter-Follower Configuration 352, Common-Base Configuration 358, Contents, , vii
Page 5 :
8.7, 8.8, 8.9, 8.10, 8.11, 8.12, 8.13, , 9, 9.1, 9.2, 9.3, 9.4, 9.5, 9.6, 9.7, 9.8, 9.9, 9.10, 9.11, 9.12, 9.13, 9.14, 9.15, , 10, 10.1, 10.2, 10.3, 10.4, 10.5, 10.6, 10.7, 10.8, 10.9, 10.10, 10.11, 10.12, , 11, 11.1, 11.2, 11.3, viii, , Contents, , Collector Feedback Configuration 360, Collector DC Feedback Configuration 366, Approximate Hybrid Equivalent Circuit 369, Complete Hybrid Equivalent Model 375, Summary Table 382, Troubleshooting 382, PSpice Windows 385, , FET SMALL-SIGNAL ANALYSIS, , 401, , Introduction 401, FET Small-Signal Model 402, JFET Fixed-Bias Configuration 410, JFET Self-Bias Configuration 412, JFET Voltage-Divider Configuration 418, JFET Source-Follower (Common-Drain) Configuration 419, JFET Common-Gate Configuration 422, Depletion-Type MOSFETs 426, Enhancement-Type MOSFETs 428, E-MOSFET Drain-Feedback Configuration 429, E-MOSFET Voltage-Divider Configuration 432, Designing FET Amplifier Networks 433, Summary Table 436, Troubleshooting 439, PSpice Windows 439, , SYSTEMS APPROACH—, EFFECTS OF Rs AND RL, , 452, , Introduction 452, Two-Port Systems 452, Effect of a Load Impedance (RL) 454, Effect of a Source Impedance (Rs) 459, Combined Effect of Rs and RL 461, BJT CE Networks 463, BJT Emitter-Follower Networks 468, BJT CB Networks 471, FET Networks 473, Summary Table 476, Cascaded Systems 480, PSpice Windows 481, , BJT AND JFET FREQUENCY RESPONSE, Introduction 493, Logarithms 493, Decibels 497, , 493
Page 6 :
11.4, 11.5, 11.6, 11.7, 11.8, 11.9, 11.10, 11.11, 11.12, 11.13, , 12, 12.1, 12.2, 12.3, 12.4, 12.5, 12.6, 12.7, 12.8, 12.9, 12.10, 12.11, , General Frequency Considerations 500, Low-Frequency Analysis—Bode Plot 503, Low-Frequency Response—BJT Amplifier 508, Low-Frequency Response—FET Amplifier 516, Miller Effect Capacitance 520, High-Frequency Response—BJT Amplifier 523, High-Frequency Response—FET Amplifier 530, Multistage Frequency Effects 534, Square-Wave Testing 536, PSpice Windows 538, , COMPOUND CONFIGURATIONS, Introduction 544, Cascade Connection 544, Cascode Connection 549, Darlington Connection 550, Feedback Pair 555, CMOS Circuit 559, Current Source Circuits 561, Current Mirror Circuits 563, Differential Amplifier Circuit 566, BIFET, BIMOS, and CMOS Differential Amplifier Circuits 574, PSpice Windows 575, , 13, , DISCRETE AND IC, MANUFACTURING TECHNIQUES, , 13.1, 13.2, 13.3, 13.4, 13.5, 13.6, 13.7, 13.8, 13.9, , Introduction 588, Semiconductor Materials, Si, Ge, and GaAs 588, Discrete Diodes 590, Transistor Fabrication 592, Integrated Circuits 593, Monolithic Integrated Circuit 595, The Production Cycle 597, Thin-Film and Thick-Film Integrated Circuits 607, Hybrid Integrated Circuits 608, , 14, 14.1, 14.2, 14.3, 14.4, 14.5, 14.6, 14.7, 14.8, , 544, , OPERATIONAL AMPLIFIERS, , 588, , 609, , Introduction 609, Differential and Common-Mode Operation 611, Op-Amp Basics 615, Practical Op-Amp Circuits 619, Op-Amp Specifications—DC Offset Parameters 625, Op-Amp Specifications—Frequency Parameters 628, Op-Amp Unit Specifications 632, PSpice Windows 638, Contents, , ix
Page 7 :
15, 15.1, 15.2, 15.3, 15.4, 15.5, 15.6, 15.7, , 16, 16.1, 16.2, 16.3, 16.4, 16.5, 16.6, 16.7, 16.8, 16.9, , 17, 17.1, 17.2, 17.3, 17.4, 17.5, 17.6, 17.7, 17.8, , 18, 18.1, 18.2, 18.3, 18.4, 18.5, 18.6, 18.7, 18.8, 18.9, 18.10, x, , Contents, , OP-AMP APPLICATIONS, , 648, , Constant-Gain Multiplier 648, Voltage Summing 652, Voltage Buffer 655, Controller Sources 656, Instrumentation Circuits 658, Active Filters 662, PSpice Windows 666, , POWER AMPLIFIERS, , 679, , Introduction—Definitions and Amplifier Types 679, Series-Fed Class A Amplifier 681, Transformer-Coupled Class A Amplifier 686, Class B Amplifier Operation 693, Class B Amplifier Circuits 697, Amplifier Distortion 704, Power Transistor Heat Sinking 708, Class C and Class D Amplifiers 712, PSpice Windows 714, , LINEAR-DIGITAL ICs, , 721, , Introduction 721, Comparator Unit Operation 721, Digital-Analog Converters 728, Timer IC Unit Operation 732, Voltage-Controlled Oscillator 735, Phase-Locked Loop 738, Interfacing Circuitry 742, PSpice Windows 745, , FEEDBACK AND OSCILLATOR CIRCUITS, Feedback Concepts 751, Feedback Connection Types 752, Practical Feedback Circuits 758, Feedback Amplifier—Phase and Frequency Considerations 765, Oscillator Operation 767, Phase-Shift Oscillator 769, Wien Bridge Oscillator 772, Tuned Oscillator Circuit 773, Crystal Oscillator 776, Unijunction Oscillator 780, , 751
Page 8 :
19, 19.1, 19.2, 19.3, 19.4, 19.5, 19.6, 19.7, , 20, 20.1, 20.2, 20.3, 20.4, 20.5, 20.6, 20.7, 20.8, 20.9, 20.10, 20.11, , 21, 21.1, 21.2, 21.3, 21.4, 21.5, 21.6, 21.7, 21.8, 21.9, 21.10, 21.11, 21.12, 21.13, 21.14, 21.15, 21.16, , POWER SUPPLIES, (VOLTAGE REGULATORS), , 783, , Introduction 783, General Filter Considerations 783, Capacitor Filter 786, RC Filter 789, Discrete Transistor Voltage Regulation 792, IC Voltage Regulators 799, PSpice Windows 804, , OTHER TWO-TERMINAL DEVICES, , 810, , Introduction 810, Schottky Barrier (Hot-Carrier) Diodes 810, Varactor (Varicap) Diodes 814, Power Diodes 818, Tunnel Diodes 819, Photodiodes 824, Photoconductive Cells 827, IR Emitters 829, Liquid-Crystal Displays 831, Solar Cells 833, Thermistors 837, , pnpn AND OTHER DEVICES, , 842, , Introduction 842, Silicon-Controlled Rectifier 842, Basic Silicon-Controlled Rectifier Operation 842, SCR Characteristics and Ratings 845, SCR Construction and Terminal Identification 847, SCR Applications 848, Silicon-Controlled Switch 852, Gate Turn-Off Switch 854, Light-Activated SCR 855, Shockley Diode 858, DIAC 858, TRIAC 860, Unijunction Transistor 861, Phototransistors 871, Opto-Isolators 873, Programmable Unijunction Transistor 875, Contents, , xi
Page 9 :
22, 22.1, 22.2, 22.3, 22.4, 22.5, 22.6, 22.7, 22.8, 22.9, , xii, , Contents, , OSCILLOSCOPE AND OTHER, MEASURING INSTRUMENTS, , 884, , Introduction 884, Cathode Ray Tube—Theory and Construction 884, Cathode Ray Oscilloscope Operation 885, Voltage Sweep Operation 886, Synchronization and Triggering 889, Multitrace Operation 893, Measurement Using Calibrated CRO Scales 893, Special CRO Features 898, Signal Generators 899, , APPENDIX A: HYBRID PARAMETERS—, CONVERSION EQUATIONS, (EXACT AND APPROXIMATE), , 902, , APPENDIX B: RIPPLE FACTOR AND, VOLTAGE CALCULATIONS, , 904, , APPENDIX C: CHARTS AND TABLES, , 911, , APPENDIX D: SOLUTIONS TO SELECTED, ODD-NUMBERED PROBLEMS, , 913, , INDEX, , 919
Page 10 :
Acknowledgments, Our sincerest appreciation must be extended to the instructors who have used the text, and sent in comments, corrections, and suggestions. We also want to thank Rex Davidson, Production Editor at Prentice Hall, for keeping together the many detailed aspects of production. Our sincerest thanks to Dave Garza, Senior Editor, and Linda, Ludewig, Editor, at Prentice Hall for their editorial support of the Seventh Edition of, this text., We wish to thank those individuals who have shared their suggestions and evaluations of this text throughout its many editions. The comments from these individuals have enabled us to present Electronic Devices and Circuit Theory in this Seventh, Edition:, Ernest Lee Abbott, Phillip D. Anderson, Al Anthony, A. Duane Bailey, Joe Baker, Jerrold Barrosse, Ambrose Barry, Arthur Birch, Scott Bisland, Edward Bloch, Gary C. Bocksch, Jeffrey Bowe, Alfred D. Buerosse, Lila Caggiano, Mauro J. Caputi, Robert Casiano, Alan H. Czarapata, Mohammad Dabbas, John Darlington, Lucius B. Day, Mike Durren, Dr. Stephen Evanson, George Fredericks, F. D. Fuller, , Napa College, Napa, CA, Muskegon Community College, Muskegon, MI, EG&G VACTEC Inc., Southern Alberta Institute of Technology, Calgary, Alberta, CANADA, University of Southern California, Los Angeles, CA, Penn State–Ogontz, University of North Carolina–Charlotte, Hartford State Technical College, Hartford, CT, SEMATECH, Austin, TX, The Perkin-Elmer Corporation, Charles S. Mott Community College, Flint, MI, Bunker Hill Community College, Charlestown, MA, Waukesha County Technical College, Pewaukee, WI, MicroSim Corporation, Hofstra University, International Rectifier Corporation, Montgomery College, Rockville, MD, ITT Technical Institute, Humber College, Ontario, CANADA, Metropolitan State College, Denver, CO, Indiana Vocational Technical College, South Bend, IN, Bradford University, UK, Northeast State Technical Community College, Blountville, TN, Humber College, Ontario, CANADA, xvii
Page 11 :
Phil Golden, Joseph Grabinski, Thomas K. Grady, William Hill, Albert L. Ickstadt, Jeng-Nan Juang, Karen Karger, Kenneth E. Kent, Donald E. King, Charles Lewis, Donna Liverman, William Mack, Robert Martin, George T. Mason, William Maxwell, Abraham Michelen, John MacDougall, Donald E. McMillan, Thomas E. Newman, Byron Paul, Dr. Robert Payne, Dr. Robert A. Powell, E. F. Rockafellow, Saeed A. Shaikh, Dr. Noel Shammas, Ken Simpson, Eric Sung, Donald P. Szymanski, Parker M. Tabor, Peter Tampas, Chuck Tinney, Katherine L. Usik, Domingo Uy, Richard J. Walters, Larry J. Wheeler, Julian Wilson, Syd R. Wilson, Jean Younes, Charles E. Yunghans, Ulrich E. Zeisler, , xviii, , Acknowledgments, , DeVry Institute of Technology, Irving, TX, Hartford State Technical College, Hartfold, CT, Western Washington University, Bellingham, WA, ITT Technical Institute, San Diego Mesa College, San Diego, CA, Mercer University, Macon, GA, Tektronix Inc., DeKalb Technical Institute, Clarkston, GA, ITT Technical Institute, Youngstown, OH, APPLIED MATERIALS, INC., Texas Instruments Inc., Harrisburg Area Community College, Northern Virginia Community College, Indiana Vocational Technical College, South Bend, IN, Nashville State Technical Institute, Hudson Valley Community College, University of Western Ontario, London, Ontario,, CANADA, Southwest State University, Marshall, MN, L. H. Bates Vocational-Technical Institute, Tacoma, WA, Bismarck State College, University of Glamorgan, Wales, UK, Oakland Community College, Southern-Alberta Institute of Technology, Calgary,, Alberta, CANADA, Miami-Dade Community College, Miami, FL, School of Engineering, Beaconside, UK, Stark State College of Technology, Computronics Technology Inc., Owens Technical College, Toledo, OH, Greenville Technical College, Greenville, SC, Michigan Technological University, Houghton, MI, University of Utah, Mohawk College of Applied Art & Technology,, Hamilton, Ontario, CANADA, Hampton University, Hampton, VA, DeVry Technical Institute, Woodbridge, NJ, PSE&G Nuclear, Southern College of Technology, Marietta, GA, Motorola Inc., ITT Technical Institute, Troy, MI, Western Washington University, Bellingham, WA, Salt Lake Community College, Salt Lake City, UT
Page 12 :
p n, , CHAPTER, , Semiconductor, Diodes, , 1, , 1.1 INTRODUCTION, It is now some 50 years since the first transistor was introduced on December 23,, 1947. For those of us who experienced the change from glass envelope tubes to the, solid-state era, it still seems like a few short years ago. The first edition of this text, contained heavy coverage of tubes, with succeeding editions involving the important, decision of how much coverage should be dedicated to tubes and how much to semiconductor devices. It no longer seems valid to mention tubes at all or to compare the, advantages of one over the other—we are firmly in the solid-state era., The miniaturization that has resulted leaves us to wonder about its limits. Complete systems now appear on wafers thousands of times smaller than the single element of earlier networks. New designs and systems surface weekly. The engineer becomes more and more limited in his or her knowledge of the broad range of advances—, it is difficult enough simply to stay abreast of the changes in one area of research or, development. We have also reached a point at which the primary purpose of the container is simply to provide some means of handling the device or system and to provide a mechanism for attachment to the remainder of the network. Miniaturization, appears to be limited by three factors (each of which will be addressed in this text):, the quality of the semiconductor material itself, the network design technique, and, the limits of the manufacturing and processing equipment., , 1.2 IDEAL DIODE, The first electronic device to be introduced is called the diode. It is the simplest of, semiconductor devices but plays a very vital role in electronic systems, having characteristics that closely match those of a simple switch. It will appear in a range of applications, extending from the simple to the very complex. In addition to the details, of its construction and characteristics, the very important data and graphs to be found, on specification sheets will also be covered to ensure an understanding of the terminology employed and to demonstrate the wealth of information typically available, from manufacturers., The term ideal will be used frequently in this text as new devices are introduced., It refers to any device or system that has ideal characteristics—perfect in every way., It provides a basis for comparison, and it reveals where improvements can still be, made. The ideal diode is a two-terminal device having the symbol and characteristics shown in Figs. 1.1a and b, respectively., , Figure 1.1 Ideal diode: (a), symbol; (b) characteristics., , 1
Page 13 :
p n, , Ideally, a diode will conduct current in the direction defined by the arrow in the, symbol and act like an open circuit to any attempt to establish current in the opposite direction. In essence:, The characteristics of an ideal diode are those of a switch that can conduct, current in only one direction., In the description of the elements to follow, it is critical that the various letter, symbols, voltage polarities, and current directions be defined. If the polarity of the, applied voltage is consistent with that shown in Fig. 1.1a, the portion of the characteristics to be considered in Fig. 1.1b is to the right of the vertical axis. If a reverse, voltage is applied, the characteristics to the left are pertinent. If the current through, the diode has the direction indicated in Fig. 1.1a, the portion of the characteristics to, be considered is above the horizontal axis, while a reversal in direction would require, the use of the characteristics below the axis. For the majority of the device characteristics that appear in this book, the ordinate (or “y” axis) will be the current axis,, while the abscissa (or “x” axis) will be the voltage axis., One of the important parameters for the diode is the resistance at the point or region of operation. If we consider the conduction region defined by the direction of ID, and polarity of VD in Fig. 1.1a (upper-right quadrant of Fig. 1.1b), we will find that, the value of the forward resistance, RF, as defined by Ohm’s law is, VF, 0V, RF , 0 , IF, 2, 3, mA, . . . , or any positive value, , (short circuit), , where VF is the forward voltage across the diode and IF is the forward current through, the diode., The ideal diode, therefore, is a short circuit for the region of conduction., Consider the region of negatively applied potential (third quadrant) of Fig. 1.1b,, 5, 20, or any reverse-bias potential, VR, , RR , IR, 0 mA, , (open-circuit), , where VR is reverse voltage across the diode and IR is reverse current in the diode., The ideal diode, therefore, is an open circuit in the region of nonconduction., In review, the conditions depicted in Fig. 1.2 are applicable., , +, , VD, , –, , Short circuit, ID, I D (limited by circuit), (a), 0, , –, , VD, , +, , VD, , Open circuit, , ID = 0, (b), , Figure 1.2 (a) Conduction and (b) nonconduction states of the ideal diode as, determined by the applied bias., , In general, it is relatively simple to determine whether a diode is in the region of, conduction or nonconduction simply by noting the direction of the current ID established by an applied voltage. For conventional flow (opposite to that of electron flow),, if the resultant diode current has the same direction as the arrowhead of the diode, symbol, the diode is operating in the conducting region as depicted in Fig. 1.3a. If, 2, , Chapter 1, , Semiconductor Diodes
Page 14 :
p n, , the resulting current has the opposite direction, as shown in Fig. 1.3b, the opencircuit equivalent is appropriate., , ID, , ID, (a), , ID = 0, , ID, , Figure 1.3 (a) Conduction, and (b) nonconduction states of, the ideal diode as determined by, the direction of conventional, current established by the, network., , (b), , As indicated earlier, the primary purpose of this section is to introduce the characteristics of an ideal device for comparison with the characteristics of the commercial variety. As we progress through the next few sections, keep the following questions in mind:, How close will the forward or “on” resistance of a practical diode compare, with the desired 0- level?, Is the reverse-bias resistance sufficiently large to permit an open-circuit approximation?, , 1.3 SEMICONDUCTOR MATERIALS, The label semiconductor itself provides a hint as to its characteristics. The prefix semiis normally applied to a range of levels midway between two limits., The term conductor is applied to any material that will support a generous, flow of charge when a voltage source of limited magnitude is applied across, its terminals., An insulator is a material that offers a very low level of conductivity under, pressure from an applied voltage source., A semiconductor, therefore, is a material that has a conductivity level somewhere between the extremes of an insulator and a conductor., Inversely related to the conductivity of a material is its resistance to the flow of, charge, or current. That is, the higher the conductivity level, the lower the resistance, level. In tables, the term resistivity (, Greek letter rho) is often used when comparing the resistance levels of materials. In metric units, the resistivity of a material is, measured in -cm or -m. The units of -cm are derived from the substitution of, the units for each quantity of Fig. 1.4 into the following equation (derived from the, basic resistance equation R l/A):, RA, ()(cm2), ⇒ -cm, l, cm, , (1.1), , In fact, if the area of Fig. 1.4 is 1 cm2 and the length 1 cm, the magnitude of the, resistance of the cube of Fig. 1.4 is equal to the magnitude of the resistivity of the, material as demonstrated below:, , Figure 1.4 Defining the metric, units of resistivity., , l, (1 cm), ohms, R , A, (1 cm2), This fact will be helpful to remember as we compare resistivity levels in the discussions to follow., In Table 1.1, typical resistivity values are provided for three broad categories of, materials. Although you may be familiar with the electrical properties of copper and, 1.3 Semiconductor Materials, , 3
Page 15 :
p n, , TABLE 1.1 Typical Resistivity Values, , Figure 1.5 Ge and Si, single-crystal structure., , 4, , Conductor, , Semiconductor, , Insulator, , 106 -cm, (copper), , 50 -cm (germanium), 50 103 -cm (silicon), , 1012 -cm, (mica), , mica from your past studies, the characteristics of the semiconductor materials of germanium (Ge) and silicon (Si) may be relatively new. As you will find in the chapters, to follow, they are certainly not the only two semiconductor materials. They are, however, the two materials that have received the broadest range of interest in the development of semiconductor devices. In recent years the shift has been steadily toward, silicon and away from germanium, but germanium is still in modest production., Note in Table 1.1 the extreme range between the conductor and insulating materials for the 1-cm length (1-cm2 area) of the material. Eighteen places separate the, placement of the decimal point for one number from the other. Ge and Si have received the attention they have for a number of reasons. One very important consideration is the fact that they can be manufactured to a very high purity level. In fact,, recent advances have reduced impurity levels in the pure material to 1 part in 10 billion (110,000,000,000). One might ask if these low impurity levels are really necessary. They certainly are if you consider that the addition of one part impurity (of, the proper type) per million in a wafer of silicon material can change that material, from a relatively poor conductor to a good conductor of electricity. We are obviously, dealing with a whole new spectrum of comparison levels when we deal with the semiconductor medium. The ability to change the characteristics of the material significantly through this process, known as “doping,” is yet another reason why Ge and Si, have received such wide attention. Further reasons include the fact that their characteristics can be altered significantly through the application of heat or light—an important consideration in the development of heat- and light-sensitive devices., Some of the unique qualities of Ge and Si noted above are due to their atomic, structure. The atoms of both materials form a very definite pattern that is periodic in, nature (i.e., continually repeats itself). One complete pattern is called a crystal and, the periodic arrangement of the atoms a lattice. For Ge and Si the crystal has the, three-dimensional diamond structure of Fig. 1.5. Any material composed solely of repeating crystal structures of the same kind is called a single-crystal structure. For, semiconductor materials of practical application in the electronics field, this singlecrystal feature exists, and, in addition, the periodicity of the structure does not change, significantly with the addition of impurities in the doping process., Let us now examine the structure of the atom itself and note how it might affect, the electrical characteristics of the material. As you are aware, the atom is composed, of three basic particles: the electron, the proton, and the neutron. In the atomic lattice, the neutrons and protons form the nucleus, while the electrons revolve around, the nucleus in a fixed orbit. The Bohr models of the two most commonly used semiconductors, germanium and silicon, are shown in Fig. 1.6., As indicated by Fig. 1.6a, the germanium atom has 32 orbiting electrons, while, silicon has 14 orbiting electrons. In each case, there are 4 electrons in the outermost, (valence) shell. The potential (ionization potential) required to remove any one of, these 4 valence electrons is lower than that required for any other electron in the structure. In a pure germanium or silicon crystal these 4 valence electrons are bonded to, 4 adjoining atoms, as shown in Fig. 1.7 for silicon. Both Ge and Si are referred to as, tetravalent atoms because they each have four valence electrons., A bonding of atoms, strengthened by the sharing of electrons, is called covalent bonding., Chapter 1, , Semiconductor Diodes
Page 16 :
p n, , Figure 1.6 Atomic structure: (a) germanium;, (b) silicon., , Figure 1.7, atom., , Covalent bonding of the silicon, , Although the covalent bond will result in a stronger bond between the valence, electrons and their parent atom, it is still possible for the valence electrons to absorb, sufficient kinetic energy from natural causes to break the covalent bond and assume, the “free” state. The term free reveals that their motion is quite sensitive to applied, electric fields such as established by voltage sources or any difference in potential., These natural causes include effects such as light energy in the form of photons and, thermal energy from the surrounding medium. At room temperature there are approximately 1.5 1010 free carriers in a cubic centimeter of intrinsic silicon material., Intrinsic materials are those semiconductors that have been carefully refined, to reduce the impurities to a very low level—essentially as pure as can be, made available through modern technology., The free electrons in the material due only to natural causes are referred to as, intrinsic carriers. At the same temperature, intrinsic germanium material will have, approximately 2.5 1013 free carriers per cubic centimeter. The ratio of the number of carriers in germanium to that of silicon is greater than 103 and would indicate that germanium is a better conductor at room temperature. This may be true,, but both are still considered poor conductors in the intrinsic state. Note in Table 1.1, that the resistivity also differs by a ratio of about 10001, with silicon having the, larger value. This should be the case, of course, since resistivity and conductivity are, inversely related., An increase in temperature of a semiconductor can result in a substantial increase in the number of free electrons in the material., As the temperature rises from absolute zero (0 K), an increasing number of valence electrons absorb sufficient thermal energy to break the covalent bond and contribute to the number of free carriers as described above. This increased number of, carriers will increase the conductivity index and result in a lower resistance level., Semiconductor materials such as Ge and Si that show a reduction in resistance with increase in temperature are said to have a negative temperature, coefficient., You will probably recall that the resistance of most conductors will increase with, temperature. This is due to the fact that the numbers of carriers in a conductor will, 1.3 Semiconductor Materials, , 5
Page 17 :
p n, , not increase significantly with temperature, but their vibration pattern about a relatively fixed location will make it increasingly difficult for electrons to pass through., An increase in temperature therefore results in an increased resistance level and a positive temperature coefficient., , 1.4 ENERGY LEVELS, In the isolated atomic structure there are discrete (individual) energy levels associated, with each orbiting electron, as shown in Fig. 1.8a. Each material will, in fact, have, its own set of permissible energy levels for the electrons in its atomic structure., The more distant the electron from the nucleus, the higher the energy state,, and any electron that has left its parent atom has a higher energy state than, any electron in the atomic structure., Energy, Valance Level (outermost shell), Energy gap, Second Level (next inner shell), Energy gap, Third Level (etc.), etc., Nucleus, , (a), Energy, Conduction band, , Electrons, "free" to, establish, conduction, , Energy, , Conduction band, , Eg, , E g > 5 eV, , Valence band, , Figure 1.8 Energy levels: (a), discrete levels in isolated atomic, structures; (b) conduction and, valence bands of an insulator,, semiconductor, and conductor., , Energy, , Valence, electrons, bound to, the atomic, stucture, , Insulator, , The bands, overlap, , Conduction band, , Valence band, Valence band, , E g = 1.1 eV (Si), E g = 0.67 eV (Ge), E g = 1.41 eV (GaAs), Semiconductor, , Conductor, , (b), , Between the discrete energy levels are gaps in which no electrons in the isolated, atomic structure can appear. As the atoms of a material are brought closer together to, form the crystal lattice structure, there is an interaction between atoms that will result in the electrons in a particular orbit of one atom having slightly different energy, levels from electrons in the same orbit of an adjoining atom. The net result is an expansion of the discrete levels of possible energy states for the valence electrons to, that of bands as shown in Fig. 1.8b. Note that there are boundary levels and maximum energy states in which any electron in the atomic lattice can find itself, and there, remains a forbidden region between the valence band and the ionization level. Recall, 6, , Chapter 1, , Semiconductor Diodes
Page 18 :
p n, , that ionization is the mechanism whereby an electron can absorb sufficient energy to, break away from the atomic structure and enter the conduction band. You will note, that the energy associated with each electron is measured in electron volts (eV). The, unit of measure is appropriate, since, W QV, , eV, , (1.2), , as derived from the defining equation for voltage V W/Q. The charge Q is the charge, associated with a single electron., Substituting the charge of an electron and a potential difference of 1 volt into Eq., (1.2) will result in an energy level referred to as one electron volt. Since energy is, also measured in joules and the charge of one electron 1.6 1019 coulomb,, W QV (1.6 1019 C)(1 V), and, , 1 eV 1.6 1019 J, , (1.3), , At 0 K or absolute zero (273.15°C), all the valence electrons of semiconductor, materials find themselves locked in their outermost shell of the atom with energy, levels associated with the valence band of Fig. 1.8b. However, at room temperature, (300 K, 25°C) a large number of valence electrons have acquired sufficient energy to, leave the valence band, cross the energy gap defined by Eg in Fig. 1.8b and enter the, conduction band. For silicon Eg is 1.1 eV, for germanium 0.67 eV, and for gallium, arsenide 1.41 eV. The obviously lower Eg for germanium accounts for the increased, number of carriers in that material as compared to silicon at room temperature. Note, for the insulator that the energy gap is typically 5 eV or more, which severely limits, the number of electrons that can enter the conduction band at room temperature. The, conductor has electrons in the conduction band even at 0 K. Quite obviously, therefore, at room temperature there are more than enough free carriers to sustain a heavy, flow of charge, or current., We will find in Section 1.5 that if certain impurities are added to the intrinsic, semiconductor materials, energy states in the forbidden bands will occur which will, cause a net reduction in Eg for both semiconductor materials—consequently, increased, carrier density in the conduction band at room temperature!, , 1.5 EXTRINSIC MATERIALS—, n- AND p-TYPE, The characteristics of semiconductor materials can be altered significantly by the addition of certain impurity atoms into the relatively pure semiconductor material. These, impurities, although only added to perhaps 1 part in 10 million, can alter the band, structure sufficiently to totally change the electrical properties of the material., A semiconductor material that has been subjected to the doping process is, called an extrinsic material., There are two extrinsic materials of immeasurable importance to semiconductor, device fabrication: n-type and p-type. Each will be described in some detail in the, following paragraphs., , n-Type Material, Both the n- and p-type materials are formed by adding a predetermined number of, impurity atoms into a germanium or silicon base. The n-type is created by introducing those impurity elements that have five valence electrons (pentavalent), such as antimony, arsenic, and phosphorus. The effect of such impurity elements is indicated in, 1.5 Extrinsic Materials—n- and p-Type, , 7
Page 19 :
p n, , –, –, , Si, , –, –, , –, , Si, , –, , Si, , –, , –, , Si, , –, –, , –, , Si, , –, , –, , Si, , –, , –, , – –, – Sb –, –, , –, –, , –, , –, , –, –, , –, –, , Fifth valence, electron, of antimony, , –, , –, , Si, , –, , –, , Antimony (Sb), impurity, , –, , –, , –, , Si, , –, , –, , Figure 1.9 Antimony impurity, in n-type material., , Fig. 1.9 (using antimony as the impurity in a silicon base). Note that the four covalent bonds are still present. There is, however, an additional fifth electron due to the, impurity atom, which is unassociated with any particular covalent bond. This remaining electron, loosely bound to its parent (antimony) atom, is relatively free to, move within the newly formed n-type material. Since the inserted impurity atom has, donated a relatively “free” electron to the structure:, Diffused impurities with five valence electrons are called donor atoms., It is important to realize that even though a large number of “free” carriers have, been established in the n-type material, it is still electrically neutral since ideally the, number of positively charged protons in the nuclei is still equal to the number of, “free” and orbiting negatively charged electrons in the structure., The effect of this doping process on the relative conductivity can best be described, through the use of the energy-band diagram of Fig. 1.10. Note that a discrete energy, level (called the donor level) appears in the forbidden band with an Eg significantly, less than that of the intrinsic material. Those “free” electrons due to the added impurity sit at this energy level and have less difficulty absorbing a sufficient measure, of thermal energy to move into the conduction band at room temperature. The result, is that at room temperature, there are a large number of carriers (electrons) in the, conduction level and the conductivity of the material increases significantly. At room, temperature in an intrinsic Si material there is about one free electron for every 1012, atoms (1 to 109 for Ge). If our dosage level were 1 in 10 million (107), the ratio, (1012/107 105) would indicate that the carrier concentration has increased by a ratio of 100,0001., Energy, , Conduction band, E g = 0.05 eV (Si), 0.01 eV (Ge), Donor energy level, , E g as before, Valence band, , Figure 1.10 Effect of donor impurities on the energy band, structure., , 8, , Chapter 1, , Semiconductor Diodes
Page 20 :
p n, , p-Type Material, The p-type material is formed by doping a pure germanium or silicon crystal with, impurity atoms having three valence electrons. The elements most frequently used for, this purpose are boron, gallium, and indium. The effect of one of these elements,, boron, on a base of silicon is indicated in Fig. 1.11., , Figure 1.11 Boron impurity in, p-type material., , Note that there is now an insufficient number of electrons to complete the covalent bonds of the newly formed lattice. The resulting vacancy is called a hole and is, represented by a small circle or positive sign due to the absence of a negative charge., Since the resulting vacancy will readily accept a “free” electron:, The diffused impurities with three valence electrons are called acceptor atoms., The resulting p-type material is electrically neutral, for the same reasons described, for the n-type material., , Electron versus Hole Flow, The effect of the hole on conduction is shown in Fig. 1.12. If a valence electron acquires sufficient kinetic energy to break its covalent bond and fills the void created, by a hole, then a vacancy, or hole, will be created in the covalent bond that released, the electron. There is, therefore, a transfer of holes to the left and electrons to the, right, as shown in Fig. 1.12. The direction to be used in this text is that of conventional flow, which is indicated by the direction of hole flow., , Figure 1.12 Electron versus, hole flow., , 1.5 Extrinsic Materials—n- and p-Type, , 9
Page 21 :
p n, , Majority and Minority Carriers, In the intrinsic state, the number of free electrons in Ge or Si is due only to those few, electrons in the valence band that have acquired sufficient energy from thermal or, light sources to break the covalent bond or to the few impurities that could not be removed. The vacancies left behind in the covalent bonding structure represent our very, limited supply of holes. In an n-type material, the number of holes has not changed, significantly from this intrinsic level. The net result, therefore, is that the number of, electrons far outweighs the number of holes. For this reason:, In an n-type material (Fig. 1.13a) the electron is called the majority carrier, and the hole the minority carrier., For the p-type material the number of holes far outweighs the number of electrons, as shown in Fig. 1.13b. Therefore:, In a p-type material the hole is the majority carrier and the electron is the, minority carrier., When the fifth electron of a donor atom leaves the parent atom, the atom remaining, acquires a net positive charge: hence the positive sign in the donor-ion representation., For similar reasons, the negative sign appears in the acceptor ion., The n- and p-type materials represent the basic building blocks of semiconductor, devices. We will find in the next section that the “joining” of a single n-type material with a p-type material will result in a semiconductor element of considerable importance in electronic systems., , Acceptor ions, , Donor ions, , + ––, – +, –, +, + –, – +, , + – + –, + + –, +, – –, +, –, + +, –, – +, , Majority, carriers, , Minority, carrier, , Majority, carriers, , +, –, + –, – + +–, – + + – –+ +, + –, + + –, –, +, +, – + – + –, , n-type, , p-type, , (a), , (b), , Minority, carrier, , Figure 1.13 (a) n-type material; (b) p-type material., , 1.6 SEMICONDUCTOR DIODE, In Section 1.5 both the n- and p-type materials were introduced. The semiconductor, diode is formed by simply bringing these materials together (constructed from the, same base—Ge or Si), as shown in Fig. 1.14, using techniques to be described in, Chapter 20. At the instant the two materials are “joined” the electrons and holes in, the region of the junction will combine, resulting in a lack of carriers in the region, near the junction., This region of uncovered positive and negative ions is called the depletion region due to the depletion of carriers in this region., Since the diode is a two-terminal device, the application of a voltage across its, terminals leaves three possibilities: no bias (VD 0 V), forward bias (VD 0 V), and, reverse bias (VD 0 V). Each is a condition that will result in a response that the, user must clearly understand if the device is to be applied effectively., 10, , Chapter 1, , Semiconductor Diodes
Page 22 :
p n, , Figure 1.14 p-n junction with, no external bias., , No Applied Bias (VD 0 V), Under no-bias (no applied voltage) conditions, any minority carriers (holes) in the, n-type material that find themselves within the depletion region will pass directly into, the p-type material. The closer the minority carrier is to the junction, the greater the, attraction for the layer of negative ions and the less the opposition of the positive ions, in the depletion region of the n-type material. For the purposes of future discussions, we shall assume that all the minority carriers of the n-type material that find themselves in the depletion region due to their random motion will pass directly into the, p-type material. Similar discussion can be applied to the minority carriers (electrons), of the p-type material. This carrier flow has been indicated in Fig. 1.14 for the minority carriers of each material., The majority carriers (electrons) of the n-type material must overcome the attractive forces of the layer of positive ions in the n-type material and the shield of, negative ions in the p-type material to migrate into the area beyond the depletion region of the p-type material. However, the number of majority carriers is so large in, the n-type material that there will invariably be a small number of majority carriers, with sufficient kinetic energy to pass through the depletion region into the p-type material. Again, the same type of discussion can be applied to the majority carriers (holes), of the p-type material. The resulting flow due to the majority carriers is also shown, in Fig. 1.14., A close examination of Fig. 1.14 will reveal that the relative magnitudes of the, flow vectors are such that the net flow in either direction is zero. This cancellation of, vectors has been indicated by crossed lines. The length of the vector representing hole, flow has been drawn longer than that for electron flow to demonstrate that the magnitude of each need not be the same for cancellation and that the doping levels for, each material may result in an unequal carrier flow of holes and electrons. In summary, therefore:, In the absence of an applied bias voltage, the net flow of charge in any one, direction for a semiconductor diode is zero., 1.6 Semiconductor Diode, , 11
Page 23 :
p n, , The symbol for a diode is repeated in Fig. 1.15 with the associated n- and p-type, regions. Note that the arrow is associated with the p-type component and the bar with, the n-type region. As indicated, for VD 0 V, the current in any direction is 0 mA., , Reverse-Bias Condition (VD, Figure 1.15 No-bias conditions, for a semiconductor diode., , 0 V), , If an external potential of V volts is applied across the p-n junction such that the positive terminal is connected to the n-type material and the negative terminal is connected to the p-type material as shown in Fig. 1.16, the number of uncovered positive ions in the depletion region of the n-type material will increase due to the large, number of “free” electrons drawn to the positive potential of the applied voltage. For, similar reasons, the number of uncovered negative ions will increase in the p-type, material. The net effect, therefore, is a widening of the depletion region. This widening of the depletion region will establish too great a barrier for the majority carriers to, overcome, effectively reducing the majority carrier flow to zero as shown in Fig. 1.16., , Figure 1.16 Reverse-biased, p-n junction., , The number of minority carriers, however, that find themselves entering the depletion region will not change, resulting in minority-carrier flow vectors of the same, magnitude indicated in Fig. 1.14 with no applied voltage., The current that exists under reverse-bias conditions is called the reverse saturation current and is represented by Is., , Figure 1.17 Reverse-bias, conditions for a semiconductor, diode., , The reverse saturation current is seldom more than a few microamperes except for, high-power devices. In fact, in recent years its level is typically in the nanoampere, range for silicon devices and in the low-microampere range for germanium. The term, saturation comes from the fact that it reaches its maximum level quickly and does not, change significantly with increase in the reverse-bias potential, as shown on the diode, characteristics of Fig. 1.19 for VD 0 V. The reverse-biased conditions are depicted, in Fig. 1.17 for the diode symbol and p-n junction. Note, in particular, that the direction of Is is against the arrow of the symbol. Note also that the negative potential is, connected to the p-type material and the positive potential to the n-type material—the, difference in underlined letters for each region revealing a reverse-bias condition., , Forward-Bias Condition (VD, , 0 V), , A forward-bias or “on” condition is established by applying the positive potential to, the p-type material and the negative potential to the n-type material as shown in Fig., 1.18. For future reference, therefore:, A semiconductor diode is forward-biased when the association p-type and positive and n-type and negative has been established., , 12, , Chapter 1, , Semiconductor Diodes
Page 24 :
p n, , Figure 1.18 Forward-biased p-n, junction., , The application of a forward-bias potential VD will “pressure” electrons in the, n-type material and holes in the p-type material to recombine with the ions near the, boundary and reduce the width of the depletion region as shown in Fig. 1.18. The resulting minority-carrier flow of electrons from the p-type material to the n-type material (and of holes from the n-type material to the p-type material) has not changed, in magnitude (since the conduction level is controlled primarily by the limited number of impurities in the material), but the reduction in the width of the depletion region has resulted in a heavy majority flow across the junction. An electron of the, n-type material now “sees” a reduced barrier at the junction due to the reduced depletion region and a strong attraction for the positive potential applied to the p-type, material. As the applied bias increases in magnitude the depletion region will continue to decrease in width until a flood of electrons can pass through the junction, reID (mA), 20, 19, , Eq. (1.4), , 18, , Actual commercially, available unit, , 17, 16, 15, 14, 13, 12, , Defined polarity and, direction for graph, VD, , 11, 10, , +, , 9, , –, , ID, , 8, 7, , Forward-bias region, (V, VD > 0 V, II D > 0 mA), , 6, 5, 4, 3, 2, , Is, –40, , –30, , –20, , 1, –10, , Reverse-bias region, (VD < 0 V, ID = –Is ), , 0, 0.3, – 0.1 µ, uA, – 0.2 µ, uA, – 0.3 µ, uA, , 0.5, , 0.7, , 1, , V D (V), , No-bias, (VD = 0 V, ID = 0 mA), , – 0.4 µ, uA, , Figure 1.19 Silicon semiconductor, diode characteristics., , 1.6 Semiconductor Diode, , 13
Page 25 :
p n, , sulting in an exponential rise in current as shown in the forward-bias region of the, characteristics of Fig. 1.19. Note that the vertical scale of Fig. 1.19 is measured in, milliamperes (although some semiconductor diodes will have a vertical scale measured in amperes) and the horizontal scale in the forward-bias region has a maximum, of 1 V. Typically, therefore, the voltage across a forward-biased diode will be less, than 1 V. Note also, how quickly the current rises beyond the knee of the curve., It can be demonstrated through the use of solid-state physics that the general characteristics of a semiconductor diode can be defined by the following equation for the, forward- and reverse-bias regions:, ID Is(ekVD/TK 1), where, , (1.4), , Is reverse saturation current, k 11,600/ with 1 for Ge and 2 for Si for relatively low levels, of diode current (at or below the knee of the curve) and 1 for Ge, and Si for higher levels of diode current (in the rapidly increasing section of the curve), TK TC 273°, , A plot of Eq. (1.4) is provided in Fig. 1.19. If we expand Eq. (1.4) into the following form, the contributing component for each region of Fig. 1.19 can easily be, described:, ID IsekVD/TK Is, , Figure 1.20 Plot of e x., , For positive values of VD the first term of the equation above will grow very, quickly and overpower the effect of the second term. The result is that for positive, values of VD, ID will be positive and grow as the function y ex appearing in Fig., 1.20. At VD 0 V, Eq. (1.4) becomes ID Is(e0 1) Is(1 1) 0 mA as appearing in Fig. 1.19. For negative values of VD the first term will quickly drop off below Is, resulting in ID Is, which is simply the horizontal line of Fig. 1.19. The, break in the characteristics at VD 0 V is simply due to the dramatic change in scale, from mA to A., Note in Fig. 1.19 that the commercially available unit has characteristics that are, shifted to the right by a few tenths of a volt. This is due to the internal “body” resistance and external “contact” resistance of a diode. Each contributes to an additional, voltage at the same current level as determined by Ohm’s law (V IR). In time, as, production methods improve, this difference will decrease and the actual characteristics approach those of Eq. (1.4)., It is important to note the change in scale for the vertical and horizontal axes. For, positive values of ID the scale is in milliamperes and the current scale below the axis, is in microamperes (or possibly nanoamperes). For VD the scale for positive values is, in tenths of volts and for negative values the scale is in tens of volts., Initially, Eq. (1.4) does appear somewhat complex and may develop an unwarranted fear that it will be applied for all the diode applications to follow. Fortunately,, however, a number of approximations will be made in a later section that will negate, the need to apply Eq. (1.4) and provide a solution with a minimum of mathematical, difficulty., Before leaving the subject of the forward-bias state the conditions for conduction, (the “on” state) are repeated in Fig. 1.21 with the required biasing polarities and the, resulting direction of majority-carrier flow. Note in particular how the direction of, conduction matches the arrow in the symbol (as revealed for the ideal diode)., , Zener Region, Figure 1.21 Forward-bias, conditions for a semiconductor, diode., , Even though the scale of Fig. 1.19 is in tens of volts in the negative region, there is, a point where the application of too negative a voltage will result in a sharp change, , 14, , Chapter 1, , Semiconductor Diodes
Page 26 :
p n, , Figure 1.22 Zener region., , in the characteristics, as shown in Fig. 1.22. The current increases at a very rapid rate, in a direction opposite to that of the positive voltage region. The reverse-bias potential that results in this dramatic change in characteristics is called the Zener potential, and is given the symbol VZ., As the voltage across the diode increases in the reverse-bias region, the velocity, of the minority carriers responsible for the reverse saturation current Is will also increase. Eventually, their velocity and associated kinetic energy (WK 12mv2) will be, sufficient to release additional carriers through collisions with otherwise stable atomic, structures. That is, an ionization process will result whereby valence electrons absorb, sufficient energy to leave the parent atom. These additional carriers can then aid the, ionization process to the point where a high avalanche current is established and the, avalanche breakdown region determined., The avalanche region (VZ) can be brought closer to the vertical axis by increasing, the doping levels in the p- and n-type materials. However, as VZ decreases to very low, levels, such as 5 V, another mechanism, called Zener breakdown, will contribute to, the sharp change in the characteristic. It occurs because there is a strong electric field, in the region of the junction that can disrupt the bonding forces within the atom and, “generate” carriers. Although the Zener breakdown mechanism is a significant contributor only at lower levels of VZ, this sharp change in the characteristic at any level is, called the Zener region and diodes employing this unique portion of the characteristic, of a p-n junction are called Zener diodes. They are described in detail in Section 1.14., The Zener region of the semiconductor diode described must be avoided if the response of a system is not to be completely altered by the sharp change in characteristics in this reverse-voltage region., The maximum reverse-bias potential that can be applied before entering the, Zener region is called the peak inverse voltage (referred to simply as the PIV, rating) or the peak reverse voltage (denoted by PRV rating)., If an application requires a PIV rating greater than that of a single unit, a number of diodes of the same characteristics can be connected in series. Diodes are also, connected in parallel to increase the current-carrying capacity., , Silicon versus Germanium, Silicon diodes have, in general, higher PIV and current rating and wider temperature, ranges than germanium diodes. PIV ratings for silicon can be in the neighborhood of, 1000 V, whereas the maximum value for germanium is closer to 400 V. Silicon can, be used for applications in which the temperature may rise to about 200°C (400°F),, whereas germanium has a much lower maximum rating (100°C). The disadvantage, of silicon, however, as compared to germanium, as indicated in Fig. 1.23, is the higher, 1.6 Semiconductor Diode, , 15
Page 27 :
p n, , Figure 1.23 Comparison of Si, and Ge semiconductor diodes., , forward-bias voltage required to reach the region of upward swing. It is typically of, the order of magnitude of 0.7 V for commercially available silicon diodes and 0.3 V, for germanium diodes when rounded off to the nearest tenths. The increased offset, for silicon is due primarily to the factor in Eq. (1.4). This factor plays a part in determining the shape of the curve only at very low current levels. Once the curve starts, its vertical rise, the factor drops to 1 (the continuous value for germanium). This is, evidenced by the similarities in the curves once the offset potential is reached. The, potential at which this rise occurs is commonly referred to as the offset, threshold, or, firing potential. Frequently, the first letter of a term that describes a particular quantity is used in the notation for that quantity. However, to ensure a minimum of confusion with other terms, such as output voltage (Vo) and forward voltage (VF), the notation VT has been adopted for this book, from the word “threshold.”, In review:, VT 0.7 (Si), VT 0.3 (Ge), Obviously, the closer the upward swing is to the vertical axis, the more “ideal” the, device. However, the other characteristics of silicon as compared to germanium still, make it the choice in the majority of commercially available units., , Temperature Effects, Temperature can have a marked effect on the characteristics of a silicon semiconductor diode as witnessed by a typical silicon diode in Fig. 1.24. It has been found, experimentally that:, The reverse saturation current Is will just about double in magnitude for, every 10°C increase in temperature., 16, , Chapter 1, , Semiconductor Diodes
Page 28 :
p n, , Figure 1.24 Variation in diode, characteristics with temperature, change., , It is not uncommon for a germanium diode with an Is in the order of 1 or 2 A, at 25°C to have a leakage current of 100 A 0.1 mA at a temperature of 100°C., Current levels of this magnitude in the reverse-bias region would certainly question, our desired open-circuit condition in the reverse-bias region. Typical values of Is for, silicon are much lower than that of germanium for similar power and current levels, as shown in Fig. 1.23. The result is that even at high temperatures the levels of Is for, silicon diodes do not reach the same high levels obtained for germanium—a very important reason that silicon devices enjoy a significantly higher level of development, and utilization in design. Fundamentally, the open-circuit equivalent in the reversebias region is better realized at any temperature with silicon than with germanium., The increasing levels of Is with temperature account for the lower levels of threshold voltage, as shown in Fig. 1.24. Simply increase the level of Is in Eq. (1.4) and, note the earlier rise in diode current. Of course, the level of TK also will be increasing in the same equation, but the increasing level of Is will overpower the smaller percent change in TK. As the temperature increases the forward characteristics are actually becoming more “ideal,” but we will find when we review the specifications sheets, that temperatures beyond the normal operating range can have a very detrimental effect on the diode’s maximum power and current levels. In the reverse-bias region the, breakdown voltage is increasing with temperature, but note the undesirable increase, in reverse saturation current., , 1.7 RESISTANCE LEVELS, As the operating point of a diode moves from one region to another the resistance of, the diode will also change due to the nonlinear shape of the characteristic curve. It, will be demonstrated in the next few paragraphs that the type of applied voltage or, signal will define the resistance level of interest. Three different levels will be introduced in this section that will appear again as we examine other devices. It is therefore paramount that their determination be clearly understood., 1.7, , Resistance Levels, , 17
Page 29 :
p n, , DC or Static Resistance, The application of a dc voltage to a circuit containing a semiconductor diode will result in an operating point on the characteristic curve that will not change with time., The resistance of the diode at the operating point can be found simply by finding the, corresponding levels of VD and ID as shown in Fig. 1.25 and applying the following, equation:, VD, RD , ID, , (1.5), , The dc resistance levels at the knee and below will be greater than the resistance, levels obtained for the vertical rise section of the characteristics. The resistance levels in the reverse-bias region will naturally be quite high. Since ohmmeters typically, employ a relatively constant-current source, the resistance determined will be at a preset current level (typically, a few milliamperes)., , Figure 1.25 Determining the dc, resistance of a diode at a particular operating point., , In general, therefore, the lower the current through a diode the higher the dc, resistance level., , EXAMPLE 1.1, , Determine the dc resistance levels for the diode of Fig. 1.26 at, (a) ID 2 mA, (b) ID 20 mA, (c) VD 10 V, , Figure 1.26 Example 1.1, , Solution, (a) At ID 2 mA, VD 0.5 V (from the curve) and, VD, 0.5 V, RD , 250 , ID, 2 mA, 18, , Chapter 1, , Semiconductor Diodes
Page 30 :
p n, , (b) At ID 20 mA, VD 0.8 V (from the curve) and, VD, 0.8 V, RD , 40 , ID, 20 mA, (c) At VD 10 V, ID Is 1 A (from the curve) and, VD, 10 V, RD , 10 M, ID, 1 A, clearly supporting some of the earlier comments regarding the dc resistance levels of, a diode., , AC or Dynamic Resistance, It is obvious from Eq. 1.5 and Example 1.1 that the dc resistance of a diode is independent of the shape of the characteristic in the region surrounding the point of interest. If a sinusoidal rather than dc input is applied, the situation will change completely., The varying input will move the instantaneous operating point up and down a region, of the characteristics and thus defines a specific change in current and voltage as shown, in Fig. 1.27. With no applied varying signal, the point of operation would, be the Q-point appearing on Fig. 1.27 determined by the applied dc levels. The designation Q-point is derived from the word quiescent, which means “still or unvarying.”, , Figure 1.27 Defining the, dynamic or ac resistance., , A straight line drawn tangent to the curve through the Q-point as shown in Fig., 1.28 will define a particular change in voltage and current that can be used to determine the ac or dynamic resistance for this region of the diode characteristics. An effort should be made to keep the change in voltage and current as small as possible, and equidistant to either side of the Q-point. In equation form,, Vd, rd , Id, , where signifies a finite change in the quantity., , (1.6), , The steeper the slope, the less the value of Vd for the same change in Id and the, less the resistance. The ac resistance in the vertical-rise region of the characteristic is, therefore quite small, while the ac resistance is much higher at low current levels., In general, therefore, the lower the Q-point of operation (smaller current or, lower voltage) the higher the ac resistance., 1.7, , Resistance Levels, , Figure 1.28 Determining the ac, resistance at a Q-point., , 19
Page 31 :
p n, , EXAMPLE 1.2, , For the characteristics of Fig. 1.29:, (a) Determine the ac resistance at ID 2 mA., (b) Determine the ac resistance at ID 25 mA., (c) Compare the results of parts (a) and (b) to the dc resistances at each current level., I D (mA), , 30, , ∆ Id, , 25, , 20, ∆Vd, 15, , 10, , 5, 4, 2, , ∆ Id, , 0, , 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9, , 1, , VD (V), , ∆Vd, , Figure 1.29 Example 1.2, , Solution, (a) For ID 2 mA; the tangent line at ID 2 mA was drawn as shown in the figure, and a swing of 2 mA above and below the specified diode current was chosen., At ID 4 mA, VD 0.76 V, and at ID 0 mA, VD 0.65 V. The resulting, changes in current and voltage are, Id 4 mA 0 mA 4 mA, Vd 0.76 V 0.65 V 0.11 V, , and, and the ac resistance:, , Vd, 0.11 V, rd , 27.5 , Id, 4 mA, (b) For ID 25 mA, the tangent line at ID 25 mA was drawn as shown on the figure and a swing of 5 mA above and below the specified diode current was chosen. At ID 30 mA, VD 0.8 V, and at ID 20 mA, VD 0.78 V. The resulting changes in current and voltage are, Id 30 mA 20 mA 10 mA, Vd 0.8 V 0.78 V 0.02 V, , and, and the ac resistance is, , 20, , Chapter 1, , Vd, 0.02 V, 2 , rd , Id, 10 mA, , Semiconductor Diodes
Page 32 :
p n, , (c) For ID 2 mA, VD 0.7 V and, VD, 0.7 V, RD , 350 , ID, 2 mA, which far exceeds the rd of 27.5 ., For ID 25 mA, VD 0.79 V and, VD, 0.79 V, RD , 31.62 , ID, 25 mA, which far exceeds the rd of 2 ., We have found the dynamic resistance graphically, but there is a basic definition, in differential calculus which states:, The derivative of a function at a point is equal to the slope of the tangent line, drawn at that point., Equation (1.6), as defined by Fig. 1.28, is, therefore, essentially finding the derivative of the function at the Q-point of operation. If we find the derivative of the general equation (1.4) for the semiconductor diode with respect to the applied forward, bias and then invert the result, we will have an equation for the dynamic or ac resistance in that region. That is, taking the derivative of Eq. (1.4) with respect to the applied bias will result in, d, d, (ID) [Is(ekVD /TK 1)], dVD, dV, dID, k, , (ID, dVD, TK, , and, , Is), , following a few basic maneuvers of differential calculus. In general, ID Is in the, vertical slope section of the characteristics and, dID, k, , ID, dVD, TK, Substituting, obtain, , 1 for Ge and Si in the vertical-rise section of the characteristics, we, 11,600, 11,600, k 11,600, 1, , and at room temperature,, TK TC, so that, and, , 273° 25°, , 273° 298°, , k, 11,600, 38.93, TK, 298, dID, , 38.93ID, dVD, , Flipping the result to define a resistance ratio (R V/I) gives us, dVD, 0.026, , , dID, ID, or, , 26 mV, rd , ID, , (1.7), Ge,Si, , 1.7, , Resistance Levels, , 21
Page 33 :
p n, , The significance of Eq. (1.7) must be clearly understood. It implies that the dynamic, resistance can be found simply by substituting the quiescent value of the diode current into the equation. There is no need to have the characteristics available or to, worry about sketching tangent lines as defined by Eq. (1.6). It is important to keep, in mind, however, that Eq. (1.7) is accurate only for values of ID in the vertical-rise, section of the curve. For lesser values of ID, 2 (silicon) and the value of rd obtained must be multiplied by a factor of 2. For small values of ID below the knee of, the curve, Eq. (1.7) becomes inappropriate., All the resistance levels determined thus far have been defined by the p-n junction and do not include the resistance of the semiconductor material itself (called body, resistance) and the resistance introduced by the connection between the semiconductor material and the external metallic conductor (called contact resistance). These additional resistance levels can be included in Eq. (1.7) by adding resistance denoted, by rB as appearing in Eq. (1.8). The resistance r d, therefore, includes the dynamic resistance defined by Eq. 1.7 and the resistance rB just introduced., 26 mV, r d , ID, , rB, , ohms, , (1.8), , The factor rB can range from typically 0.1 for high-power devices to 2 for, some low-power, general-purpose diodes. For Example 1.2 the ac resistance at 25 mA, was calculated to be 2 . Using Eq. (1.7), we have, 26 mV, 26 mV, rd 1.04 , ID, 25 mA, The difference of about 1 could be treated as the contribution of rB., For Example 1.2 the ac resistance at 2 mA was calculated to be 27.5 . Using, Eq. (1.7) but multiplying by a factor of 2 for this region (in the knee of the curve, 2),, , , , , , , , 26 mV, 26 mV, rd 2 2 2(13 ) 26 , ID, 2 mA, The difference of 1.5 could be treated as the contribution due to rB., In reality, determining rd to a high degree of accuracy from a characteristic curve, using Eq. (1.6) is a difficult process at best and the results have to be treated with a, grain of salt. At low levels of diode current the factor rB is normally small enough, compared to rd to permit ignoring its impact on the ac diode resistance. At high levels of current the level of rB may approach that of rd, but since there will frequently, be other resistive elements of a much larger magnitude in series with the diode we, will assume in this book that the ac resistance is determined solely by rd and the impact of rB will be ignored unless otherwise noted. Technological improvements of recent years suggest that the level of rB will continue to decrease in magnitude and, eventually become a factor that can certainly be ignored in comparison to rd., The discussion above has centered solely on the forward-bias region. In the reverse-bias region we will assume that the change in current along the Is line is nil, from 0 V to the Zener region and the resulting ac resistance using Eq. (1.6) is sufficiently high to permit the open-circuit approximation., , Average AC Resistance, If the input signal is sufficiently large to produce a broad swing such as indicated in, Fig. 1.30, the resistance associated with the device for this region is called the average ac resistance. The average ac resistance is, by definition, the resistance deter22, , Chapter 1, , Semiconductor Diodes
Page 34 :
p n, , I D (mA), 20, , 15, , ∆ Id, , 10, , 5, , 0, , 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9, , 1, , VD (V), , ∆Vd, , Figure 1.30 Determining the average ac resistance between indicated limits., , mined by a straight line drawn between the two intersections established by the maximum and minimum values of input voltage. In equation form (note Fig. 1.30),, Vd, rav , Id, , , , (1.9), pt. to pt., , For the situation indicated by Fig. 1.30,, Id 17 mA 2 mA 15 mA, and, , Vd 0.725 V 0.65 V 0.075 V, , with, , Vd, 0.075 V, rav , 5 , Id, 15 mA, , If the ac resistance (rd) were determined at ID 2 mA its value would be more, than 5 , and if determined at 17 mA it would be less. In between the ac resistance, would make the transition from the high value at 2 mA to the lower value at 17 mA., Equation (1.9) has defined a value that is considered the average of the ac values from, 2 to 17 mA. The fact that one resistance level can be used for such a wide range of, the characteristics will prove quite useful in the definition of equivalent circuits for a, diode in a later section., As with the dc and ac resistance levels, the lower the level of currents used to, determine the average resistance the higher the resistance level., , Summary Table, Table 1.2 was developed to reinforce the important conclusions of the last few pages, and to emphasize the differences among the various resistance levels. As indicated, earlier, the content of this section is the foundation for a number of resistance calculations to be performed in later sections and chapters., 1.7, , Resistance Levels, , 23
Page 35 :
p n, , TABLE 1.2 Resistance Levels, Type, , Equation, , DC or static, , VD, RD , ID, , AC or, dynamic, , Average ac, , V, 26 mV, rd d , Id, ID, , Vd, rav , Id pt. to pt., , Special, Characteristics, , Graphical, Determination, , Defined as a, point on the, characteristics, , Defined by a, tangent line at, the Q-point, , Defined by a straight, line between limits, of operation, , 1.8 DIODE EQUIVALENT CIRCUITS, An equivalent circuit is a combination of elements properly chosen to best, represent the actual terminal characteristics of a device, system, or such in a, particular operating region., In other words, once the equivalent circuit is defined, the device symbol can be, removed from a schematic and the equivalent circuit inserted in its place without severely affecting the actual behavior of the system. The result is often a network that, can be solved using traditional circuit analysis techniques., , Piecewise-Linear Equivalent Circuit, One technique for obtaining an equivalent circuit for a diode is to approximate the, characteristics of the device by straight-line segments, as shown in Fig. 1.31. The resulting equivalent circuit is naturally called the piecewise-linear equivalent circuit. It, should be obvious from Fig. 1.31 that the straight-line segments do not result in an exact duplication of the actual characteristics, especially in the knee region. However,, the resulting segments are sufficiently close to the actual curve to establish an equivalent circuit that will provide an excellent first approximation to the actual behavior of, the device. For the sloping section of the equivalence the average ac resistance as introduced in Section 1.7 is the resistance level appearing in the equivalent circuit of Fig., 1.32 next to the actual device. In essence, it defines the resistance level of the device, when it is in the “on” state. The ideal diode is included to establish that there is only, one direction of conduction through the device, and a reverse-bias condition will re24, , Chapter 1, , Semiconductor Diodes
Page 36 :
p n, , Figure 1.31 Defining the, piecewise-linear equivalent circuit, using straight-line segments, to approximate the, characteristic curve., , +, VD, , +, , VD, VT, , –, , ID, , ID, , 0.7 V, , r av, , –, Ideal diode, , 10 Ω, , Figure 1.32 Components of the piecewise-linear equivalent circuit., , sult in the open-circuit state for the device. Since a silicon semiconductor diode does, not reach the conduction state until VD reaches 0.7 V with a forward bias (as shown, in Fig. 1.31), a battery VT opposing the conduction direction must appear in the equivalent circuit as shown in Fig. 1.32. The battery simply specifies that the voltage across, the device must be greater than the threshold battery voltage before conduction through, the device in the direction dictated by the ideal diode can be established. When conduction is established the resistance of the diode will be the specified value of rav., Keep in mind, however, that VT in the equivalent circuit is not an independent, voltage source. If a voltmeter is placed across an isolated diode on the top of a lab, bench, a reading of 0.7 V will not be obtained. The battery simply represents the horizontal offset of the characteristics that must be exceeded to establish conduction., The approximate level of rav can usually be determined from a specified operating point on the specification sheet (to be discussed in Section 1.9). For instance, for, a silicon semiconductor diode, if IF 10 mA (a forward conduction current for the, diode) at VD 0.8 V, we know for silicon that a shift of 0.7 V is required before the, characteristics rise and, Vd, rav , Id, , , , 0.8 V 0.7 V, 0.1 V, 10 , 1, 0, m, A, , 0, m, A, 1, 0 mA, pt. to pt., , as obtained for Fig. 1.30., , Simplified Equivalent Circuit, For most applications, the resistance rav is sufficiently small to be ignored in comparison to the other elements of the network. The removal of rav from the equivalent, 1.8, , Diode Equivalent Circut, , 25
Page 37 :
p n, , ID, , +, , VT = 0.7 V, , r av = 0 Ω, ID, 0, , –, , VD, , Ideal diode, , V T = 0.7 V V D, , Figure 1.33 Simplified equivalent circuit for the silicon semiconductor diode., , circuit is the same as implying that the characteristics of the diode appear as shown, in Fig. 1.33. Indeed, this approximation is frequently employed in semiconductor circuit analysis as demonstrated in Chapter 2. The reduced equivalent circuit appears in, the same figure. It states that a forward-biased silicon diode in an electronic system, under dc conditions has a drop of 0.7 V across it in the conduction state at any level, of diode current (within rated values, of course)., , Ideal Equivalent Circuit, Now that rav has been removed from the equivalent circuit let us take it a step further, and establish that a 0.7-V level can often be ignored in comparison to the applied, voltage level. In this case the equivalent circuit will be reduced to that of an ideal, diode as shown in Fig. 1.34 with its characteristics. In Chapter 2 we will see that this, approximation is often made without a serious loss in accuracy., In industry a popular substitution for the phrase “diode equivalent circuit” is diode, model—a model by definition being a representation of an existing device, object,, system, and so on. In fact, this substitute terminology will be used almost exclusively, in the chapters to follow., , Figure 1.34 Ideal diode and its characteristics., , Summary Table, For clarity, the diode models employed for the range of circuit parameters and applications are provided in Table 1.3 with their piecewise-linear characteristics. Each will, be investigated in greater detail in Chapter 2. There are always exceptions to the general rule, but it is fairly safe to say that the simplified equivalent model will be employed most frequently in the analysis of electronic systems while the ideal diode is, frequently applied in the analysis of power supply systems where larger voltages are, encountered., , 26, , Chapter 1, , Semiconductor Diodes
Page 38 :
p n, , TABLE 1.3 Diode Equivalent Circuits (Models), Type, , Conditions, , Model, , Characteristics, , Piecewise-linear model, , Simplified model, , Rnetwork rav, , Ideal device, , Rnetwork rav, Enetwork VT, , 1.9 DIODE SPECIFICATION SHEETS, Data on specific semiconductor devices are normally provided by the manufacturer, in one of two forms. Most frequently, it is a very brief description limited to perhaps, one page. Otherwise, it is a thorough examination of the characteristics using graphs,, artwork, tables, and so on. In either case, there are specific pieces of data that must, be included for proper utilization of the device. They include:, 1. The forward voltage VF (at a specified current and temperature), 2. The maximum forward current IF (at a specified temperature), 3. The reverse saturation current IR (at a specified voltage and temperature), 4. The reverse-voltage rating [PIV or PRV or V(BR), where BR comes from the term, “breakdown” (at a specified temperature)], 5. The maximum power dissipation level at a particular temperature, 6. Capacitance levels (as defined in Section 1.10), 7. Reverse recovery time trr (as defined in Section 1.11), 8. Operating temperature range, Depending on the type of diode being considered, additional data may also be, provided, such as frequency range, noise level, switching time, thermal resistance levels, and peak repetitive values. For the application in mind, the significance of the, data will usually be self-apparent. If the maximum power or dissipation rating is also, provided, it is understood to be equal to the following product:, PDmax VD ID, , (1.10), , where ID and VD are the diode current and voltage at a particular point of operation., , 1.9, , Diode Specification Sheets, , 27
Page 39 :
p n, , If we apply the simplified model for a particular application (a common occurrence), we can substitute VD VT 0.7 V for a silicon diode in Eq. (1.10) and determine the resulting power dissipation for comparison against the maximum power, rating. That is,, Pdissipated (0.7 V)ID, , Figure 1.35 Electrical characteristics of a high-voltage, low-leakage diode., , 28, , Chapter 1, , Semiconductor Diodes, , (1.11)
Page 40 :
p n, , An exact copy of the data provided for a high-voltage/low-leakage diode appears, in Figs. 1.35 and 1.36. This example would represent the expanded list of data and, characteristics. The term rectifier is applied to a diode when it is frequently used in, a rectification process to be described in Chapter 2., , Figure 1.36 Terminal characteristics of a high-voltage diode., , 1.9, , Diode Specification Sheets, , 29
Page 41 :
p n, , Specific areas of the specification sheet have been highlighted in blue with a letter identification corresponding with the following description:, A: The minimum reverse-bias voltage (PIVs) for a diode at a specified reverse, saturation current., B: Temperature characteristics as indicated. Note the use of the Celsius scale and, the wide range of utilization [recall that 32°F 0°C freezing (H2O) and, 212°F 100°C boiling (H2O)]., C: Maximum power dissipation level PD VDID 500 mW. The maximum, power rating decreases at a rate of 3.33 mW per degree increase in temperature above room temperature (25°C), as clearly indicated by the power, derating curve of Fig. 1.36., D: Maximum continuous forward current IFmax 500 mA (note IF versus temperature in Fig. 1.36)., E: Range of values of VF at IF 200 mA. Note that it exceeds VT 0.7 V for, both devices., F: Range of values of VF at IF 1.0 mA. Note in this case how the upper limits surround 0.7 V., G: At VR 20 V and a typical operating temperature IR 500 nA 0.5 A,, while at a higher reverse voltage IR drops to 5 nA 0.005 A., H: The capacitance level between terminals is about 8 pF for the diode at VR , VD 0 V (no-bias) and an applied frequency of 1 MHz., I: The reverse recovery time is 3 s for the list of operating conditions., A number of the curves of Fig. 1.36 employ a log scale. A brief investigation of, Section 11.2 should help with the reading of the graphs. Note in the top left figure, how VF increased from about 0.5 V to over 1 V as IF increased from 10 A to over, 100 mA. In the figure below we find that the reverse saturation current does change, slightly with increasing levels of VR but remains at less than 1 nA at room temperature up to VR 125 V. As noted in the adjoining figure, however, note how quickly, the reverse saturation current increases with increase in temperature (as forecasted, earlier)., In the top right figure note how the capacitance decreases with increase in reversebias voltage, and in the figure below note that the ac resistance (rd) is only about, 1 at 100 mA and increases to 100 at currents less than 1 mA (as expected from, the discussion of earlier sections)., The average rectified current, peak repetitive forward current, and peak forward, surge current as they appear on the specification sheet are defined as follows:, 1. Average rectified current. A half-wave-rectified signal (described in Section 2.8), has an average value defined by Iav 0.318Ipeak. The average current rating is, lower than the continuous or peak repetitive forward currents because a half-wave, current waveform will have instantaneous values much higher than the average, value., 2. Peak repetitive forward current. This is the maximum instantaneous value of repetitive forward current. Note that since it is at this level for a brief period of time,, its level can be higher than the continuous level., 3. Peak forward surge current. On occasion during turn-on, malfunctions, and so on,, there will be very high currents through the device for very brief intervals of time, (that are not repetitive). This rating defines the maximum value and the time interval for such surges in current level., , 30, , Chapter 1, , Semiconductor Diodes
Page 42 :
p n, , The more one is exposed to specification sheets, the “friendlier” they will become,, especially when the impact of each parameter is clearly understood for the application under investigation., , 1.10 TRANSITION AND DIFFUSION, CAPACITANCE, Electronic devices are inherently sensitive to very high frequencies. Most shunt capacitive effects that can be ignored at lower frequencies because the reactance XC , 1/2 f C is very large (open-circuit equivalent). This, however, cannot be ignored at, very high frequencies. XC will become sufficiently small due to the high value of f to, introduce a low-reactance “shorting” path. In the p-n semiconductor diode, there are, two capacitive effects to be considered. Both types of capacitance are present in the, forward- and reverse-bias regions, but one so outweighs the other in each region that, we consider the effects of only one in each region., In the reverse-bias region we have the transition- or depletion-region capacitance (CT), while in the forward-bias region we have the diffusion (CD ) or, storage capacitance., Recall that the basic equation for the capacitance of a parallel-plate capacitor is, defined by C A/d, where is the permittivity of the dielectric (insulator) between, the plates of area A separated by a distance d. In the reverse-bias region there is a depletion region (free of carriers) that behaves essentially like an insulator between the, layers of opposite charge. Since the depletion width (d) will increase with increased, reverse-bias potential, the resulting transition capacitance will decrease, as shown in, Fig. 1.37. The fact that the capacitance is dependent on the applied reverse-bias potential has application in a number of electronic systems. In fact, in Chapter 20 a, diode will be introduced whose operation is wholly dependent on this phenomenon., Although the effect described above will also be present in the forward-bias region, it is overshadowed by a capacitance effect directly dependent on the rate at, which charge is injected into the regions just outside the depletion region. The result, is that increased levels of current will result in increased levels of diffusion capacitance. However, increased levels of current result in reduced levels of associated resistance (to be demonstrated shortly), and the resulting time constant ( RC ), which, is very important in high-speed applications, does not become excessive., , C (pF), 15, , 10, C T), Reverse-bias (C, 5, , CD ), Forward-bias (C, (V), , –25, , –20, , –15, , –10, , –5, , 0, , 0.25, , 0.5, , Figure 1.37 Transition and diffusion capacitance versus applied bias for a, silicon diode., , 1.10 Transition and Diffusion Capacitance, , 31
Page 43 :
p n, , The capacitive effects described above are represented by a capacitor in parallel, with the ideal diode, as shown in Fig. 1.38. For low- or mid-frequency applications, (except in the power area), however, the capacitor is normally not included in the, diode symbol., Figure 1.38 Including the effect, of the transition or diffusion, capacitance on the semiconductor, diode., , 1.11 REVERSE RECOVERY TIME, There are certain pieces of data that are normally provided on diode specification, sheets provided by manufacturers. One such quantity that has not been considered yet, is the reverse recovery time, denoted by trr . In the forward-bias state it was shown, earlier that there are a large number of electrons from the n-type material progressing through the p-type material and a large number of holes in the n-type—a requirement for conduction. The electrons in the p-type and holes progressing through, the n-type material establish a large number of minority carriers in each material. If, the applied voltage should be reversed to establish a reverse-bias situation, we would, ideally like to see the diode change instantaneously from the conduction state to the, nonconduction state. However, because of the large number of minority carriers in, each material, the diode current will simply reverse as shown in Fig. 1.39 and stay at, this measurable level for the period of time ts (storage time) required for the minority carriers to return to their majority-carrier state in the opposite material. In essence,, the diode will remain in the short-circuit state with a current Ireverse determined by, the network parameters. Eventually, when this storage phase has passed, the current, will reduce in level to that associated with the nonconduction state. This second period of time is denoted by tt (transition interval). The reverse recovery time is the sum, of these two intervals: trr ts tt. Naturally, it is an important consideration in highspeed switching applications. Most commercially available switching diodes have a, trr in the range of a few nanoseconds to 1 s. Units are available, however, with a trr, of only a few hundred picoseconds (1012)., ID, Change of state (on, required at t = t 1, , I forward, , off), , Desired response, t1, , t, , I reverse, ts, , tt, t rr, , Figure 1.39 Defining the, reverse recovery time., , 1.12 SEMICONDUCTOR DIODE, NOTATION, The notation most frequently used for semiconductor diodes is provided in Fig. 1.40., For most diodes any marking such as a dot or band, as shown in Fig. 1.40, appears, at the cathode end. The terminology anode and cathode is a carryover from vacuumtube notation. The anode refers to the higher or positive potential, and the cathode, refers to the lower or negative terminal. This combination of bias levels will result in, a forward-bias or “on” condition for the diode. A number of commercially available, semiconductor diodes appear in Fig. 1.41. Some details of the actual construction of, devices such as those appearing in Fig. 1.41 are provided in Chapters 12 and 20., 32, , Chapter 1, , Semiconductor Diodes
Page 44 :
p n, , Anode, p, n, , or •, K, etc., Cathode, , Figure 1.40 Semiconductor diode notation., , Figure 1.41 Various types of junction diodes. [(a) Courtesy of Motorola Inc.;, and (b) and (c) Courtesy International Rectifier Corporation.], , 1.13 DIODE TESTING, The condition of a semiconductor diode can be determined quickly using (1) a digital display meter (DDM) with a diode checking function, (2) the ohmmeter section of, a multimeter, or (3) a curve tracer., , Diode Checking Function, A digital display meter with a diode checking capability appears in Fig. 1.42. Note, the small diode symbol as the bottom option of the rotating dial. When set in this position and hooked up as shown in Fig. 1.43a, the diode should be in the “on” state, and the display will provide an indication of the forward-bias voltage such as 0.67 V, (for Si). The meter has an internal constant current source (about 2 mA) that will define the voltage level as indicated in Fig. 1.43b. An OL indication with the hookup, of Fig. 1.43a reveals an open (defective) diode. If the leads are reversed, an OL indication should result due to the expected open-circuit equivalence for the diode. In, general, therefore, an OL indication in both directions is an indication of an open or, defective diode., 1.13, , Diode Testing, , 33
Page 45 :
p n, , Figure 1.42 Digital display, meter with diode checking, capability. (Courtesy, Computronics Technology, Inc.), , Figure 1.43 Checking a diode, in the forward-bias state., , Ohmmeter Testing, In Section 1.7 we found that the forward-bias resistance of a semiconductor diode is, quite low compared to the reverse-bias level. Therefore, if we measure the resistance, of a diode using the connections indicated in Fig. 1.44a, we can expect a relatively, low level. The resulting ohmmeter indication will be a function of the current established through the diode by the internal battery (often 1.5 V) of the ohmmeter circuit., The higher the current, the less the resistance level. For the reverse-bias situation the, reading should be quite high, requiring a high resistance scale on the meter, as indicated in Fig. 1.44b. A high resistance reading in both directions obviously indicates, an open (defective device) condition, while a very low resistance reading in both directions will probably indicate a shorted device., , Curve Tracer, Figure 1.44 Checking a diode, with an ohmmeter., , The curve tracer of Fig. 1.45 can display the characteristics of a host of devices, including the semiconductor diode. By properly connecting the diode to the test panel, at the bottom center of the unit and adjusting the controls, the display of Fig. 1.46, , 34, , Chapter 1, , Semiconductor Diodes
Page 46 :
p n, , Figure 1.45 Curve tracer., (Courtesy of Tektronix, Inc.), , Figure 1.46 Curve tracer, response to 1N4007 silicon diode., , can be obtained. Note that the vertical scaling is 1 mA/div, resulting in the levels indicated. For the horizontal axis the scaling is 100 mV/div, resulting in the voltage levels indicated. For a 2-mA level as defined for a DDM, the resulting voltage would be, about 625 mV 0.625 V. Although the instrument initially appears quite complex,, the instruction manual and a few moments of exposure will reveal that the desired results can usually be obtained without an excessive amount of effort and time. The, same instrument will appear on more than one occasion in the chapters to follow as, we investigate the characteristics of the variety of devices., , 1.14 ZENER DIODES, The Zener region of Fig. 1.47 was discussed in some detail in Section 1.6. The characteristic drops in an almost vertical manner at a reverse-bias potential denoted VZ., The fact that the curve drops down and away from the horizontal axis rather than up, and away for the positive VD region reveals that the current in the Zener region has, a direction opposite to that of a forward-biased diode., 1.14, , Zener Diodes, , Figure 1.47 Reviewing the, Zener region., , 35
Page 47 :
p n, , Figure 1.48 Conduction direction: (a) Zener diode; (b) semiconductor diode., , Figure 1.49 Zener equivalent, circuit: (a) complete; (b) approximate., , This region of unique characteristics is employed in the design of Zener diodes,, which have the graphic symbol appearing in Fig. 1.48a. Both the semiconductor diode, and zener diode are presented side by side in Fig. 1.48 to ensure that the direction of, conduction of each is clearly understood together with the required polarity of the applied voltage. For the semiconductor diode the “on” state will support a current in the, direction of the arrow in the symbol. For the Zener diode the direction of conduction, is opposite to that of the arrow in the symbol as pointed out in the introduction to this, section. Note also that the polarity of VD and VZ are the same as would be obtained, if each were a resistive element., The location of the Zener region can be controlled by varying the doping levels., An increase in doping, producing an increase in the number of added impurities, will, decrease the Zener potential. Zener diodes are available having Zener potentials of, 1.8 to 200 V with power ratings from 14 to 50 W. Because of its higher temperature, and current capability, silicon is usually preferred in the manufacture of Zener diodes., The complete equivalent circuit of the Zener diode in the Zener region includes, a small dynamic resistance and dc battery equal to the Zener potential, as shown in, Fig. 1.49. For all applications to follow, however, we shall assume as a first approximation that the external resistors are much larger in magnitude than the Zener-equivalent resistor and that the equivalent circuit is simply the one indicated in Fig. 1.49b., A larger drawing of the Zener region is provided in Fig. 1.50 to permit a description of the Zener nameplate data appearing in Table 1.4 for a 10-V, 500-mW, 20%, diode. The term nominal associated with VZ indicates that it is a typical average value., Since this is a 20% diode, the Zener potential can be expected to vary as 10 V 20%, , Figure 1.50 Zener test, characteristics., , TABLE 1.4 Electrical Characteristics (25°C Ambient Temperature Unless Otherwise Noted), Zener, Voltage, Nominal,, VZ, (V), , Test, Current,, IZT, (mA), , Max, Dynamic, Impedance,, ZZT at IZT, (), , 10, , 12.5, , 8.5, , 36, , Chapter 1, , Maximum, Knee, Impedance,, ZZK at IZK, () (mA), 700, , Maximum, Reverse, Current,, IR at VR, ( A), , Test, Voltage,, VR, (V), , Maximum, Regulator, Current,, IZM, (mA), , 10, , 7.2, , 32, , 0.25, , Semiconductor Diodes, , Typical, Temperature, Coefficient, (%/°C), 0.072
Page 48 :
p n, , or from 8 to 12 V in its range of application. Also available are 10% and 5% diodes, with the same specifications. The test current IZT is the current defined by the 14 power, level, and ZZT is the dynamic impedance at this current level. The maximum knee impedance occurs at the knee current of IZK. The reverse saturation current is provided, at a particular potential level, and IZM is the maximum current for the 20% unit., The temperature coefficient reflects the percent change in VZ with temperature. It, is defined by the equation, VZ, 100%, TC , VZ (T1 T0), , %/°C, , (1.12), , where VZ is the resulting change in Zener potential due to the temperature variation. Note in Fig. 1.51a that the temperature coefficient can be positive, negative, or, even zero for different Zener levels. A positive value would reflect an increase in VZ, with an increase in temperature, while a negative value would result in a decrease in, value with increase in temperature. The 24-V, 6.8-V, and 3.6-V levels refer to three, Zener diodes having these nominal values within the same family of Zeners. The curve, for the 10-V Zener would naturally lie between the curves of the 6.8-V and 24-V devices. Returning to Eq. (1.12), T0 is the temperature at which VZ is provided (normally room temperature—25°C), and T1 is the new level. Example 1.3 will demonstrate the use of Eq. (1.12)., , Temperature coefficient, versus Zener current, , Dynamic impedence, versus Zener current, , +0.08, , 24 V, , +0.04, , 6.8 V, , Dynamic impedance, ZZ – ( Ω ), , Temperature coefficient – TC (%/˚C), , +0.12, , 0, – 0.04, 3.6 V, – 0.08, , 1 kΩ, 500, 200, 100, 50, 3.6 V, , 20, 10, 5, , 24 V, , 2, – 0.12, 0.01 0.05 0.1, , 0.5 1, , 5 10, , 50 100, , 1, 0.1 0.2 0.5 1, , Zener current, IZ – (mA), , 2, , 6.8 V, 5 10 20 50 100, , Zener current, IZ – (mA), , (a), , (b), , Figure 1.51 Electrical characteristics for a 10-V, 500-mW Zener diode., , Determine the nominal voltage for the Zener diode of Table 1.4 at a temperature of, 100°C., , EXAMPLE 1.3, , Solution, From Eq. 1.12,, T VZ, VZ C, (T1 T0), 100, 1.14, , Zener Diodes, , 37
Page 49 :
p n, , Substitution values from Table 1.4 yield, (0.072)(10 V), VZ (100°C 25°C), 100, (0.0072)(75), 0.54 V, and because of the positive temperature coefficient, the new Zener potential, defined, by VZ, is, VZ VZ, , 0.54 V, , 10.54 V, The variation in dynamic impedance (fundamentally, its series resistance) with, current appears in Fig. 1.51b. Again, the 10-V Zener appears between the 6.8-V and, 24-V Zeners. Note that the heavier the current (or the farther up the vertical rise you, are in Fig. 1.47), the less the resistance value. Also note that as you drop below the, knee of the curve, the resistance increases to significant levels., The terminal identification and the casing for a variety of Zener diodes appear in, Fig. 1.52. Figure 1.53 is an actual photograph of a variety of Zener devices. Note that, their appearance is very similar to the semiconductor diode. A few areas of application for the Zener diode will be examined in Chapter 2., , Figure 1.52 Zener terminal, identification and symbols., , Figure 1.53 Zener diodes., (Courtesy Siemens Corporation.), , 1.15 LIGHT-EMITTING DIODES, The increasing use of digital displays in calculators, watches, and all forms of instrumentation has contributed to the current extensive interest in structures that will, emit light when properly biased. The two types in common use today to perform this, function are the light-emitting diode (LED) and the liquid-crystal display (LCD). Since, the LED falls within the family of p-n junction devices and will appear in some of, 38, , Chapter 1, , Semiconductor Diodes
Page 50 :
p n, , the networks in the next few chapters, it will be introduced in this chapter. The LCD, display is described in Chapter 20., As the name implies, the light-emitting diode (LED) is a diode that will give off, visible light when it is energized. In any forward-biased p-n junction there is, within, the structure and primarily close to the junction, a recombination of holes and electrons. This recombination requires that the energy possessed by the unbound free electron be transferred to another state. In all semiconductor p-n junctions some of this, energy will be given off as heat and some in the form of photons. In silicon and germanium the greater percentage is given up in the form of heat and the emitted light, is insignificant. In other materials, such as gallium arsenide phosphide (GaAsP) or, gallium phosphide (GaP), the number of photons of light energy emitted is sufficient, to create a very visible light source., The process of giving off light by applying an electrical source of energy is, called electroluminescence., As shown in Fig. 1.54 with its graphic symbol, the conducting surface connected, to the p-material is much smaller, to permit the emergence of the maximum number, of photons of light energy. Note in the figure that the recombination of the injected, carriers due to the forward-biased junction results in emitted light at the site of recombination. There may, of course, be some absorption of the packages of photon energy in the structure itself, but a very large percentage are able to leave, as shown in, the figure., , Figure 1.54 (a) Process of, electroluminescence in the LED;, (b) graphic symbol., , The appearance and characteristics of a subminiature high-efficiency solid-state, lamp manufactured by Hewlett-Packard appears in Fig. 1.55. Note in Fig. 1.55b that, the peak forward current is 60 mA, with 20 mA the typical average forward current., The test conditions listed in Fig. 1.55c, however, are for a forward current of 10 mA., The level of VD under forward-bias conditions is listed as VF and extends from 2.2, to 3 V. In other words, one can expect a typical operating current of about 10 mA at, 2.5 V for good light emission., Two quantities yet undefined appear under the heading Electrical/Optical Characteristics at TA 25°C. They are the axial luminous intensity (IV) and the luminous, efficacy ( v). Light intensity is measured in candela. One candela emits a light flux, of 4 lumens and establishes an illumination of 1 footcandle on a 1-ft2 area 1 ft from, the light source. Even though this description may not provide a clear understanding, of the candela as a unit of measure, its level can certainly be compared between similar devices. The term efficacy is, by definition, a measure of the ability of a device, to produce a desired effect. For the LED this is the ratio of the number of lumens, generated per applied watt of electrical energy. The relative efficiency is defined by, 1.15, , Light-Emitting Diodes, , 39
Page 51 :
p n, , the luminous intensity per unit current, as shown in Fig. 1.55g. The relative intensity, of each color versus wavelength appears in Fig. 1.55d., Since the LED is a p-n junction device, it will have a forward-biased characteristic, (Fig. 1.55e) similar to the diode response curves. Note the almost linear increase in relative luminous intensity with forward current (Fig. 1.55f). Figure 1.55h reveals that the, longer the pulse duration at a particular frequency, the lower the permitted peak current, (after you pass the break value of tp). Figure 1.55i simply reveals that the intensity is, greater at 0° (or head on) and the least at 90° (when you view the device from the side)., , Figure 1.55 Hewlett-Packard subminiature high-efficiency red solid-state lamp: (a) appearance;, (b) absolute maximum ratings; (c) electrical/optical characteristics; (d) relative intensity versus wavelength; (e) forward current versus forward voltage; (f) relative luminous intensity versus forward current; (g) relative efficiency versus peak current; (h) maximum peak current versus pulse duration;, (i) relative luminous intensity versus angular displacement. (Courtesy Hewlett-Packard Corporation.), , 40, , Chapter 1, , Semiconductor Diodes
Page 52 :
p n, , 1.0, Relative intensity, , Green, , TA = 25˚C, , GaAsP Red, , Yellow, , High efficiency, Red, 0.5, , 0, 500, , 550, , 600, , 650, Wavelength–nm, , 700, , 750, , (d), , 20, , 15, , 10, , 5, , 2.0, , 1.0, , 0, 0, , 0.5, , 1.0 1.5 2.0 2.5, , 3.0, , 0, , 5, , VF – Forward voltage – V, , 20, , 0, , 10, , 20, , 30, , 40, , 50, , Ipeak – Peak current – mA, , (f), , (g), , 60, , 5, tp, , 4, , 20˚, 40˚, , 0.6, , Hz, 100, Hz, 300, z, 1 kH, , 10, 100, 1000, tp – Pulse duration – µs, , 0.8, , 60˚, 70˚, 80˚, , 1, 1.0, , 0˚, , 50˚, , T, z, 3 kH, z, 10 kH, , –, , 2, , 10˚, , 30˚, , 3, , z, 30 kH, Hz, , Idc max, , 15, , 6, , 100 k, , Ratio of maximum tolerable, peak current, to maximum tolerable, dc current, , 10, , 1.6, 1.5, 1.4, 1.3, 1.2, 1.1, 1.0, 0.9, 0.8, 0.7, 0.6, , IF – Forward current – mA, , (e), , Ipeak max, , Relative efficiency, (normalized at 10 mA dc), , Relative luminous intensity, (normalized at 10 mA), , IF – Forward current – mA, , TA = 25˚C, , 0, , TA = 25˚C, , 3.0, , 0.4, 0.2, , 90˚, , 10,000, , (h), , 20˚ 40˚, , 60˚ 80˚ 100˚, , (i), , Figure 1.55 Continued., , 1.15, , Light-Emitting Diodes, , 41
Page 53 :
p n, , LED displays are available today in many different sizes and shapes. The lightemitting region is available in lengths from 0.1 to 1 in. Numbers can be created by, segments such as shown in Fig. 1.56. By applying a forward bias to the proper p-type, material segment, any number from 0 to 9 can be displayed., , Figure 1.56 Litronix segment display., , There are also two-lead LED lamps that contain two LEDs, so that a reversal in, biasing will change the color from green to red, or vice versa. LEDs are presently, available in red, green, yellow, orange, and white, and white with blue soon to be, commercially available. In general, LEDs operate at voltage levels from 1.7 to 3.3 V,, which makes them completely compatible with solid-state circuits. They have a fast, response time (nanoseconds) and offer good contrast ratios for visibility. The power, requirement is typically from 10 to 150 mW with a lifetime of 100,000 hours. Their, semiconductor construction adds a significant ruggedness factor., , 1.16 DIODE ARRAYS—INTEGRATED, CIRCUITS, The unique characteristics of integrated circuits will be introduced in Chapter 12., However, we have reached a plateau in our introduction to electronic circuits that permits at least a surface examination of diode arrays in the integrated-circuit package., You will find that the integrated circuit is not a unique device with characteristics totally different from those we examine in these introductory chapters. It is simply a, packaging technique that permits a significant reduction in the size of electronic systems. In other words, internal to the integrated circuit are systems and discrete devices that were available long before the integrated circuit as we know it today became a reality., One possible array appears in Fig. 1.57. Note that eight diodes are internal to the, diode array. That is, in the container shown in Fig. 1.58 there are diodes set in a single silicon wafer that have all the anodes connected to pin 1 and the cathodes of each, to pins 2 through 9. Note in the same figure that pin 1 can be determined as being to, the left of the small projection in the case if we look from the bottom toward the case., The other numbers then follow in sequence. If only one diode is to be used, then only, pins 1 and 2 (or any number from 3 to 9) would be used. The remaining diodes would, be left hanging and not affect the network to which pins 1 and 2 are connected., Another diode array appears in Fig. 1.59 (see page 44). In this case the package, is different but the numbering sequence appears in the outline. Pin 1 is the pin directly above the small indentation as you look down on the device., 42, , Chapter 1, , Semiconductor Diodes
Page 54 :
p n, , Figure 1.57 Monolithic diode array., , 1.17 PSPICE WINDOWS, The computer has now become such an integral part of the electronics industry that, the capabilities of this working “tool” must be introduced at the earliest possible opportunity. For those students with no prior computer experience there is a common, initial fear of this seemingly complicated powerful system. With this in mind the computer analysis of this book was designed to make the computer system more “friendly”, by revealing the relative ease with which it can be applied to perform some very help1.16 Diode Arrays — Integrated Circuits, , 43
Page 55 :
p n, , Figure 1.58 Package outline, TO-96 for a diode array. All, dimensions are in inches., , TO-116-2 Outline, 0.785", Connection Diagrams, FSA2500M, , 1, , 7, , 1, , 8, , 14, , 0.271", 2, , 3, , 4, , 5, , 6, , 7, , 8, , 9, , 0.310", , 10, 0.200", max., Seating, plane, , Notes:, Alloy 42 pins, tin plated, Gold plated pins available, Hermetically sealed ceramic, package, , Figure 1.59 Monolithic diode array. All dimensions are in inches., , ful and special tasks in a minimum amount of time with a high degree of accuracy., The content was written with the assumption that the reader has no prior computer, experience or exposure to the terminology to be applied. There is also no suggestion, that the content of this book is sufficient to permit a complete understanding of the, “hows” and “whys” that will surface. The purpose here is solely to introduce some, of the terminology, discuss a few of its capabilities, reveal the possibilities available,, touch on some of its limitations, and demonstrate its versatility with a number of carefully chosen examples., In general, the computer analysis of electronic systems can take one of two approaches: using a language such as BASIC, Fortran, Pascal, or C; or utilizing a software package such as PSpice, MicroCap II, Breadboard, or Circuit Master, to name, a few. A language, through its symbolic notation, forms a bridge between the user, and the computer that permits a dialogue between the two for establishing the operations to be performed., In earlier editions of this text, the chosen language was BASIC, primarily because, it uses a number of familiar words and phrases from the English language that in, themselves reveal the operation to be performed. When a language is employed to analyze a system, a program is developed that sequentially defines the operations to be, performed—in much the same order in which we perform the same analysis in longhand. As with the longhand approach, one wrong step and the result obtained can be, completely meaningless. Programs typically develop with time and application as, more efficient paths toward a solution become obvious. Once established in its “best”, form it can be cataloged for future use. The important advantage of the language approach is that a program can be tailored to meet all the special needs of the user. It, permits innovative “moves” by the user that can result in printouts of data in an informative and interesting manner., The alternative approach referred to above utilizes a software package to perform, the desired investigation. A software package is a program written and tested over a, 44, , Chapter 1, , Semiconductor Diodes
Page 56 :
p n, , period of time designed to perform a particular type of analysis or synthesis in an efficient manner with a high level of accuracy., The package itself cannot be altered by the user, and its application is limited to the, operations built into the system. A user must adjust his or her desire for output information to the range of possibilities offered by the package. In addition, the user must, input information exactly as requested by the package or the data may be misinterpreted., The software package chosen for this book is PSpice.* PSpice currently is available in, two forms: DOS and Windows. Although DOS format was the first introduced, the Windows version is the most popular today. The Windows version employed in this text is, 8.0, the latest available. A photograph of a complete Design Center package appears in, Fig. 1.60 with the 8.0 CD-ROM version. It is also available in 3.5 diskettes. A more, sophisticated version referred to simply as SPICE is finding widespread application in, industry., , Figure 1.60 PSpice Design, package. (Courtesy of the, OrCAD-MicroSim Corporation.), , In total, therefore, a software package is “packaged” to perform a specific series, of calculations and operations and to provide the results in a defined format. A language permits an expanded level of flexibility but also fails to benefit from the extensive testing and research normally devoted to the development of a “trusted” package. The user must define which approach best fits the needs of the moment. Obviously,, if a package exists for the desired analysis or synthesis, it should be considered before turning to the many hours required to develop a reliable, efficient program. In, addition, one may acquire the data needed for a particular analysis from a software, package and then turn to a language to define the format of the output. In many ways,, the two approaches go hand in hand. If one is to depend on computer analysis on a, continuing basis, knowledge of the use and limits of both languages and software, packages is a necessity. The choice of which language or software package to become, familiar with is primarily a function of the area of investigation. Fortunately, however, a fluent knowledge of one language or a particular software package will usually help the user become familiar with other languages and software packages. There, is a similarity in purpose and procedures that ease the transition from one approach, to another., When using PSpice Windows, the network is first drawn on the screen followed, by an analysis dictated by the needs of the user. This text will be using Version 8.0,, though the differences between this and earlier Windows versions are so few and, relatively minor for this level of application that one should not be concerned if using an earlier edition. The first step, of course, is to install PSpice into the hard-disk, *PSpice is a registered trademark of the OrCAD-MicroSim Corporation., , 1.17 PSpice Windows, , 45
Page 57 :
p n, , memory of your computer following the directions provided by MicroSim. Next,, the Schematics screen must be obtained using a control mechanism such as, Windows 95. Once established, the elements for the network must be obtained and, placed on the screen to build the network. In this text, the procedure for each element, will be described following the discussion of the characteristics and analysis of each, device., Since we have just finished covering the diode in detail, the procedure for finding the diodes stored in the library will be introduced along with the method for placing them on the screen. The next chapter will introduce the procedure for analyzing, a complete network with diodes using PSpice. There are several ways to proceed, but, the most direct path is to click on the picture symbol with the binoculars on the top, right of the schematics screen. As you bring the marker close to the box using the, mouse, a message Get New Part will be displayed. Left click on the symbol and a, Part Browser Basic dialog box will appear. By choosing Libraries, a Library, Browser dialog box will appear and the EVAL.slb library should be chosen. When, selected, all available parts in this library will appear in the Part listing. Next, scroll, the Part list and choose the D1N4148 diode. The result is that the Part Name will, appear above and the Description will indicate it is a diode. Once set, click OK and, the Part Browser Basic dialog box will reappear with the full review of the chosen, element. To place the device on the screen and close the dialog box, simply click on, the Place & Close option. The result is that the diode will appear on the screen and, can be put in place with a left click of the mouse. Once located, two labels will appear—one indicating how any diodes have been placed (D1, D2, D3, and so on) and, the other the name of the chosen diode (D1N4148). The same diode can be placed in, other places on the same screen by simply moving the pointer and left clicking the, mouse. The process can be ended by a single right click of the mouse. Any of the, diodes can be removed by simply clicking on them to make them red and pressing, the Delete key. If preferred, the Edit choice of the menu bar at the top of the screen, also can be chosen, followed by using the Delete command., Another path for obtaining an element is to choose Draw on the menu bar, followed by Get New Part. Once chosen, the Part Browser Basic dialog box will appear as before and the same procedure can be followed. Now that we know the, D1N4148 diode exists, it can be obtained directly once the Part Browser Basic dialog box appears. Simply type D1N4148 in the Part Name box, followed by Place, & Close, and the diode will appear on the screen., If a diode has to be moved, simply left click on it once, until it turns red. Then,, click on it again and hold the clicker down on the mouse. At the same time, move the, diode to any location you prefer and, when set, lift up on the clicker. Remember that, anything in red can be operated on. To remove the red status, simply remove the, pointer from the element and click it once. The diode will turn green and blue, indicating that its location and associated information is set in memory. For all the above, and for the chapters to follow, if you happen to have a monochromatic (black-andwhite) screen, you will simply have to remember whether the device is in the active, state., If the label or parameters of the diode are to be changed, simply click on the element once (to make it red) and choose Edit, followed by Model. An Edit Model, dialog box will appear with a choice of changing the model reference (D1N4148),, the text associated with each parameter, or the parameters that define the characteristics of the diode., As mentioned above, additional comments regarding use of the diode will be made, in the chapters to follow. For the moment, we are at least aware of how to find and, place an element on the screen. If time permits, review the other elements available, within the various libraries to prepare yourself for the work to follow., , 46, , Chapter 1, , Semiconductor Diodes
Page 58 :
p n, , § 1.2 Ideal Diode, , PROBLEMS, , 1. Describe in your own words the meaning of the word ideal as applied to a device or system., 2. Describe in your own words the characteristics of the ideal diode and how they determine the, on and off states of the device. That is, describe why the short-circuit and open-circuit equivalents are appropriate., 3. What is the one important difference between the characteristics of a simple switch and those, of an ideal diode?, , § 1.3 Semiconductor Materials, 4. In your own words, define semiconductor, resistivity, bulk resistance, and ohmic contact resistance., 5. (a) Using Table 1.1, determine the resistance of a silicon sample having an area of 1 cm2 and, a length of 3 cm., (b) Repeat part (a) if the length is 1 cm and the area 4 cm2., (c) Repeat part (a) if the length is 8 cm and the area 0.5 cm2., (d) Repeat part (a) for copper and compare the results., 6. Sketch the atomic structure of copper and discuss why it is a good conductor and how its structure is different from germanium and silicon., 7. In your own words, define an intrinsic material, a negative temperature coefficient, and covalent bonding., 8. Consult your reference library and list three materials that have a negative temperature coefficient and three that have a positive temperature coefficient., , § 1.4 Energy Levels, 9. How much energy in joules is required to move a charge of 6 C through a difference in potential of 3 V?, 10. If 48 eV of energy is required to move a charge through a potential difference of 12 V, determine the charge involved., 11. Consult your reference library and determine the level of Eg for GaP and ZnS, two semiconductor materials of practical value. In addition, determine the written name for each material., , § 1.5 Extrinsic Materials—n- and p-Type, 12. Describe the difference between n-type and p-type semiconductor materials., 13. Describe the difference between donor and acceptor impurities., 14. Describe the difference between majority and minority carriers., 15. Sketch the atomic structure of silicon and insert an impurity of arsenic as demonstrated for silicon in Fig. 1.9., 16. Repeat Problem 15 but insert an impurity of indium., 17. Consult your reference library and find another explanation of hole versus electron flow. Using both descriptions, describe in your own words the process of hole conduction., , § 1.6 Semiconductor Diode, 18. Describe in your own words the conditions established by forward- and reverse-bias conditions, on a p-n junction diode and how the resulting current is affected., 19. Describe how you will remember the forward- and reverse-bias states of the p-n junction diode., That is, how you will remember which potential (positive or negative) is applied to which terminal?, 20. Using Eq. (1.4), determine the diode current at 20°C for a silicon diode with Is 50 nA and, an applied forward bias of 0.6 V., Problems, , 47
Page 59 :
p n, , 21. Repeat Problem 20 for T 100°C (boiling point of water). Assume that Is has increased to, 5.0 A., 22. (a) Using Eq. (1.4), determine the diode current at 20°C for a silicon diode with Is 0.1 A, at a reverse-bias potential of 10 V., (b) Is the result expected? Why?, 23. (a) Plot the function y ex for x from 0 to 5., (b) What is the value of y ex at x 0?, (c) Based on the results of part (b), why is the factor 1 important in Eq. (1.4)?, 24. In the reverse-bias region the saturation current of a silicon diode is about 0.1 A (T 20°C)., Determine its approximate value if the temperature is increased 40°C., 25. Compare the characteristics of a silicon and a germanium diode and determine which you would, prefer to use for most practical applications. Give some details. Refer to a manufacturer’s listing and compare the characteristics of a germanium and a silicon diode of similar maximum, ratings., 26. Determine the forward voltage drop across the diode whose characteristics appear in Fig. 1.24, at temperatures of 75°C, 25°C, 100°C, and 200°C and a current of 10 mA. For each temperature, determine the level of saturation current. Compare the extremes of each and comment, on the ratio of the two., , § 1.7 Resistance Levels, 27. Determine the static or dc resistance of the commercially available diode of Fig. 1.19 at a forward current of 2 mA., 28. Repeat Problem 26 at a forward current of 15 mA and compare results., 29. Determine the static or dc resistance of the commercially available diode of Fig. 1.19 at a reverse voltage of 10 V. How does it compare to the value determined at a reverse voltage of, 30 V?, 30. (a) Determine the dynamic (ac) resistance of the diode of Fig. 1.29 at a forward current of 10, mA using Eq. (1.6)., (b) Determine the dynamic (ac) resistance of the diode of Fig. 1.29 at a forward current of 10, mA using Eq. (1.7)., (c) Compare solutions of parts (a) and (b)., 31. Calculate the dc and ac resistance for the diode of Fig. 1.29 at a forward current of 10 mA and, compare their magnitudes., 32. Using Eq. (1.6), determine the ac resistance at a current of 1 mA and 15 mA for the diode of, Fig. 1.29. Compare the solutions and develop a general conclusion regarding the ac resistance, and increasing levels of diode current., 33. Using Eq. (1.7), determine the ac resistance at a current of 1 mA and 15 mA for the diode of, Fig. 1.19. Modify the equation as necessary for low levels of diode current. Compare to the solutions obtained in Problem 32., 34. Determine the average ac resistance for the diode of Fig. 1.19 for the region between 0.6 and, 0.9 V., 35. Determine the ac resistance for the diode of Fig. 1.19 at 0.75 V and compare to the average ac, resistance obtained in Problem 34., , § 1.8 Diode Equivalent Circuits, 36. Find the piecewise-linear equivalent circuit for the diode of Fig. 1.19. Use a straight line segment that intersects the horizontal axis at 0.7 V and best approximates the curve for the region, greater than 0.7 V., 37. Repeat Problem 36 for the diode of Fig. 1.29., , 48, , Chapter 1, , Semiconductor Diodes
Page 60 :
p n, , § 1.9 Diode Specification Sheets, * 38. Plot IF versus VF using linear scales for the diode of Fig. 1.36. Note that the provided graph, employs a log scale for the vertical axis (log scales are covered in sections 11.2 and 11.3)., 39. Comment on the change in capacitance level with increase in reverse-bias potential for the diode, of Fig. 1.36., 40. Does the reverse saturation current of the diode of Fig. 1.36 change significantly in magnitude, for reverse-bias potentials in the range 25 to 100 V?, * 41. For the diode of Fig. 1.36 determine the level of IR at room temperature (25°C) and the boiling point of water (100°C). Is the change significant? Does the level just about double for every, 10°C increase in temperature?, 42. For the diode of Fig. 1.36 determine the maximum ac (dynamic) resistance at a forward current of 0.1, 1.5, and 20 mA. Compare levels and comment on whether the results support conclusions derived in earlier sections of this chapter., 43. Using the characteristics of Fig. 1.36, determine the maximum power dissipation levels for the, diode at room temperature (25°C) and 100°C. Assuming that VF remains fixed at 0.7 V, how, has the maximum level of IF changed between the two temperature levels?, 44. Using the characteristics of Fig. 1.36, determine the temperature at which the diode current will, be 50% of its value at room temperature (25°C)., , § 1.10 Transition and Diffusion Capacitance, * 45. (a) Referring to Fig. 1.37, determine the transition capacitance at reverse-bias potentials of 25, and 10 V. What is the ratio of the change in capacitance to the change in voltage?, (b) Repeat part (a) for reverse-bias potentials of 10 and 1 V. Determine the ratio of the, change in capacitance to the change in voltage., (c) How do the ratios determined in parts (a) and (b) compare? What does it tell you about, which range may have more areas of practical application?, 46. Referring to Fig. 1.37, determine the diffusion capacitance at 0 and 0.25 V., 47. Describe in your own words how diffusion and transition capacitances differ., 48. Determine the reactance offered by a diode described by the characteristics of Fig. 1.37 at a, forward potential of 0.2 V and a reverse potential of 20 V if the applied frequency is 6 MHz., , § 1.11 Reverse Recovery Time, 49. Sketch the waveform for i of the network of Fig. 1.61 if tt 2ts and the total reverse recovery, time is 9 ns., , Figure 1.61 Problem 49, , § 1.14 Zener Diodes, 50. The following characteristics are specified for a particular Zener diode: VZ 29 V, VR 16.8 V,, IZT 10 mA, IR 20 A, and IZM 40 mA. Sketch the characteristic curve in the manner, displayed in Fig. 1.50., * 51. At what temperature will the 10-V Zener diode of Fig. 1.50 have a nominal voltage of 10.75 V?, (Hint: Note the data in Table 1.4.), Problems, , 49
Page 61 :
p n, , 52. Determine the temperature coefficient of a 5-V Zener diode (rated 25°C value) if the nominal, voltage drops to 4.8 V at a temperature of 100°C., 53. Using the curves of Fig. 1.51a, what level of temperature coefficient would you expect for a, 20-V diode? Repeat for a 5-V diode. Assume a linear scale between nominal voltage levels and, a current level of 0.1 mA., 54. Determine the dynamic impedance for the 24-V diode at IZ 10 mA for Fig. 1.51b. Note that, it is a log scale., * 55. Compare the levels of dynamic impedance for the 24-V diode of Fig. 1.51b at current levels of, 0.2, 1, and 10 mA. How do the results relate to the shape of the characteristics in this region?, , § 1.15 Light-Emitting Diodes, 56. Referring to Fig. 1.55e, what would appear to be an appropriate value of VT for this device?, How does it compare to the value of VT for silicon and germanium?, 57. Using the information provided in Fig. 1.55, determine the forward voltage across the diode if, the relative luminous intensity is 1.5., * 58. (a) What is the percent increase in relative efficiency of the device of Fig. 1.55 if the peak current is increased from 5 to 10 mA?, (b) Repeat part (a) for 30 to 35 mA (the same increase in current)., (c) Compare the percent increase from parts (a) and (b). At what point on the curve would you, say there is little gained by further increasing the peak current?, * 59. (a) Referring to Fig. 1.55h, determine the maximum tolerable peak current if the period of the, pulse duration is 1 ms, the frequency is 300 Hz, and the maximum tolerable dc current is, 20 mA., (b) Repeat part (a) for a frequency of 100 Hz., 60. (a) If the luminous intensity at 0° angular displacement is 3.0 mcd for the device of Fig. 1.55,, at what angle will it be 0.75 mcd?, (b) At what angle does the loss of luminous intensity drop below the 50% level?, * 61. Sketch the current derating curve for the average forward current of the high-efficiency red LED, of Fig. 1.55 as determined by temperature. (Note the absolute maximum ratings.), *Please Note: Asterisks indicate more difficult problems., , 50, , Chapter 1, , Semiconductor Diodes
Page 62 :
CHAPTER, , Diode, Applications, , 2, , 2.1 INTRODUCTION, The construction, characteristics, and models of semiconductor diodes were introduced in Chapter 1. The primary goal of this chapter is to develop a working knowledge of the diode in a variety of configurations using models appropriate for the area, of application. By chapter’s end, the fundamental behavior pattern of diodes in dc and, ac networks should be clearly understood. The concepts learned in this chapter will, have significant carryover in the chapters to follow. For instance, diodes are frequently, employed in the description of the basic construction of transistors and in the analysis of transistor networks in the dc and ac domains., The content of this chapter will reveal an interesting and very positive side of the, study of a field such as electronic devices and systems—once the basic behavior of, a device is understood, its function and response in an infinite variety of configurations can be determined. The range of applications is endless, yet the characteristics, and models remain the same. The analysis will proceed from one that employs the, actual diode characteristic to one that utilizes the approximate models almost exclusively. It is important that the role and response of various elements of an electronic, system be understood without continually having to resort to lengthy mathematical, procedures. This is usually accomplished through the approximation process, which, can develop into an art itself. Although the results obtained using the actual characteristics may be slightly different from those obtained using a series of approximations, keep in mind that the characteristics obtained from a specification sheet may, in themselves be slightly different from the device in actual use. In other words, the, characteristics of a 1N4001 semiconductor diode may vary from one element to the, next in the same lot. The variation may be slight, but it will often be sufficient to validate the approximations employed in the analysis. Also consider the other elements, of the network: Is the resistor labeled 100 exactly 100 ? Is the applied voltage, exactly 10 V or perhaps 10.08 V? All these tolerances contribute to the general belief that a response determined through an appropriate set of approximations can often be “as accurate” as one that employs the full characteristics. In this book the emphasis is toward developing a working knowledge of a device through the use of, appropriate approximations, thereby avoiding an unnecessary level of mathematical, complexity. Sufficient detail will normally be provided, however, to permit a detailed, mathematical analysis if desired., , 51
Page 63 :
2.2 LOAD-LINE ANALYSIS, The applied load will normally have an important impact on the point or region of, operation of a device. If the analysis is performed in a graphical manner, a line can, be drawn on the characteristics of the device that represents the applied load. The intersection of the load line with the characteristics will determine the point of operation, of the system. Such an analysis is, for obvious reasons, called load-line analysis., Although the majority of the diode networks analyzed in this chapter do not employ, the load-line approach, the technique is one used quite frequently in subsequent chapters, and this introduction offers the simplest application of the method. It also permits, a validation of the approximate technique described throughout the remainder of this, chapter., Consider the network of Fig. 2.1a employing a diode having the characteristics, of Fig. 2.1b. Note in Fig. 2.1a that the “pressure” established by the battery is to establish a current through the series circuit in the clockwise direction. The fact that, this current and the defined direction of conduction of the diode are a “match” reveals that the diode is in the “on” state and conduction has been established. The resulting polarity across the diode will be as shown and the first quadrant (VD and ID, positive) of Fig. 2.1b will be the region of interest—the forward-bias region., Applying Kirchhoff’s voltage law to the series circuit of Fig. 2.1a will result in, E VD VR 0, E VD ID R, , or, , (2.1), , The two variables of Eq. (2.1) (VD and ID) are the same as the diode axis variables of Fig. 2.1b. This similarity permits a plotting of Eq. (2.1) on the same characteristics of Fig. 2.1b., The intersections of the load line on the characteristics can easily be determined, if one simply employs the fact that anywhere on the horizontal axis ID 0 A and, anywhere on the vertical axis VD 0 V., If we set VD 0 V in Eq. (2.1) and solve for ID, we have the magnitude of ID on, the vertical axis. Therefore, with VD 0 V, Eq. (2.1) becomes, E VD IDR, 0 V IDR, , , , E, I D , R, , and, Figure 2.1 Series diode configuration: (a) circuit; (b) characteristics., , VD=0 V, , (2.2), , as shown in Fig. 2.2. If we set ID 0 A in Eq. (2.1) and solve for VD, we have the, magnitude of VD on the horizontal axis. Therefore, with ID 0 A, Eq. (2.1) becomes, E VD ID R, VD (0 A)R, VD EID =0 A, , and, , (2.3), , as shown in Fig. 2.2. A straight line drawn between the two points will define the, load line as depicted in Fig. 2.2. Change the level of R (the load) and the intersection, on the vertical axis will change. The result will be a change in the slope of the load, line and a different point of intersection between the load line and the device characteristics., We now have a load line defined by the network and a characteristic curve defined by the device. The point of intersection between the two is the point of opera52, , Chapter 2, , Diode Applications
Page 64 :
ID, , Characteristics (device), , E, R, , Q-point, , ID, , Q, , Load line (network), , 0, , VD, , Q, , E, , VD, , Figure 2.2 Drawing the load line and finding the point of operation., , tion for this circuit. By simply drawing a line down to the horizontal axis the diode, voltage VDQ can be determined, whereas a horizontal line from the point of intersection to the vertical axis will provide the level of IDQ. The current ID is actually the, current through the entire series configuration of Fig. 2.1a. The point of operation is, usually called the quiescent point (abbreviated “Q-pt.”) to reflect its “still, unmoving”, qualities as defined by a dc network., The solution obtained at the intersection of the two curves is the same that would, be obtained by a simultaneous mathematical solution of Eqs. (2.1) and (1.4) [ID , Is(ekVD/TK 1)]. Since the curve for a diode has nonlinear characteristics the mathematics involved would require the use of nonlinear techniques that are beyond the, needs and scope of this book. The load-line analysis described above provides a solution with a minimum of effort and a “pictorial” description of why the levels of solution for VDQ and IDQ were obtained. The next two examples will demonstrate the, techniques introduced above and reveal the relative ease with which the load line can, be drawn using Eqs. (2.2) and (2.3)., For the series diode configuration of Fig. 2.3a employing the diode characteristics of, Fig. 2.3b determine:, (a) VDQ and IDQ., (b) VR., , EXAMPLE 2.1, , Figure 2.3 (a) Circuit; (b) characteristics., , 2.2 Load-line Analysis, , 53
Page 65 :
Solution, , , , E, 10 V, (a) Eq. (2.2): ID , 10 mA, R VD0 V 2 k, Eq. (2.3): VD EID0 A 10 V, The resulting load line appears in Fig. 2.4. The intersection between the load line and, the characteristic curve defines the Q-point as, VD 0.78 V, Q, , ID 9.25 mA, Q, , The level of VD is certainly an estimate, and the accuracy of ID is limited by the chosen scale. A higher degree of accuracy would require a plot that would be much larger, and perhaps unwieldy., (b) VR IRR IDQR (9.25 mA)(1 k) 9.25 V, or VR E VD 10 V 0.78 V 9.22 V, The difference in results is due to the accuracy with which the graph can be read. Ideally, the results obtained either way should be the same., , Figure 2.4 Solution to Example 2.1., , EXAMPLE 2.2, , Repeat the analysis of Example 2.1 with R 2 k., , Solution, , , , E, 10 V, (a) Eq. (2.2): ID , 5 mA, R VD0 V 2 k, Eq. (2.3): VD EID0 A 10 V, The resulting load line appears in Fig. 2.5. Note the reduced slope and levels of diode, current for increasing loads. The resulting Q-point is defined by, VDQ 0.7 V, IDQ 4.6 mA, (b) VR IRR IDQR (4.6 mA)(2 k) 9.2 V, with VR E VD 10 V 0.7 V 9.3 V, The difference in levels is again due to the accuracy with which the graph can be read., Certainly, however, the results provide an expected magnitude for the voltage VR., 54, , Chapter 2, , Diode Applications
Page 66 :
I D (mA), 10, 9, 8, 7, E, R 6, 5, ID ~, = 4.6 mA, Q, 4, 3, 2, 1, , Q-point, Load line, (from Example 2.1), 0.5 1, 2, ~ 0.7 V, VD =, Q, , 0, , 3, , 4, , 5, , 6, , 7, , 9, , 8, , 10 VD (V), (E), , Figure 2.5 Solution to Example 2.2., , As noted in the examples above, the load line is determined solely by the applied, network while the characteristics are defined by the chosen device. If we turn to our, approximate model for the diode and do not disturb the network, the load line will, be exactly the same as obtained in the examples above. In fact, the next two examples repeat the analysis of Examples 2.1 and 2.2 using the approximate model to permit a comparison of the results., Repeat Example 2.1 using the approximate equivalent model for the silicon semiconductor diode., , EXAMPLE 2.3, , Solution, The load line is redrawn as shown in Fig. 2.6 with the same intersections as defined, in Example 2.1. The characteristics of the approximate equivalent circuit for the diode, have also been sketched on the same graph. The resulting Q-point:, VD 0.7 V, Q, , ID 9.25 mA, Q, , I D (mA), 10, ID ~, = 9.25 mA 9, Q, 8, 7, 6, 5, 4, 3, 2, 1, , Q-point, , 0, , 0.5 1, 2, ~ 0.7 V, VD =, , ⇒, , Load line, , 0.7 V, ID, , 3, , 4, , 5, , 6, , 7, , 8, , 9, , 10 VD (V), , Q, , Figure 2.6 Solution to Example 2.1 using the diode approximate model., , 2.2 Load-line Analysis, , 55
Page 67 :
The results obtained in Example 2.3 are quite interesting. The level of IDQ is exactly the same as obtained in Example 2.1 using a characteristic curve that is a great, deal easier to draw than that appearing in Fig. 2.4. The level of VD 0.7 V versus, 0.78 V from Example 2.1 is of a different magnitude to the hundredths place, but they, are certainly in the same neighborhood if we compare their magnitudes to the magnitudes of the other voltages of the network., , EXAMPLE 2.4, , Repeat Example 2.2 using the approximate equivalent model for the silicon semiconductor diode., , Solution, The load line is redrawn as shown in Fig. 2.7 with the same intersections defined in, Example 2.2. The characteristics of the approximate equivalent circuit for the diode, have also been sketched on the same graph. The resulting Q-point:, VD 0.7 V, Q, , ID 4.6 mA, , I D (mA), 10, 9, 8, 7, 6, ~, I D = 4.6 mA 5, Q, 4, 3, 2, 1, 0, , Q, , ⇒, , 0.7 V, ID, , Q-point, , Load line, , 0.5 1, 2, ~, VD = 0.7 V, , 3, , 4, , 5, , 6, , 7, , 9, , 8, , 10 VD (V), , Q, , Figure 2.7 Solution to Example, 2.2 using the diode approximate, model., , In Example 2.4 the results obtained for both VDQ and IDQ are the same as those, obtained using the full characteristics in Example 2.2. The examples above have, demonstrated that the current and voltage levels obtained using the approximate model, have been very close to those obtained using the full characteristics. It suggests, as, will be applied in the sections to follow, that the use of appropriate approximations, can result in solutions that are very close to the actual response with a reduced level, of concern about properly reproducing the characteristics and choosing a large-enough, scale. In the next example we go a step further and substitute the ideal model. The, results will reveal the conditions that must be satisfied to apply the ideal equivalent, properly., , EXAMPLE 2.4, , Repeat Example 2.1 using the ideal diode model., , Solution, As shown in Fig. 2.8 the load line continues to be the same, but the ideal characteristics now intersect the load line on the vertical axis. The Q-point is therefore defined, by, VD 0 V, Q, , ID 10 mA, Q, , 56, , Chapter 2, , Diode Applications
Page 68 :
Figure 2.8 Solution to Example 2.1 using the ideal diode model., , The results are sufficiently different from the solutions of Example 2.1 to cause, some concern about their accuracy. Certainly, they do provide some indication of the, level of voltage and current to be expected relative to the other voltage levels of the, network, but the additional effort of simply including the 0.7-V offset suggests that, the approach of Example 2.3 is more appropriate., Use of the ideal diode model therefore should be reserved for those occasions, when the role of a diode is more important than voltage levels that differ by tenths, of a volt and in those situations where the applied voltages are considerably larger, than the threshold voltage VT. In the next few sections the approximate model will be, employed exclusively since the voltage levels obtained will be sensitive to variations, that approach VT. In later sections the ideal model will be employed more frequently, since the applied voltages will frequently be quite a bit larger than VT and the authors, want to ensure that the role of the diode is correctly and clearly understood., , 2.3 DIODE APPROXIMATIONS, In Section 2.2 we revealed that the results obtained using the approximate piecewiselinear equivalent model were quite close, if not equal, to the response obtained using, the full characteristics. In fact, if one considers all the variations possible due to tolerances, temperature, and so on, one could certainly consider one solution to be “as, accurate” as the other. Since the use of the approximate model normally results in a, reduced expenditure of time and effort to obtain the desired results, it is the approach, that will be employed in this book unless otherwise specified. Recall the following:, The primary purpose of this book is to develop a general knowledge of the behavior, capabilities, and possible areas of application of a device in a manner, that will minimize the need for extensive mathematical developments., The complete piecewise-linear equivalent model introduced in Chapter 1 was not, employed in the load-line analysis because rav is typically much less than the other, series elements of the network. If rav should be close in magnitude to the other series, elements of the network, the complete equivalent model can be applied in much the, same manner as described in Section 2.2., In preparation for the analysis to follow, Table 2.1 was developed to review the, important characteristics, models, and conditions of application for the approximate, and ideal diode models. Although the silicon diode is used almost exclusively due to, 2.3 Diode Approximations, , 57
Page 69 :
TABLE 2.1 Approximate and Ideal Semiconductor Diode Models, , its temperature characteristics, the germanium diode is still employed and is therefore included in Table 2.1. As with the silicon diode, a germanium diode is approximated by an open-circuit equivalent for voltages less than VT. It will enter the “on”, state when VD VT 0.3 V., Keep in mind that the 0.7 and 0.3 V in the equivalent circuits are not independent, sources of energy but are there simply to remind us that there is a “price to pay” to, turn on a diode. An isolated diode on a laboratory table will not indicate 0.7 or 0.3, V if a voltmeter is placed across its terminals. The supplies specify the voltage drop, across each when the device is “on” and specify that the diode voltage must be at, least the indicated level before conduction can be established., , 58, , Chapter 2, , Diode Applications
Page 70 :
In the next few sections we demonstrate the impact of the models of Table 2.1 on, the analysis of diode configurations. For those situations where the approximate equivalent circuit will be employed, the diode symbol will appear as shown in Fig. 2.9a, for the silicon and germanium diodes. If conditions are such that the ideal diode model, can be employed, the diode symbol will appear as shown in Fig. 2.9b., , 2.4 SERIES DIODE CONFIGURATIONS, WITH DC INPUTS, , Figure 2.9 (a) Approximate, model notation; (b) ideal diode, notation., , In this section the approximate model is utilized to investigate a number of series, diode configurations with dc inputs. The content will establish a foundation in diode, analysis that will carry over into the sections and chapters to follow. The procedure, described can, in fact, be applied to networks with any number of diodes in a variety, of configurations., For each configuration the state of each diode must first be determined. Which, diodes are “on” and which are “off”? Once determined, the appropriate equivalent as, defined in Section 2.3 can be substituted and the remaining parameters of the network determined., In general, a diode is in the “on” state if the current established by the, applied sources is such that its direction matches that of the arrow in the, diode symbol, and VD 0.7 V for silicon and VD 0.3 V for germanium., For each configuration, mentally replace the diodes with resistive elements and, note the resulting current direction as established by the applied voltages (“pressure”)., If the resulting direction is a “match” with the arrow in the diode symbol, conduction through the diode will occur and the device is in the “on” state. The description, above is, of course, contingent on the supply having a voltage greater than the “turnon” voltage (VT) of each diode., If a diode is in the “on” state, one can either place a 0.7-V drop across the, element, or the network can be redrawn with the VT equivalent circuit as defined in, Table 2.1. In time the preference will probably simply be to include the 0.7-V drop across, each “on” diode and draw a line through each diode in the “off” or open state. Initially, however, the substitution method will be utilized to ensure that the proper voltage and current levels are determined., The series circuit of Fig. 2.10 described in some detail in Section 2.2 will be used, to demonstrate the approach described in the paragraphs above. The state of the diode, is first determined by mentally replacing the diode with a resistive element as shown, in Fig. 2.11. The resulting direction of I is a match with the arrow in the diode symbol, and since E VT the diode is in the “on” state. The network is then redrawn as, shown in Fig. 2.12 with the appropriate equivalent model for the forward-biased silicon diode. Note for future reference that the polarity of VD is the same as would result if in fact the diode were a resistive element. The resulting voltage and current, levels are the following:, VD VT, , (2.4), , VR E VT, , (2.5), , VR, ID IR , R, , (2.6), , 2.4 Series Diode Configurations with DC Inputs, , Figure 2.10 Series diode configuration., , +, E, , I, , +, R, , –, , VR, , –, , Figure 2.11 Determining the, state of the diode of Fig. 2.10., , Figure 2.12 Substituting the, equivalent model for the “on”, diode of Fig. 2.10., , 59
Page 71 :
Figure 2.14 Determining the, state of the diode of Fig. 2.13., , Figure 2.13 Reversing the diode, of Fig. 2.10., , Figure 2.15 Substituting the, equivalent model for the “off”, diode of Figure 2.13., , In Fig. 2.13 the diode of Fig. 2.10 has been reversed. Mentally replacing the diode, with a resistive element as shown in Fig. 2.14 will reveal that the resulting current direction does not match the arrow in the diode symbol. The diode is in the “off” state,, resulting in the equivalent circuit of Fig. 2.15. Due to the open circuit, the diode current is 0 A and the voltage across the resistor R is the following:, VR IRR ID R (0 A)R 0 V, The fact that VR 0 V will establish E volts across the open circuit as defined by, Kirchhoff’s voltage law. Always keep in mind that under any circumstances—dc, ac, instantaneous values, pulses, and so on—Kirchhoff’s voltage law must be satisfied!, , EXAMPLE 2.6, , For the series diode configuration of Fig. 2.16, determine VD, VR, and ID., , Solution, Since the applied voltage establishes a current in the clockwise direction to match the, arrow of the symbol and the diode is in the “on” state,, VD 0.7 V, VR E VD 8 V 0.7 V 7.3 V, 7.3 V, VR, ID IR , 3.32 mA, 2.2 k, R, , Figure 2.16 Circuit for Example, 2.6., , Repeat Example 2.6 with the diode reversed., , EXAMPLE 2.7, ID = 0 A, , Solution, + VD –, , IR = 0 A, , +, E, , 8V, , R, , 2.2 kΩ VR, , –, , Removing the diode, we find that the direction of I is opposite to the arrow in the, diode symbol and the diode equivalent is the open circuit no matter which model is, employed. The result is the network of Fig. 2.17, where ID 0 A due to the open circuit. Since VR IRR, VR (0)R 0 V. Applying Kirchhoff’s voltage law around the, closed loop yields, E VD VR 0, , Figure 2.17 Determining the, unknown quantities for Example, 2.7., , and, , 60, , Chapter 2, , VD E VR E 0 E 8 V, , Diode Applications
Page 72 :
In particular, note in Example 2.7 the high voltage across the diode even though, it is an “off” state. The current is zero, but the voltage is significant. For review purposes, keep the following in mind for the analysis to follow:, 1. An open circuit can have any voltage across its terminals, but the current is always 0 A., 2. A short circuit has a 0-V drop across its terminals, but the current is limited, only by the surrounding network., In the next example the notation of Fig. 2.18 will be employed for the applied voltage. It is a common industry notation and one with which the reader should become very, familiar. Such notation and other defined voltage levels are treated further in Chapter 4., E = + 10 V, , +10 V, , E, , –5 V, , E = –5 V, , 10 V, , E, , 5V, , Figure 2.18 Source notation., , For the series diode configuration of Fig. 2.19, determine VD, VR, and ID., , EXAMPLE 2.8, , Figure 2.19 Series diode circuit, for Example 2.8., , Solution, Although the “pressure” establishes a current with the same direction as the arrow, symbol, the level of applied voltage is insufficient to turn the silicon diode “on.” The, point of operation on the characteristics is shown in Fig. 2.20, establishing the opencircuit equivalent as the appropriate approximation. The resulting voltage and current, levels are therefore the following:, ID 0 A, VR IRR ID R (0 A)1.2 k 0 V, and, , VD E 0.5 V, , Figure 2.20 Operating point, with E 0.5 V., , 2.4 Series Diode Configurations with DC Inputs, , 61
Page 73 :
EXAMPLE 2.9, , Determine Vo and ID for the series circuit of Fig. 2.21., , Figure 2.21 Circuit for Example 2.9., , Solution, , An attack similar to that applied in Example 2.6 will reveal that the resulting current, has the same direction as the arrowheads of the symbols of both diodes, and the network of Fig. 2.22 results because E 12 V (0.7 V 0.3 V) 1 V. Note the redrawn supply of 12 V and the polarity of Vo across the 5.6-k resistor. The resulting, voltage, Vo E VT VT 12 V 0.7 V 0.3 V 11 V, 1, , 2, , VR, V, 11 V, ID IR , o 1.96 mA, R, R, 5.6 k, , and, , Figure 2.22 Determining the, unknown quantities for Example, 2.9., , EXAMPLE 2.10, , Determine ID, VD2, and Vo for the circuit of Fig. 2.23., , +, Si, +12 V, , VD, , 2, , –, , Si, IR, , ID, , Vo, , 5.6 kΩ, , Figure 2.23 Circuit for Example 2.10., , Solution, , Removing the diodes and determining the direction of the resulting current I will result in the circuit of Fig. 2.24. There is a match in current direction for the silicon, diode but not for the germanium diode. The combination of a short circuit in series, with an open circuit always results in an open circuit and ID 0 A, as shown in, Fig. 2.25., , +, , I, E, , R, , 5.6 kΩ Vo, , –, Figure 2.24 Determining the state of the, diodes of Figure 2.23., , 62, , Chapter 2, , Diode Applications, , Figure 2.25 Substituting the equivalent, state for the open diode.
Page 74 :
The question remains as to what to substitute for the silicon diode. For the analysis to follow in this and succeeding chapters, simply recall for the actual practical, diode that when ID 0 A, VD 0 V (and vice versa), as described for the no-bias, situation in Chapter 1. The conditions described by ID 0 A and VD1 0 V are indicated in Fig. 2.26., , Figure 2.26 Determining the, unknown quantities for the circuit, of Example 2.10., , Vo IRR IDR (0 A)R 0 V, and, , VD Vopen circuit E 12 V, 2, , Applying Kirchhoff’s voltage law in a clockwise direction gives us, E VD VD Vo 0, 1, , and, , 2, , VD E VD Vo 12 V 0 0, 2, , 1, , 12 V, with, , Vo 0 V, , Determine I, V1, V2, and Vo for the series dc configuration of Fig. 2.27., , EXAMPLE 2.11, , Figure 2.27 Circuit for Example 2.11., , Solution, The sources are drawn and the current direction indicated as shown in Fig. 2.28. The, diode is in the “on” state and the notation appearing in Fig. 2.29 is included to indicate this state. Note that the “on” state is noted simply by the additional VD 0.7 V, , Figure 2.28 Determining the state of the, diode for the network of Fig. 2.27., , Figure 2.29 Determining the unknown quantities for the network of Fig. 2.27., , 2.4 Series Diode Configurations with DC Inputs, , 63
Page 75 :
on the figure. This eliminates the need to redraw the network and avoids any confusion that may result from the appearance of another source. As indicated in the introduction to this section, this is probably the path and notation that one will take, when a level of confidence has been established in the analysis of diode configurations. In time the entire analysis will be performed simply by referring to the original network. Recall that a reverse-biased diode can simply be indicated by a line, through the device., The resulting current through the circuit is,, 10 V 5 V 0.7 V, E1 E2 VD, 14.3 V, , I, R1 R2, 4.7 k 2.2 k, 6.9 k, 2.072 mA, and the voltages are, V1 IR1 (2.072 mA)(4.7 k) 9.74 V, V2 IR2 (2.072 mA)(2.2 k) 4.56 V, Applying Kirchhoff’s voltage law to the output section in the clockwise direction will, result in, E2 V2 Vo 0, and, , Vo V2 E2 4.56 V 5 V 0.44 V, , The minus sign indicates that Vo has a polarity opposite to that appearing in Fig. 2.27., , 2.5 PARALLEL AND SERIES–PARALLEL, CONFIGURATIONS, The methods applied in Section 2.4 can be extended to the analysis of parallel and, series–parallel configurations. For each area of application, simply match the sequential series of steps applied to series diode configurations., , EXAMPLE 2.12, , Determine Vo, I1, ID1, and ID2 for the parallel diode configuration of Fig. 2.30., , Figure 2.30 Network for Example 2.12., , Solution, For the applied voltage the “pressure” of the source is to establish a current through, each diode in the same direction as shown in Fig. 2.31. Since the resulting current direction matches that of the arrow in each diode symbol and the applied voltage is, greater than 0.7 V, both diodes are in the “on” state. The voltage across parallel elements is always the same and, Vo 0.7 V, 64, , Chapter 2, , Diode Applications
Page 76 :
Figure 2.31 Determining the, unknown quantities for the network of Example 2.12., , The current, VR, E VD, 10 V 0.7 V, I1 , , 28.18 mA, R, 0.33 k, R, Assuming diodes of similar characteristics, we have, I, 28.18 mA, ID ID 1 14.09 mA, 2, 2, 1, , 2, , Example 2.12 demonstrated one reason for placing diodes in parallel. If the current rating of the diodes of Fig. 2.30 is only 20 mA, a current of 28.18 mA would, damage the device if it appeared alone in Fig. 2.30. By placing two in parallel, the, current is limited to a safe value of 14.09 mA with the same terminal voltage., , EXAMPLE 2.13, , Determine the current I for the network of Fig. 2.32., , Figure 2.32 Network for Example 2.13., , Solution, Redrawing the network as shown in Fig. 2.33 reveals that the resulting current direction is such as to turn on diode D1 and turn off diode D2. The resulting current I, is then, E1 E2 VD, 20 V 4 V 0.7 V, 6.95 mA, I, 2.2 k, R, , Figure 2.33 Determining the, unknown quantities for the network of Example 2.13., , 2.5 Parallel and Series–Parallel Configurations, , 65
Page 77 :
EXAMPLE 2.14, , Determine the voltage Vo for the network of Fig. 2.34., , Solution, , 12 V, , Si, , Ge, , Vo, 2.2 kΩ, , Initially, it would appear that the applied voltage will turn both diodes “on.” However,, if both were “on,” the 0.7-V drop across the silicon diode would not match the 0.3 V, across the germanium diode as required by the fact that the voltage across parallel elements must be the same. The resulting action can be explained simply by realizing, that when the supply is turned on it will increase from 0 to 12 V over a period of, time—although probably measurable in milliseconds. At the instant during the rise, that 0.3 V is established across the germanium diode it will turn “on” and maintain, a level of 0.3 V. The silicon diode will never have the opportunity to capture its required 0.7 V and therefore remains in its open-circuit state as shown in Fig. 2.35. The, result:, Vo 12 V 0.3 V 11.7 V, , Figure 2.34, ple 2.14., , Network for Exam-, , Figure 2.35 Determining Vo, for the network of Fig. 2.34., , EXAMPLE 2.15, , Determine the currents I1, I2, and ID2 for the network of Fig. 2.36., , Solution, The applied voltage (pressure) is such as to turn both diodes on, as noted by the resulting current directions in the network of Fig. 2.37. Note the use of the abbreviated, notation for “on” diodes and that the solution is obtained through an application of, techniques applied to dc series—parallel networks., 0.7 V, V, I1 T 0.212 mA, R1, 3.3 k, 2, , Figure 2.36 Network for Example 2.15., , Figure 2.37 Determining the, unknown quantities for Example, 2.15., , 66, , Chapter 2, , Diode Applications
Page 78 :
Applying Kirchhoff’s voltage law around the indicated loop in the clockwise direction yields, V2 E VT VT 0, 1, , 2, , and, , V2 E VT VT 20 V 0.7 V 0.7 V 18.6 V, , with, , V2, 18.6 V, I2 , 3.32 mA, R2, 5.6 k, , 1, , 2, , At the bottom node (a),, ID2 I1 I2, and, , ID2 I2 I1 3.32 mA 0.212 mA 3.108 mA, , 2.6 AND/OR GATES, The tools of analysis are now at our disposal, and the opportunity to investigate a, computer configuration is one that will demonstrate the range of applications of this, relatively simple device. Our analysis will be limited to determining the voltage levels and will not include a detailed discussion of Boolean algebra or positive and negative logic., The network to be analyzed in Example 2.16 is an OR gate for positive logic., That is, the 10-V level of Fig. 2.38 is assigned a “1” for Boolean algebra while the, 0-V input is assigned a “0.” An OR gate is such that the output voltage level will be, a 1 if either or both inputs is a 1. The output is a 0 if both inputs are at the 0 level., The analysis of AND/OR gates is made measurably easier by using the approximate equivalent for a diode rather than the ideal because we can stipulate that the, voltage across the diode must be 0.7 V positive for the silicon diode (0.3 V for Ge), to switch to the “on” state., In general, the best approach is simply to establish a “gut” feeling for the state of, the diodes by noting the direction and the “pressure” established by the applied potentials. The analysis will then verify or negate your initial assumptions., , Figure 2.38 Positive logic OR, gate., , EXAMPLE 2.16, , Determine Vo for the network of Fig. 2.38., , Solution, First note that there is only one applied potential; 10 V at terminal 1. Terminal 2 with, a 0-V input is essentially at ground potential, as shown in the redrawn network of Fig., 2.39. Figure 2.39 “suggests” that D1 is probably in the “on” state due to the applied, 10 V while D2 with its “positive” side at 0 V is probably “off.” Assuming these states, will result in the configuration of Fig. 2.40., The next step is simply to check that there is no contradiction to our assumptions., That is, note that the polarity across D1 is such as to turn it on and the polarity across, D2 is such as to turn it off. For D1 the “on” state establishes Vo at Vo E VD , 10 V 0.7 V 9.3 V. With 9.3 V at the cathode () side of D2 and 0 V at the anode () side, D2 is definitely in the “off” state. The current direction and the resulting continuous path for conduction further confirm our assumption that D1 is conducting. Our assumptions seem confirmed by the resulting voltages and current, and, our initial analysis can be assumed to be correct. The output voltage level is not 10, V as defined for an input of 1, but the 9.3 V is sufficiently large to be considered a, 1 level. The output is therefore at a 1 level with only one input, which suggests that, 2.6 And/Or Gates, , +, , –, D1, , E, , Vo, , 10 V, , D2, R, , 1 kΩ, , 0V, , Figure 2.39 Redrawn network, of Fig. 2.38., , 67
Page 79 :
Figure 2.40 Assumed diode, states for Fig. 2.38., , the gate is an OR gate. An analysis of the same network with two 10-V inputs will, result in both diodes being in the “on” state and an output of 9.3 V. A 0-V input at, both inputs will not provide the 0.7 V required to turn the diodes on, and the output, will be a 0 due to the 0-V output level. For the network of Fig. 2.40 the current level, is determined by, E VD, 10 V 0.7 V, 9.3 mA, I , R, 1 k, , EXAMPLE 2.17, (1), E1 = 10 V, , (0), E2 = 0 V, , Determine the output level for the positive logic AND gate of Fig. 2.41., , Solution, , Si, 1, , D1, Si, , 2, , Vo, D2, R, , E, , Figure 2.41, gate., , 1 kΩ, , 10 V, , Positive logic AND, , Note in this case that an independent source appears in the grounded leg of the network. For reasons soon to become obvious it is chosen at the same level as the input, logic level. The network is redrawn in Fig. 2.42 with our initial assumptions regarding the state of the diodes. With 10 V at the cathode side of D1 it is assumed that D1, is in the “off” state even though there is a 10-V source connected to the anode of D1, through the resistor. However, recall that we mentioned in the introduction to this section that the use of the approximate model will be an aid to the analysis. For D1,, where will the 0.7 V come from if the input and source voltages are at the same level, and creating opposing “pressures”? D2 is assumed to be in the “on” state due to the, low voltage at the cathode side and the availability of the 10-V source through the, 1-k resistor., For the network of Fig. 2.42 the voltage at Vo is 0.7 V due to the forward-biased, diode D2. With 0.7 V at the anode of D1 and 10 V at the cathode, D1 is definitely in, the “off” state. The current I will have the direction indicated in Fig. 2.42 and a magnitude equal to, E VD, 10 V 0.7 V, 9.3 mA, I , R, 1 k, , VD, , –, (1), E1, , +, , Vo = VD = 0.7 V (0), , 0.7V, , 10 V, , R, , 1 kΩ, , (0), I, , 68, , Chapter 2, , E, , Diode Applications, , 10 V, , Figure 2.42 Substituting the, assumed states for the diodes of, Fig. 2.41.
Page 80 :
The state of the diodes is therefore confirmed and our earlier analysis was correct. Although not 0 V as earlier defined for the 0 level, the output voltage is sufficiently small to be considered a 0 level. For the AND gate, therefore, a single input, will result in a 0-level output. The remaining states of the diodes for the possibilities, of two inputs and no inputs will be examined in the problems at the end of the, chapter., , 2.7 SINUSOIDAL INPUTS; HALF-WAVE, RECTIFICATION, The diode analysis will now be expanded to include time-varying functions such as, the sinusoidal waveform and the square wave. There is no question that the degree of, difficulty will increase, but once a few fundamental maneuvers are understood, the, analysis will be fairly direct and follow a common thread., The simplest of networks to examine with a time-varying signal appears in Fig., 2.43. For the moment we will use the ideal model (note the absence of the Si or Ge, label to denote ideal diode) to ensure that the approach is not clouded by additional, mathematical complexity., vi, , +, , +, , T, 2, , 0, , –, , +, Vm, , T, , vi, , t, , vo, , R, , –, , –, , 1 cycle, vi = Vm sin ωt, , Figure 2.43, , Half-wave rectifier., , Over one full cycle, defined by the period T of Fig. 2.43, the average value (the, algebraic sum of the areas above and below the axis) is zero. The circuit of Fig. 2.43,, called a half-wave rectifier, will generate a waveform vo that will have an average, value of particular, use in the ac-to-dc conversion process. When employed in the rectification process, a diode is typically referred to as a rectifier. Its power and current, ratings are typically much higher than those of diodes employed in other applications,, such as computers and communication systems., During the interval t 0 → T/2 in Fig. 2.43 the polarity of the applied voltage vi, is such as to establish “pressure” in the direction indicated and turn on the diode with, the polarity appearing above the diode. Substituting the short-circuit equivalence for, the ideal diode will result in the equivalent circuit of Fig. 2.44, where it is fairly obvious that the output signal is an exact replica of the applied signal. The two terminals defining the output voltage are connected directly to the applied signal via the, short-circuit equivalence of the diode., , +, , –, , +, vi, , –, Figure 2.44, , R, , +, , +, , vo, , vi, , –, , –, , +, R, , vo, Vm, , vo = vi, , –, , 0, , T, 2, , t, , Conduction region (0 → T/2)., , 2.7 Sinusoidal Inputs; Half-Wave Rectification, , 69
Page 81 :
For the period T/2 → T, the polarity of the input vi is as shown in Fig. 2.45 and, the resulting polarity across the ideal diode produces an “off” state with an open-circuit equivalent. The result is the absence of a path for charge to flow and vo iR , (0)R 0 V for the period T/2 → T. The input vi and the output vo were sketched together in Fig. 2.46 for comparison purposes. The output signal vo now has a net positive area above the axis over a full period and an average value determined by, Vdc 0.318Vm, , –, , (2.7), , half-wave, , +, , –, vi, , R, , +, Figure 2.45, , +, , –, , vo, , vi, , –, , +, , +, , vo, vo = 0 V, , vo = 0 V, , R, , 0, , –, , T, 2, , T, , t, , Nonconduction region (T/2 → T)., vi, Vm, , t, , 0, , Vdc = 0 V, , vo, Vm, Vdc = 0.318Vm, 0, , t, , T, , Figure 2.46, signal., , Half-wave rectified, , The process of removing one-half the input signal to establish a dc level is aptly, called half-wave rectification., The effect of using a silicon diode with VT 0.7 V is demonstrated in Fig. 2.47, for the forward-bias region. The applied signal must now be at least 0.7 V before the, diode can turn “on.” For levels of vi less than 0.7 V, the diode is still in an opencircuit state and vo 0 V as shown in the same figure. When conducting, the difference between vo and vi is a fixed level of VT 0.7 V and vo vi VT , as shown in, the figure. The net effect is a reduction in area above the axis, which naturally reduces, , vi, , +, Vm, , 0, , +, , T, 2, , VT = 0.7 V, t, T, , vi, , VT, , –, , vo, , +, , 0.7 V, R, , vo, 0, , –, , Vm – VT, , –, , T, 2, Offset due to VT, , Figure 2.47, , 70, , Chapter 2, , Effect of VT on half-wave rectified signal., , Diode Applications, , Tt
Page 82 :
the resulting dc voltage level. For situations where Vm VT, Eq. 2.8 can be applied, to determine the average value with a relatively high level of accuracy., Vdc 0.318(Vm VT), , (2.8), , In fact, if Vm is sufficiently greater than VT, Eq. 2.7 is often applied as a first approximation for Vdc., , EXAMPLE 2.18, , (a) Sketch the output vo and determine the dc level of the output for the network of, Fig. 2.48., (b) Repeat part (a) if the ideal diode is replaced by a silicon diode., (c) Repeat parts (a) and (b) if Vm is increased to 200 V and compare solutions using, Eqs. (2.7) and (2.8)., , +, , vi, 20 V, , vi, T t, , T, 2, , 0, , +, R, , vo, , 2 kΩ, , –, , –, , Figure 2.48, ple 2.18., , Network for Exam-, , Solution, (a) In this situation the diode will conduct during the negative part of the input as, shown in Fig. 2.49, and vo will appear as shown in the same figure. For the full, period, the dc level is, Vdc 0.318Vm 0.318(20 V) 6.36 V, The negative sign indicates that the polarity of the output is opposite to the defined, polarity of Fig. 2.48., , –, , vi, , T, 2, , T, 20, , Figure 2.49, , vo, , –, , 20, , 0, , +, , t, , vi, , +, 2 kΩ, , vo, , –, , +, , 0, , T, 2, , T, , t, 20 V, , Resulting vo for the circuit of Example 2.18., , (b) Using a silicon diode, the output has the appearance of Fig. 2.50 and, Vdc 0.318(Vm 0.7 V) 0.318(19.3 V) 6.14 V, The resulting drop in dc level is 0.22 V or about 3.5%., (c) Eq. (2.7): Vdc 0.318Vm 0.318(200 V) 63.6 V, Eq. (2.8): Vdc 0.318(Vm VT) 0.318(200 V 0.7 V), (0.318)(199.3 V) 63.38 V, which is a difference that can certainly be ignored for most applications. For part c, the offset and drop in amplitude due to VT would not be discernible on a typical oscilloscope if the full pattern is displayed., , 2.7 Sinusoidal Inputs; Half-Wave Rectification, , vo, , 0, , T, 2, , T, , t, , 20 V – 0.7 V = 19.3 V, , Figure 2.50 Effect of VT on output of Fig. 2.49., , 71
Page 83 :
PIV (PRV), The peak inverse voltage (PIV) [or PRV (peak reverse voltage)] rating of the diode, is of primary importance in the design of rectification systems. Recall that it is the, voltage rating that must not be exceeded in the reverse-bias region or the diode will, enter the Zener avalanche region. The required PIV rating for the half-wave rectifier, can be determined from Fig. 2.51, which displays the reverse-biased diode of Fig., 2.43 with maximum applied voltage. Applying Kirchhoff”s voltage law, it is fairly, obvious that the PIV rating of the diode must equal or exceed the peak value of the, applied voltage. Therefore,, PIV rating, , –, , V (PIV), , –, , (2.9), , half-wave rectifier, , +, –, , I= 0, , Vm, , Vm, , Vo = IR = (0)R = 0 V, , R, , +, , +, , Figure 2.51 Determining the required PIV rating for the halfwave rectifier., , 2.8 FULL-WAVE RECTIFICATION, Bridge Network, The dc level obtained from a sinusoidal input can be improved 100% using a process, called full-wave rectification. The most familiar network for performing such a function appears in Fig. 2.52 with its four diodes in a bridge configuration. During the, period t 0 to T/2 the polarity of the input is as shown in Fig. 2.53. The resulting, polarities across the ideal diodes are also shown in Fig. 2.53 to reveal that D2 and D3, are conducting while D1 and D4 are in the “off” state. The net result is the configuration of Fig. 2.54, with its indicated current and polarity across R. Since the diodes, are ideal the load voltage is vo vi, as shown in the same figure., vi, , +, , D1, , Vm, , T, 2, , 0, , T, , –, , vi, , t, , "off ", , –, vi, , +, –, , –, , vo, , +, , –, , +, , D3, , D4, , Figure 2.52 Full-wave, bridge rectifier., , "on", vi, , –, , vo, , +, Vm, , R, , +, "on", , +, , vo, R, , –, +, , D2, , Vm, , +, –, , "off ", , R, , vi, 0, , T, 2, , –, , t, , vo, , +, , –, , Figure 2.53 Network of Fig., 2.52 for the period 0 → T/2 of, the input voltage vi., , Figure 2.54, , 72, , Chapter 2, , Conduction path for the positive region of vi., , Diode Applications, , 0, , T, 2, , t
Page 84 :
For the negative region of the input the conducting diodes are D1 and D4, resulting in the configuration of Fig. 2.55. The important result is that the polarity across, the load resistor R is the same as in Fig. 2.53, establishing a second positive pulse,, as shown in Fig. 2.55. Over one full cycle the input and output voltages will appear, as shown in Fig. 2.56., vi, , vo, , –, , Vm, 0, , T, , T, 2, , –, , vi, , vo, , t, , +, 0, , R, , T, 2, , T, , t, , Vm, , +, Figure 2.55, , Conduction path for the negative region of vi., vo, , vi, Vm, , Vm, Vdc = 0.636Vm, , 0, , T, , T, 2, , T, 2, , 0, , t, , T t, , Figure 2.56 Input and output, waveforms for a full-wave rectifier., , Since the area above the axis for one full cycle is now twice that obtained for a, half-wave system, the dc level has also been doubled and, Vdc 2(Eq. 2.7) 2(0.318Vm), Vdc 0.636Vm, , or, , full-wave, , (2.10), , If silicon rather than ideal diodes are employed as shown in Fig. 2.57, an application of Kirchhoff’s voltage law around the conduction path would result in, vi VT vo VT 0, vo vi 2VT, , and, , The peak value of the output voltage vo is therefore, Vomax Vm 2VT, For situations where Vm 2VT, Eq. (2.11) can be applied for the average value with, a relatively high level of accuracy., Vdc 0.636(Vm 2VT), , +, , +, , vo, VT = 0.7 V, , –, , –, , vi, , –, , Vm – 2VT, , +, , R, VT = 0.7 V, , +, –, , vo, , (2.11), , 0, , T, 2, , T, , t, , Figure 2.57 Determining Vomax for, silicon diodes in the bridge configuration., , Then again, if Vm is sufficiently greater than 2VT, then Eq. (2.10) is often applied as, a first approximation for Vdc., 2.8 Full-Wave Rectification, , 73
Page 85 :
PIV, The required PIV of each diode (ideal) can be determined from Fig. 2.58 obtained, at the peak of the positive region of the input signal. For the indicated loop the maximum voltage across R is Vm and the PIV rating is defined by, PIV, , Vm, , (2.12), , full-wave bridge rectifier, , Center-Tapped Transformer, Figure 2.58 Determining the required PIV for the bridge configuration., , A second popular full-wave rectifier appears in Fig. 2.59 with only two diodes but, requiring a center-tapped (CT) transformer to establish the input signal across each, section of the secondary of the transformer. During the positive portion of vi applied, to the primary of the transformer, the network will appear as shown in Fig. 2.60. D1, assumes the short-circuit equivalent and D2 the open-circuit equivalent, as determined, by the secondary voltages and the resulting current directions. The output voltage appears as shown in Fig. 2.60., D1, , 1:2, , +, , vi, , vi, , Vm, , +, t, , 0, , R, , –, , vi, , CT, , –, , +, , –, , vo, , +, , vi, , –, , Figure 2.59 Center-tapped, transformer full-wave rectifier., , D2, 1:2, , vi, , +, , vo, Vm, Vm, , Vm, , +, 0, , T, 2, , t, , vi, , –, , +, –, , Figure 2.60, , –, , –, CT, , vo, , +, 0, , R, , Vm, , T, 2, , t, , – +, , Network conditions for the positive region of vi., , During the negative portion of the input the network appears as shown in Fig., 2.61, reversing the roles of the diodes but maintaining the same polarity for the voltvi, , –, , vo, , – +, , Vm, , –, 0, , T, 2, , T, Vm, , t, , vi, , +, , +, CT, , 74, , Chapter 2, , R, , –, , –, , +, Figure 2.61, , Vm, , vo, , +, , Vm, , Network conditions for the negative region of vi., , Diode Applications, , 0, , T, 2, , T, , t
Page 86 :
age across the load resistor R. The net effect is the same output as that appearing in, Fig. 2.56 with the same dc levels., PIV, The network of Fig. 2.62 will help us determine the net PIV for each diode for, this full-wave rectifier. Inserting the maximum voltage for the secondary voltage and, Vm as established by the adjoining loop will result in, PIV Vsecondary VR, Vm Vm, and, , PIV, , 2Vm, , Figure 2.62 Determining the, PIV level for the diodes of the CT, transformer full-wave rectifier., , (2.13), , CT transformer, full-wave rectifier, , EXAMPLE 2.19, , Determine the output waveform for the network of Fig. 2.63 and calculate the output, dc level and the required PIV of each diode., vi, , +, 10 V, 2 kΩ, , vi, T, 2, , 0, , –, , T t, , +, , vo, , 2 kΩ, , 2 kΩ, , –, , Figure 2.63 Bridge network for, Example 2.19., , Solution, The network will appear as shown in Fig. 2.64 for the positive region of the input, voltage. Redrawing the network will result in the configuration of Fig. 2.65, where, vo 12 vi or Vomax 12 Vi max 12 (10 V) 5 V, as shown in Fig. 2.65. For the negative, part of the input the roles of the diodes will be interchanged and vo will appear as, shown in Fig. 2.66., , +, , vi, , +, , +, , 2 kΩ, , –, , 10 V, , 2 kΩ, vi, 0, , T, 2, , –, Figure 2.64, region of vi., , –, , t, 2 kΩ, , +, , vo, , vo, , –, , vi, , +, , 2 kΩ, 2 kΩ, , Network of Fig. 2.63 for the positive, , vo, 5V, 2 kΩ, 0, , T, 2, , t, , –, Figure 2.65, , Redrawn network of Fig. 2.64., , The effect of removing two diodes from the bridge configuration was therefore to, reduce the available dc level to the following:, , vo, 5V, , Vdc 0.636(5 V) 3.18 V, or that available from a half-wave rectifier with the same input. However, the PIV as, determined from Fig. 2.58 is equal to the maximum voltage across R, which is 5 V, or half of that required for a half-wave rectifier with the same input., , 2.8 Full-Wave Rectification, , 0, , T, 2, , T, , t, , Figure 2.66 Resulting output, for Example 2.19., , 75
Page 87 :
2.9 CLIPPERS, There are a variety of diode networks called clippers that have the ability to “clip”, off a portion of the input signal without distorting the remaining part of the alternating waveform. The half-wave rectifier of Section 2.7 is an example of the simplest, form of diode clipper—one resistor and diode. Depending on the orientation of the, diode, the positive or negative region of the input signal is “clipped” off., There are two general categories of clippers: series and parallel. The series configuration is defined as one where the diode is in series with the load, while the parallel variety has the diode in a branch parallel to the load., , Series, The response of the series configuration of Fig. 2.67a to a variety of alternating waveforms is provided in Fig. 2.67b. Although first introduced as a half-wave rectifier (for, sinusoidal waveforms), there are no boundaries on the type of signals that can be applied to a clipper. The addition of a dc supply such as shown in Fig. 2.68 can have a, pronounced effect on the output of a clipper. Our initial discussion will be limited to, ideal diodes, with the effect of VT reserved for a concluding example., , +, , +, vi, , R, , vo, , –, , –, (a), , vi, , vo, , V, , 0, , V, , t, , vo, , vi, V, , V, , t, , –V, , t, , t, , –V, (b), , Figure 2.67, , Series clipper., , Figure 2.68, a dc supply., , Series clipper with, , There is no general procedure for analyzing networks such as the type in Fig., 2.68, but there are a few thoughts to keep in mind as you work toward a solution., 1. Make a mental sketch of the response of the network based on the direction of the diode and the applied voltage levels., For the network of Fig. 2.68, the direction of the diode suggests that the signal vi, must be positive to turn it on. The dc supply further requires that the voltage vi be, greater than V volts to turn the diode on. The negative region of the input signal is, 76, , Chapter 2, , Diode Applications
Page 88 :
“pressuring” the diode into the “off” state, supported further by the dc supply. In general, therefore, we can be quite sure that the diode is an open circuit (“off” state) for, the negative region of the input signal., 2. Determine the applied voltage (transition voltage) that will cause a change, in state for the diode., For the ideal diode the transition between states will occur at the point on the, characteristics where vd 0 V and id 0 A. Applying the condition id 0 at vd , 0 to the network of Fig. 2.68 will result in the configuration of Fig. 2.69, where it is, recognized that the level of vi that will cause a transition in state is, vi V, , V, , vd = 0 V, , +, , –, , (2.14), , id = 0 A, , +, , +, , vi, , R, , –, , vo = iRR = id R = (0)R = 0 V, , Figure 2.69 Determining the, transition level for the circuit of, Fig. 2.68., , –, , For an input voltage greater than V volts the diode is in the short-circuit state, while, for input voltages less than V volts it is in the open-circuit or “off” state., 3. Be continually aware of the defined terminals and polarity of vo., When the diode is in the short-circuit state, such as shown in Fig. 2.70, the output voltage vo can be determined by applying Kirchhoff’s voltage law in the clockwise direction:, , Figure 2.70, , Determining vo., , Figure 2.71, levels of vo., , Determining, , vi V vo 0 (CW direction), vo vi V, , and, , (2.15), , 4. It can be helpful to sketch the input signal above the output and determine, the output at instantaneous values of the input., It is then possible that the output voltage can be sketched from the resulting data, points of vo as demonstrated in Fig. 2.71. Keep in mind that at an instantaneous value, of vi the input can be treated as a dc supply of that value and the corresponding dc, value (the instantaneous value) of the output determined. For instance, at vi Vm, for the network of Fig. 2.68, the network to be analyzed appears in Fig. 2.72. For Vm, V the diode is in the short-circuit state and vo Vm V, as shown in Fig. 2.71., At vi V the diodes change state; at vi Vm, vo 0 V; and the complete curve, for vo can be sketched as shown in Fig. 2.73., vi, , vo, Vm, , Vm – V, , V, 0, , T, 2, , T, , t, , 0, , T, 2, , T, , t, , vi = V (diodes change state), , Figure 2.72, , Determining vo when vi Vm., , Figure 2.73, , Sketching vo., , 2.9 Clippers, , 77
Page 89 :
EXAMPLE 2.20, , Determine the output waveform for the network of Fig. 2.74., , Figure 2.74 Series clipper for, Example 2.20., , Solution, Past experience suggests that the diode will be in the “on” state for the positive region of vi —especially when we note the aiding effect of V 5 V. The network will, then appear as shown in Fig. 2.75 and vo vi 5 V. Substituting id 0 at vd 0 for, the transition levels, we obtain the network of Fig. 2.76 and vi 5 V., , Figure 2.75 vo with diode in, the “on” state., , – +, +, , vd = 0 V, , +, , 5 V id = 0 A, , vi, , vo = vR = iR R = id R = (0) R = 0 V, , R, , –, , Figure 2.76 Determining the, transition level for the clipper of, Fig. 2.74., , –, , For vi more negative than 5 V the diode will enter its open-circuit state, while, for voltages more positive than 5 V the diode is in the short-circuit state. The input, and output voltages appear in Fig. 2.77., vo, , vi, , vi + 5 V = 20 V + 5 V = 25 V, , 20, , vo = 0 V + 5 V = 5 V, , 5V, –5V, , T, 2, , T, , t, , 0, , Transition, voltage, , Figure 2.77, , T, 2, , T, , t, , vo = –5 V + 5 V = 0 V, , Sketching vo for Example 2.20., , The analysis of clipper networks with square-wave inputs is actually easier to analyze than with sinusoidal inputs because only two levels have to be considered. In, other words, the network can be analyzed as if it had two dc level inputs with the resulting output vo plotted in the proper time frame., 78, , Chapter 2, , Diode Applications
Page 90 :
EXAMPLE 2.21, , Repeat Example 2.20 for the square-wave input of Fig. 2.78., , Figure 2.78 Applied signal for, Example 2.21., , Solution, For vi 20 V (0 → T/ 2) the network of Fig. 2.79 will result. The diode is in the shortcircuit state and vo 20 V 5 V 25 V. For vi 10 V the network of Fig. 2.80, will result, placing the diode in the “off” state and vo iRR (0)R 0 V. The resulting output voltage appears in Fig. 2.81., , –, , +, , 5V, , +, , +, R, , 20 V, , –, , –, , vo, , +, , 5V, , vo = 0 V, , R, , 10 V, , +, , –, , Figure 2.79, , – +, , vo at vi 20 V., , –, , Figure 2.80, , vo at vi 10 V., , Figure 2.81 Sketching vo for, Example 2.21., , Note in Example 2.21 that the clipper not only clipped off 5 V from the total, swing but raised the dc level of the signal by 5 V., , Parallel, The network of Fig. 2.82 is the simplest of parallel diode configurations with the output for the same inputs of Fig. 2.67. The analysis of parallel configurations is very, similar to that applied to series configurations, as demonstrated in the next example., , +, , vi, , vi, , vo, , –, , –, , vo, , vi, , V, , 0, –V, , Figure 2.82, , +, , R, , vo, , V, t, , 0, –V, , t, , 0, , t, , 0, , t, , –V, , –V, , Response to a parallel clipper., , 2.9 Clippers, , 79
Page 91 :
EXAMPLE 2.2, , Determine vo for the network of Fig. 2.83., , Figure 2.83, , Example 2.22., , Solution, The polarity of the dc supply and the direction of the diode strongly suggest that the, diode will be in the “on” state for the negative region of the input signal. For this region the network will appear as shown in Fig. 2.84, where the defined terminals for, vo require that vo V 4 V., , –, , +, , R, , vi, , vo = V = 4 V, V, , +, , 4V, , –, , Figure 2.84, region of vi., , vo for the negative, , The transition state can be determined from Fig. 2.85, where the condition id , 0 A at vd 0 V has been imposed. The result is vi (transition) V 4 V., Since the dc supply is obviously “pressuring” the diode to stay in the shortcircuit state, the input voltage must be greater than 4 V for the diode to be in the “off”, state. Any input voltage less than 4 V will result in a short-circuited diode., For the open-circuit state the network will appear as shown in Fig. 2.86, where, vo vi. Completing the sketch of vo results in the waveform of Fig. 2.87., Figure 2.85 Determining the, transition level for Example 2.22., , Figure 2.87 Sketching vo for, Example 2.22., Figure 2.86 Determining vo for, the open state of the diode., , To examine the effects of VT on the output voltage, the next example will specify a silicon diode rather than an ideal diode equivalent., 80, , Chapter 2, , Diode Applications
Page 92 :
Repeat Example 2.22 using a silicon diode with VT 0.7 V., , EXAMPLE 2.23, , Solution, The transition voltage can first be determined by applying the condition id 0 A at, vd VD 0.7 V and obtaining the network of Fig. 2.88. Applying Kirchhoff’s voltage law around the output loop in the clockwise direction, we find that, vi VT V 0, and, , vi V VT 4 V 0.7 V 3.3 V, , Figure 2.88 Determining the, transition level for the network of, Fig. 2.83., , For input voltages greater than 3.3 V, the diode will be an open circuit and, vo vi. For input voltages of less than 3.3 V, the diode will be in the “on” state and, the network of Fig. 2.89 results, where, vo 4 V 0.7 V 3.3 V, , Figure 2.89 Determining vo for, the diode of Fig. 2.83 in the “on”, state., , The resulting output waveform appears in Fig. 2.90. Note that the only effect of VT, was to drop the transition level to 3.3 from 4 V., , Figure 2.90 Sketching vo for, Example 2.23., , There is no question that including the effects of VT will complicate the analysis, somewhat, but once the analysis is understood with the ideal diode, the procedure,, including the effects of VT, will not be that difficult., , Summary, A variety of series and parallel clippers with the resulting output for the sinusoidal, input are provided in Fig. 2.91. In particular, note the response of the last configuration, with its ability to clip off a positive and a negative section as determined by the, magnitude of the dc supplies., 2.9 Clippers, , 81
Page 93 :
Figure 2.91, , 82, , Chapter 2, , Clipping circuits., , Diode Applications
Page 94 :
2.10 CLAMPERS, The clamping network is one that will “clamp” a signal to a different dc level. The, network must have a capacitor, a diode, and a resistive element, but it can also employ an independent dc supply to introduce an additional shift. The magnitude of R, and C must be chosen such that the time constant RC is large enough to ensure, that the voltage across the capacitor does not discharge significantly during the interval the diode is nonconducting. Throughout the analysis we will assume that for all, practical purposes the capacitor will fully charge or discharge in five time constants., The network of Fig. 2.92 will clamp the input signal to the zero level (for ideal, diodes). The resistor R can be the load resistor or a parallel combination of the load, resistor and a resistor designed to provide the desired level of R., C, , +, V, , +, , V, , –, , +, R, , vo, , –, –, Figure 2.92, , Clamper., , During the interval 0 → T/2 the network will appear as shown in Fig. 2.93, with, the diode in the “on” state effectively “shorting out” the effect of the resistor R. The, resulting RC time constant is so small (R determined by the inherent resistance of the, network) that the capacitor will charge to V volts very quickly. During this interval, the output voltage is directly across the short circuit and vo 0 V., When the input switches to the V state, the network will appear as shown in, Fig. 2.94, with the open-circuit equivalent for the diode determined by the applied, signal and stored voltage across the capacitor—both “pressuring” current through the, diode from cathode to anode. Now that R is back in the network the time constant, determined by the RC product is sufficiently large to establish a discharge period 5, much greater than the period T/2 → T, and it can be assumed on an approximate basis that the capacitor holds onto all its charge and, therefore, voltage (since V Q/C), during this period., Since vo is in parallel with the diode and resistor, it can also be drawn in the alternative position shown in Fig. 2.94. Applying Kirchhoff’s voltage law around the, input loop will result in, , Figure 2.93 Diode “on” and the, capacitor charging to V volts., , Figure 2.94 Determining vo, with the diode “off.”, , V V vo 0, and, , vo 2V, , The negative sign resulting from the fact that the polarity of 2V is opposite to the polarity defined for vo. The resulting output waveform appears in Fig. 2.95 with the input signal. The output signal is clamped to 0 V for the interval 0 to T/2 but maintains, the same total swing (2V) as the input., For a clamping network:, The total swing of the output is equal to the total swing of the input, signal., This fact is an excellent checking tool for the result obtained., In general, the following steps may be helpful when analyzing clamping networks:, 1. Start the analysis of clamping networks by considering that part of the input signal that will forward bias the diode., , Figure 2.95 Sketching vo for the, network of Fig. 2.92., , 2.10 Clampers, , 83
Page 95 :
The statement above may require skipping an interval of the input signal (as demonstrated in an example to follow), but the analysis will not be extended by an unnecessary measure of investigation., 2. During the period that the diode is in the “on” state, assume that the capacitor will charge up instantaneously to a voltage level determined by the, network., 3. Assume that during the period when the diode is in the “off” state the capacitor will hold on to its established voltage level., 4. Throughout the analysis maintain a continual awareness of the location, and reference polarity for vo to ensure that the proper levels for vo are obtained., 5. Keep in mind the general rule that the total swing of the total output must, match the swing of the input signal., , EXAMPLE 2.24, , Determine vo for the network of Fig. 2.96 for the input indicated., , Figure 2.96, , Applied signal and network for Example 2.24., , Solution, , Figure 2.97 Determining vo and, VC with the diode in the “on”, state., , Note that the frequency is 1000 Hz, resulting in a period of 1 ms and an interval of, 0.5 ms between levels. The analysis will begin with the period t1 → t2 of the input, signal since the diode is in its short-circuit state as recommended by comment 1. For, this interval the network will appear as shown in Fig. 2.97. The output is across R,, but it is also directly across the 5-V battery if you follow the direct connection between the defined terminals for vo and the battery terminals. The result is vo 5 V, for this interval. Applying Kirchhoff’s voltage law around the input loop will result in, 20 V VC 5 V 0, VC 25 V, , and, , The capacitor will therefore charge up to 25 V, as stated in comment 2. In this, case the resistor R is not shorted out by the diode but a Thévenin equivalent circuit, of that portion of the network which includes the battery and the resistor will result, in RTh 0 with ETh V 5 V. For the period t2 → t3 the network will appear as, shown in Fig. 2.98., The open-circuit equivalent for the diode will remove the 5-V battery from having any effect on vo, and applying Kirchhoff’s voltage law around the outside loop of, the network will result in, 10 V 25 V vo 0, , Figure 2.98 Determining vo, with the diode in the “off” state., , and, , 84, , Chapter 2, , vo 35 V, Diode Applications
Page 96 :
The time constant of the discharging network of Fig. 2.98 is determined by the, product RC and has the magnitude, RC (100 k)(0.1 F) 0.01 s 10 ms, The total discharge time is therefore 5 5(10 ms) 50 ms., Since the interval t2 → t3 will only last for 0.5 ms, it is certainly a good approximation that the capacitor will hold its voltage during the discharge period between pulses, of the input signal. The resulting output appears in Fig. 2.99 with the input signal., Note that the output swing of 30 V matches the input swing as noted in step 5., , Figure 2.99 vi and vo for the, clamper of Fig. 2.96., , Repeat Example 2.24 using a silicon diode with VT 0.7 V., , EXAMPLE 2.25, , Solution, For the short-circuit state the network now takes on the appearance of Fig. 2.100 and, vo can be determined by Kirchhoff’s voltage law in the output section., 5 V 0.7 V vo 0, and, , vo 5 V 0.7 V 4.3 V, , For the input section Kirchhoff’s voltage law will result in, 20 V VC 0.7 V 5 V 0, and, , VC 25 V 0.7 V 24.3 V, , For the period t2 → t3 the network will now appear as in Fig. 2.101, with the only, change being the voltage across the capacitor. Applying Kirchhoff’s voltage law yields, , Figure 2.100 Determining vo, and VC with the diode in the “on”, state., , 10 V 24.3 V vo 0, and, , vo 34.3 V, , Figure 2.101 Determining vo, with the diode in the open state., , 2.10 Clampers, , 85
Page 97 :
The resulting output appears in Fig. 2.102, verifying the statement that the input and, output swings are the same., , Figure 2.102 Sketching vo for, the clamper of Fig. 2.96 with a, silicon diode., , A number of clamping circuits and their effect on the input signal are shown in, Fig. 2.103. Although all the waveforms appearing in Fig. 2.103 are square waves,, clamping networks work equally well for sinusoidal signals. In fact, one approach to, the analysis of clamping networks with sinusoidal inputs is to replace the sinusoidal, signal by a square wave of the same peak values. The resulting output will then form, an envelope for the sinusoidal response as shown in Fig. 2.104 for a network appearing in the bottom right of Fig. 2.103., , Figure 2.103 Clamping circuits with ideal diodes (5 5RC T/2)., , 86, , Chapter 2, , Diode Applications
Page 98 :
vo (V), vi, , +30, 20 V, , +, t, , 0, , –20 V, , +, , C, , –, , vi, , R, , vo, , 10 V, , +, , –, , t, , 0, –10 V, , –, , Figure 2.104 Clamping network with a sinusoidal input., , 2.11 ZENER DIODES, The analysis of networks employing Zener diodes is quite similar to that applied to, the analysis of semiconductor diodes in previous sections. First the state of the diode, must be determined followed by a substitution of the appropriate model and a determination of the other unknown quantities of the network. Unless otherwise specified,, the Zener model to be employed for the “on” state will be as shown in Fig. 2.105a., For the “off” state as defined by a voltage less than VZ but greater than 0 V with the, polarity indicated in Fig. 2.105b, the Zener equivalent is the open circuit that appears, in the same figure., , Figure 2.105 Zener diode, equivalents for the (a) “on” and, (b) “off” states., , V, , i, , and R, , The simplest of Zener diode networks appears in Fig. 2.106. The applied dc voltage, is fixed, as is the load resistor. The analysis can fundamentally be broken down into, two steps., 1. Determine the state of the Zener diode by removing it from the network, and calculating the voltage across the resulting open circuit., , Figure 2.106 Basic Zener regulator., , Applying step 1 to the network of Fig. 2.106 will result in the network of Fig., 2.107, where an application of the voltage divider rule will result in, R Vi, V VL L, R RL, , (2.16), , If V VZ, the Zener diode is “on” and the equivalent model of Fig. 2.105a can be, substituted. If V VZ, the diode is “off” and the open-circuit equivalence of Fig., 2.105b is substituted., 2.11 Zener Diodes, , Figure 2.107 Determining the, state of the Zener diode., , 87
Page 99 :
2. Substitute the appropriate equivalent circuit and solve for the desired unknowns., For the network of Fig. 2.106, the “on” state will result in the equivalent network, of Fig. 2.108. Since voltages across parallel elements must be the same, we find that, VL VZ, , (2.17), , The Zener diode current must be determined by an application of Kirchhoff’s current, law. That is,, Figure 2.108 Substituting the, Zener equivalent for the “on” situation., , IR IZ IL, IZ IR IL, , and, , (2.18), , where, VL, IL , RL, , and, , VR, Vi VL, IR , , , R, R, , The power dissipated by the Zener diode is determined by, PZ VZ IZ, , (2.19), , which must be less than the PZM specified for the device., Before continuing, it is particularly important to realize that the first step was employed only to determine the state of the Zener diode. If the Zener diode is in the, “on” state, the voltage across the diode is not V volts. When the system is turned on,, the Zener diode will turn “on” as soon as the voltage across the Zener diode is VZ, volts. It will then “lock in” at this level and never reach the higher level of V volts., Zener diodes are most frequently used in regulator networks or as a reference, voltage. Figure 2.106 is a simple regulator designed to maintain a fixed voltage across, the load RL. For values of applied voltage greater than required to turn the Zener diode, “on,” the voltage across the load will be maintained at VZ volts. If the Zener diode is, employed as a reference voltage, it will provide a level for comparison against other, voltages., , EXAMPLE 2.26, , (a) For the Zener diode network of Fig. 2.109, determine VL, VR, IZ, and PZ., (b) Repeat part (a) with RL = 3 k., , Figure 2.109 Zener diode, regulator for Example 2.26., , Solution, (a) Following the suggested procedure the network is redrawn as shown in Fig., 2.110. Applying Eq. (2.16) gives, R Vi, 1.2 k(16 V), 8.73 V, V L, R RL, 1 k 1.2 k, 88, , Chapter 2, , Diode Applications
Page 100 :
Figure 2.110 Determining V for, the regulator of Fig. 2.109., , Since V 8.73 V is less than VZ 10 V, the diode is in the “off” state as shown, on the characteristics of Fig. 2.111. Substituting the open-circuit equivalent will result in the same network as in Fig. 2.110, where we find that, VL V 8.73 V, VR Vi VL 16 V 8.73 V 7.27 V, IZ 0 A, and, , Figure 2.111 Resulting operating point for the network of Fig., 2.109., , PZ VZIZ VZ (0 A) 0 W, , (b) Applying Eq. (2.16) will now result in, R Vi, 3 k(16 V), V L, 12 V, R RL, 1 k 3 k, Since V 12 V is greater than VZ 10 V, the diode is in the “on” state and the network of Fig. 2.112 will result. Applying Eq. (2.17) yields, VL VZ 10 V, VR Vi VL 16 V 10 V 6 V, , and, with, , VL, 10 V, IL , 3.33 mA, RL, 3 k, , and, , VR, 6V, IR , 6 mA, R, 1 k, , so that, , IZ IR IL [Eq. (2.18)], 6 mA 3.33 mA, 2.67 mA, , The power dissipated,, PZ VZIZ (10 V)(2.67 mA) 26.7 mW, which is less than the specified PZM 30 mW., , Figure 2.112 Network of Fig., 2.109 in the “on” state., , 2.11 Zener Diodes, , 89
Page 101 :
Fixed Vi, Variable RL, Due to the offset voltage VZ, there is a specific range of resistor values (and therefore, load current) which will ensure that the Zener is in the “on” state. Too small a load, resistance RL will result in a voltage VL across the load resistor less than VZ , and the, Zener device will be in the “off” state., To determine the minimum load resistance of Fig. 2.106 that will turn the Zener, diode on, simply calculate the value of RL that will result in a load voltage VL VZ., That is,, R Vi, VL VZ L, RL R, Solving for RL, we have, RVZ, RLmin , Vi VZ, , (2.20), , Any load resistance value greater than the RL obtained from Eq. (2.20) will ensure, that the Zener diode is in the “on” state and the diode can be replaced by its VZ source, equivalent., The condition defined by Eq. (2.20) establishes the minimum RL but in turn specifies the maximum IL as, VL, VZ, ILmax , , RL, RLmin, , (2.21), , Once the diode is in the “on” state, the voltage across R remains fixed at, VR Vi VZ, , (2.22), , VR, IR , R, , (2.23), , IZ IR IL, , (2.24), , and IR remains fixed at, , The Zener current, , resulting in a minimum IZ when IL is a maximum and a maximum IZ when IL is a, minimum value since IR is constant., Since IZ is limited to IZM as provided on the data sheet, it does affect the range, of RL and therefore IL. Substituting IZM for IZ establishes the minimum IL as, ILmin IR IZM, , (2.25), , and the maximum load resistance as, VZ, RLmax , ILmin, , 90, , Chapter 2, , Diode Applications, , (2.26)
Page 102 :
(a) For the network of Fig. 2.113, determine the range of RL and IL that will result, in VRL being maintained at 10 V., (b) Determine the maximum wattage rating of the diode., , EXAMPLE 2.27, , Figure 2.113 Voltage regulator, for Example 2.27., , Solution, (a) To determine the value of RL that will turn the Zener diode on, apply Eq. (2.20):, RVZ, (1 k)(10 V), 10 k, RLmin , 250 , Vi VZ, 50 V 10 V, 40, The voltage across the resistor R is then determined by Eq. (2.22):, VR Vi VZ 50 V 10 V 40 V, and Eq. (2.23) provides the magnitude of IR:, VR, 40 V, IR , 40 mA, R, 1 k, The minimum level of IL is then determined by Eq. (2.25):, ILmin IR IZM 40 mA 32 mA 8 mA, with Eq. (2.26) determining the maximum value of RL:, VZ, 10 V, RLmax , 1.25 k, ILmin, 8 mA, A plot of VL versus RL appears in Fig. 2.114a and for VL versus IL in Fig. 2.114b., (b) Pmax VZ IZM, (10 V)(32 mA) 320 mW, , Figure 2.114 VL versus RL and IL for the regulator of Fig. 2.113., , 2.11 Zener Diodes, , 91
Page 104 :
The results of Example 2.28 reveal that for the network of Fig. 2.115 with a fixed, RL, the output voltage will remain fixed at 20 V for a range of input voltage that extends from 23.67 to 36.87 V., In fact, the input could appear as shown in Fig. 2.117 and the output would remain constant at 20 V, as shown in Fig. 2.116. The waveform appearing in Fig. 2.117, is obtained by filtering a half-wave- or full-wave-rectified output—a process described, in detail in a later chapter. The net effect, however, is to establish a steady dc voltage, (for a defined range of Vi) such as that shown in Fig. 2.116 from a sinusoidal source, with 0 average value., , Figure 2.117 Waveform generated by a filtered rectified signal., , Two or more reference levels can be established by placing Zener diodes in series, as shown in Fig. 2.118. As long as Vi is greater than the sum of VZ1 and VZ2, both, diodes will be in the “on” state and the three reference voltages will be available., Two back-to-back Zeners can also be used as an ac regulator as shown in Fig., 2.119a. For the sinusoidal signal vi the circuit will appear as shown in Fig. 2.119b at, the instant vi 10 V. The region of operation for each diode is indicated in the adjoining figure. Note that Z1 is in a low-impedance region, while the impedance of Z2, is quite large, corresponding with the open-circuit representation. The result is that, vo vi when vi 10 V. The input and output will continue to duplicate each other, until vi reaches 20 V. Z2 will then “turn on” (as a Zener diode), while Z1 will be in a, vi, , +, , vo, , +, , 5 kΩ, , 22 V, , Figure 2.118 Establishing three, reference voltage levels., , Z1, ωt, , 0, –22 V, , vi, , vo, , 20-V, Zeners, Z2, , –, , 20 V, 0, , 20 V, , ωt, , –, (a), , I, , +, , 5 kΩ, , –, +, , vi = 10 V, , –, , Z1, , 20 V, 0, , V, , Z2, , (b), , Figure 2.119 Sinusoidal ac regulation: (a) 40-V peak-to-peak sinusoidal ac regulator; (b) circuit operation at vi 10 V., , 2.11 Zener Diodes, , 93
Page 105 :
region of conduction with a resistance level sufficiently small compared to the series, 5-k resistor to be considered a short circuit. The resulting output for the full range, of vi is provided in Fig. 2.119(a). Note that the waveform is not purely sinusoidal, but, its rms value is lower than that associated with a full 22-V peak signal. The network, is effectively limiting the rms value of the available voltage. The network of Fig., 2.119a can be extended to that of a simple square-wave generator (due to the clipping action) if the signal vi is increased to perhaps a 50-V peak with 10-V Zeners as, shown in Fig. 2.120 with the resulting output waveform., vi, , 50 V, , 0, , +, , 5 kΩ, , vi, , 10-V, Zeners, , vo, , +, , +, Z1, , π, , 2π ω t, , –, +, , vo, , –10 V, , Z2, , –, , –, , 10 V, , –, , Figure 2.120 Simple square-wave generator., , 2.12 VOLTAGE-MULTIPLIER CIRCUITS, Voltage-multiplier circuits are employed to maintain a relatively low transformer peak, voltage while stepping up the peak output voltage to two, three, four, or more times, the peak rectified voltage., , Voltage Doubler, The network of Figure 2.121 is a half-wave voltage doubler. During the positive voltage half-cycle across the transformer, secondary diode D1 conducts (and diode D2 is, cut off), charging capacitor C1 up to the peak rectified voltage (Vm). Diode D1 is ideally a short during this half-cycle, and the input voltage charges capacitor C1 to Vm, with the polarity shown in Fig. 2.122a. During the negative half-cycle of the secondary voltage, diode D1 is cut off and diode D2 conducts charging capacitor C2., Since diode D2 acts as a short during the negative half-cycle (and diode D1 is open),, we can sum the voltages around the outside loop (see Fig. 2.122b):, Vm VC1 VC2 0, Vm Vm VC2 0, from which, VC 2 2Vm, , Figure 2.121 Half-wave voltage, doubler., , 94, , Chapter 2, , Diode Applications
Page 106 :
Figure 2.122 Double operation, showing each half-cycle of, operation: (a) positive half-cycle;, (b) negative half cycle., , On the next positive half-cycle, diode D2 is nonconducting and capacitor C2 will discharge through the load. If no load is connected across capacitor C2, both capacitors, stay charged—C1 to Vm and C2 to 2Vm. If, as would be expected, there is a load connected to the output of the voltage doubler, the voltage across capacitor C2 drops during the positive half-cycle (at the input) and the capacitor is recharged up to 2Vm during the negative half-cycle. The output waveform across capacitor C2 is that of a, half-wave signal filtered by a capacitor filter. The peak inverse voltage across each, diode is 2Vm., Another doubler circuit is the full-wave doubler of Fig. 2.123. During the positive half-cycle of transformer secondary voltage (see Fig. 2.124a) diode D1 conducts, charging capacitor C1 to a peak voltage Vm. Diode D2 is nonconducting at this time., , Figure 2.123 Full-wave voltage, doubler., , D1, , Conducting, , +, , Nonconducting, , –, C1, , Vm, , D1, , +, –, , Vm, , –, , C1, , Vm, , +, –, , Vm, , +, +, C2, , D2, (a), , –, , +, Vm, , C2, , D2, , Nonconducting, , –, , Vm, , Conducting, , (b), , 2.12 Voltage-Multiplier Circuits, , Figure 2.124 Alternate halfcycles of operation for full-wave, voltage doubler., , 95
Page 107 :
During the negative half-cycle (see Fig. 2.124b) diode D2 conducts charging capacitor C2 while diode D1 is nonconducting. If no load current is drawn from the circuit, the voltage across capacitors C1 and C2 is 2Vm. If load current is drawn from the, circuit, the voltage across capacitors C1 and C2 is the same as that across a capacitor, fed by a full-wave rectifier circuit. One difference is that the effective capacitance, is that of C1 and C2 in series, which is less than the capacitance of either C1 or C2, alone. The lower capacitor value will provide poorer filtering action than the singlecapacitor filter circuit., The peak inverse voltage across each diode is 2Vm , as it is for the filter capacitor, circuit. In summary, the half-wave or full-wave voltage-doubler circuits provide twice, the peak voltage of the transformer secondary while requiring no center-tapped transformer and only 2Vm PIV rating for the diodes., , Voltage Tripler and Quadrupler, Figure 2.125 shows an extension of the half-wave voltage doubler, which develops, three and four times the peak input voltage. It should be obvious from the pattern of, the circuit connection how additional diodes and capacitors may be connected so that, the output voltage may also be five, six, seven, and so on, times the basic peak, voltage (Vm)., , Figure 2.125 Voltage tripler and quadrupler., , In operation capacitor C1 charges through diode D1 to a peak voltage, Vm, during, the positive half-cycle of the transformer secondary voltage. Capacitor C2 charges to, twice the peak voltage 2Vm developed by the sum of the voltages across capacitor C1, and the transformer, during the negative half-cycle of the transformer secondary voltage., During the positive half-cycle, diode D3 conducts and the voltage across capacitor C2 charges capacitor C3 to the same 2Vm peak voltage. On the negative halfcycle, diodes D2 and D4 conduct with capacitor C3, charging C4 to 2Vm., The voltage across capacitor C2 is 2Vm, across C1 and C3 it is 3Vm, and across C2, and C4 it is 4Vm. If additional sections of diode and capacitor are used, each capacitor will be charged to 2Vm. Measuring from the top of the transformer winding (Fig., 2.125) will provide odd multiples of Vm at the output, whereas measuring the output, voltage from the bottom of the transformer will provide even multiples of the peak, voltage, Vm., The transformer rating is only Vm, maximum, and each diode in the circuit must, be rated at 2Vm PIV. If the load is small and the capacitors have little leakage, extremely high dc voltages may be developed by this type of circuit, using many sections to step up the dc voltage., 96, , Chapter 2, , Diode Applications
Page 108 :
2.13 PSPICE WINDOWS, Series Diode Configuration, PSpice Windows will now be applied to the network of Fig. 2.27 to permit a comparison with the hand-calculated solution. As briefly described in Chapter 1, the application of PSpice Windows requires that the network first be constructed on the, schematics screen. The next few paragraphs will examine the basics of setting up the, network on the screen, assuming no prior experience with the process. It might be, helpful to reference the completed network of Fig. 2.126 as we progress through the, discussion., , Figure 2.126 PSpice Windows, analysis of a series diode, configuration., , In general, it is easier to draw the network if the grid is on the screen and the stipulation is made that all elements be on the grid. This will ensure that all the connections are made between the elements. The screen can be set up by first choosing Options at the heading of the schematics screen, followed by Display Options. The, Display Options dialog box will permit you to make all the choices necessary regarding the type of display desired. For our purposes, we will choose Grid On, Stay, on Grid, and Grid Spacing of 0.1 in., , R, The resistor R will be the first to be positioned. By clicking on the Get New Part, icon (the icon in the top right area with the binoculars) followed by Libraries, we, can choose the Analog.slb library of basic elements. We can then scroll the Part list, until we find R. Clicking on R followed by OK will result in the Part Browser Basic dialog box reflecting our choice of a resistive element. Choosing the Place &, Close option will place the resistive element on the screen and close the dialog box., The resistor will appear horizontal, which is perfect for the R1 of Fig. 2.27 (note Fig., 2.126). Move the resistor to a logical location, and click the left button of the mouse—, the resistor R1 is in place. Note that it snaps to the grid structure. The resistor R2 must, now be placed to the right of R1. By simply moving the mouse to the right, the second resistor will appear, and R2 can be placed in the proper location with a subsequent click of the mouse. Since the network only has two resistors, the depositing of, resistors can be ended by a right click of the mouse. The resistor R2 can be rotated, by pressing the keys Ctrl and R simultaneously or by choosing Edit on the menu, bar, followed by Rotate., The result of the above is two resistors with the right labels but the wrong values. To change a value, double click on the value of the screen (first R1). A Set Attribute Value dialog box will appear. Type in the correct value, and send the value, to the screen with OK. The 4.7k will appear within a box that can be moved by, simply clicking on the small box and, while holding the clicker down, moving the, 4.7k to the desired location. Release the clicker, and the 4.7k label will remain, where placed. Once located, an additional click anywhere on the screen will remove, the boxes and end the process. If you want to move the 4.7k in the future, simply, click once on the value and the boxes will reappear. Repeat the above for the value, of the resistor R2., 2.13 PSpice Windows, , 97
Page 109 :
To remove (clip) an element, simply click on it (to establish the red or active, color), and then click the scissors icon or use the sequence Edit-Delete., E, The voltage sources are set by going to the source.slb library of Library Browser, and choosing VDC. Clicking OK results in the source symbol appearing on the, schematic. This symbol can be placed as required. After clicking it in the appropriate place, a V1 label will appear. To change the label to E1 simply click the V1 twice, and an Edit Reference Designator dialog box will appear. Change the label to E1, and click OK, and then E1 will appear on the screen within a box. The box can be, moved in the same manner as the labels for resistors. When you have the correct position, simply click the mouse once more and place E1 as desired., To set the value of E1, click the value twice and the Set Attribute Value will appear. Set the value to 10V and click OK. The new value will appear on the schematic., The value can also be set by clicking the battery symbol itself twice, after which a, dialog box will appear labeled E1 PartName:VDC. By choosing DC 0V, DC and, Value will appear in the designated areas at the top of the dialog box. Using the, mouse, bring the marker to the Value box and change it to 10V. Then click Save Attr., to be sure and save the new value, and an OK will result in E1 being changed to 10V., E1 can now be set, but be sure to turn it 180° with the appropriate operations., DIODE, The diode is found in the EVAL.slb library of the Library Browser dialog box., Choosing the D1N4148 diode followed by an OK and Close & Place will place the, diode symbol on the screen. Move the diode to the correct position, click it in place, with a left click, and end the operation with a right click of the mouse. The labels D1, and D1N4148 will appear near the diode. Clicking on either label will provide the, boxes that permit movement of the labels., Let us now take a look at the diode specs by clicking the diode symbol once, followed by the Edit-Model-Edit Instance Model sequence. For the moment, we will, leave the parameters as listed. In particular, note that Is 2.682nA and the terminal, capacitance (important when the applied frequency becomes a factor) is 4pF., IPROBE, One or more currents of a network can be displayed by inserting an IPROBE in, the desired path. IPROBE is found in the SPECIAL.slb library and appears as a meter face on the screen. IPROBE will respond with a positive answer if the current, (conventional) enters the symbol at the end with the arc representing the scale. Since, we are looking for a positive answer in this investigation, IPROBE should be installed as shown in Fig. 2.126. When the symbol first appears, it is 180° out of phase, with the desired current. Therefore, it is necessary to use the Ctrl-R sequence twice, to rotate the symbol before finalizing its position. As with the elements described, above, once it is in place a single click will place the meter and a right click will complete the insertion process., LINE, The elements now need to be connected by choosing the icon with the thin line, and pencil or by the sequence Draw-Wire. A pencil will appear that can draw the desired connections in the following manner: Move the pencil to the beginning of the, line, and click the left side of the mouse. The pencil is now ready to draw. Draw the, desired line (connection), and click the left side again when the connection is complete. The line will appear in red, waiting for another random click of the mouse or, 98, , Chapter 2, , Diode Applications
Page 110 :
the insertion of another line. It will then turn geen to indicate it is in memory. For, additional lines, simply repeat the procedure. When done, simply click the right side, of the mouse., EGND, The system must have a ground to serve as a reference point for the nodal voltages. Earth ground (EGND) is part of the PORT.slb library and can be placed in the, same manner as the elements described above., VIEWPOINT, Nodal voltages can be displayed on the diagram after the simulation using VIEWPOINTS, which is found in the SPECIAL.slb library. Simply place the arrow of the, VIEWPOINT symbol where you desire the voltage with respect to ground. A VIEWPOINT can be placed at every node of the network if necessary, although only three, are placed in Fig. 2.126. The network is now complete, as shown in Fig 2.126., ANALYSIS, The network is now ready to be analyzed. To expedite the process, click on Analysis and choose Probe Setup. By selecting Do not auto-run Probe you save intermediary steps that are inappropriate for this analysis; it is an option that will be discussed later in this chapter. After OK, go to Analysis and choose Simulation. If the, network was installed properly, a PSpiceAD dialog box will appear and reveal that, the bias (dc) points have been calculated. If we now exit the box by clicking on the, small x in the top right corner, you will obtain the results appearing in Fig. 2.126., Note that the program has automatically provided four dc voltages of the network, (in addition to the VIEWPOINT voltages). This occurred because an option under, analysis was enabled. For future analysis we will want control over what is displayed, so follow the path through Analysis-Display Results on Schematic and slide over to, the adjoining Enable box. Clicking the Enable box will remove the check, and the, dc voltages will not automatically appear. They will only appear where VIEWPOINTS have been inserted. A more direct path toward controlling the appearance, of the dc voltages is to use the icon on the menu bar with the large capital V. By clicking it on and off, you can control whether the dc levels of the network will appear., The icon with the large capital I will permit all the dc currents of the network to be, shown if desired. For practice, click it on and off and note the effect on the schematic., If you want to remove selected dc voltages on the schematic, simply click the nodal, voltage of interest, then click the icon with the smaller capital V in the same grouping. Clicking it once will remove the selected dc voltage. The same can be done for, selected currents with the remaining icon of the group. For the future, it should be, noted that an analysis can also be initiated by simply clicking the Simulation icon, having the yellow background and the two waveforms (square wave and sinusoidal)., Note also that the results are not an exact match with those obtained in Example, 2.11. The VIEWPOINT voltage at the far right is 421.56 rather than the 454.2, mV obtained in Example 2.11. In addition, the current is 2.081 rather than the 2.066, mA obtained in the same example. Further, the voltage across the diode is 281.79 mV, 421.56 mV 0.64 V rather than the 0.7 V assumed for all silicon diodes. This all, results from our using a real diode with a long list of variables defining its operation., However, it is important to remember that the analysis of Example 2.11 was an approximate one and, therefore, it is expected that the results are only close to the actual response. On the other hand, the results obtained for the nodal voltage and current are quite close. If taken to the tenths place, the currents (2.1 mA) are an exact match., The results obtained in Fig. 2.126 can be improved (in the sense that they will be, a closer match to the hand-written solution) by clicking on the diode (to make it red), 2.13 PSpice Windows, , 99
Page 111 :
Figure 2.127 The circuit of Figure 2.126 reexamined with, Is set to 3.5E-15A., , and using the sequence Edit-Model-Edit Instance Model (Text) to obtain the Model, Editor dialog box. Choose Is 3.5E-15A (a value determined by trial and error),, and delete all the other parameters for the device. Then, follow with OK-Simulate, icon to obtain the results of Fig. 2.127. Note that the voltage across the diode now is, 260.17 mV 440.93 mV 0.701 V, or almost exactly 0.7 V. The VIEWPOINT voltage is 440.93 V or, again, an almost perfect match with the hand-written solution, of 0.44 V. In either case, the results obtained are very close to the expected values., One is more accurate as far as the actual device is concerned, while the other provides, an almost exact match with the hand-written solution. One cannot expect a perfect, match for every diode network by simply setting Is to 3.5E-15A. As the current through, the diode changes, the level of Is must also change if an exact match with the handwritten solution is to be obtained. However, rather than worry about the current in, each system, it is suggested that Is 3.5E-15A be used as the standard value if the, PSpice solution is desired to be a close match with the hand-written solution. The results will not always be perfect, but in most cases they will be closer than if the parameters of the diode are left at their default values. For transistors in the chapters to, follow, it will be set to 2E-15A to obtain a suitable match with the hand-written solution. Note also that the Bias Current Display was enabled to show that the current, is indeed the same everywhere in the circuit., The results can also be viewed in tabulated form by returning to Analysis and, choosing Examine Output. The result is the long listing of Fig. 2.128. The Schematics Netlist describes the network in terms of numbered nodes. The 0 refers to ground, level, with the 10V source from node 0 to 5. The source E2 is from 0 to node 3. The, resistor R2 is connected from node 3 to 4, and so on. Scrolling down the output file,, we find the Diode MODEL PARAMETERS clearly showing that Is is set at 3.5E15A and is the only parameter listed. Next is the SMALL SIGNAL BIAS SOLUTION or dc solution with the voltages at the various nodes. In addition, the current, through the sources of the network is shown. The negative sign reveals that it is reflecting the direction of electron flow (into the positive terminal). The total power dissipation of the elements is 31.1 mW. Finally, the OPERATING POINT INFORMATION reveals that the current through the diode is 2.07 mA and the voltage across, the diode 0.701 V., The analysis is now complete for the diode circuit of interest. We have not touched, on all the alternative paths available through PSpice Windows, but sufficient coverage has been provided to examine any of the networks covered in this chapter with a, dc source. For practice, the other examples should be examined using the Windows, approach since the results are provided for comparison. The same can be said for the, odd-numbered exercises at the end of this chapter., , Diode Characteristics, The characteristics of the D1N4148 diode used in the above analysis will now be obtained using a few maneuvers somewhat more sophisticated than those employed previously. First, the network in Fig. 2.129 is constructed using the procedures described, 100, , Chapter 2, , Diode Applications
Page 112 :
Figure 2.128 Output file for, PSpice Windows analysis of the, circuit of Figure 2.127., , above. Note, however, the Vd appearing above the diode D1. A point in the network, (representing the voltage from anode to ground for the diode) has been identified as, a particular voltage by double-clicking on the wire above the device and typing Vd, in the Set Attribute Value as the LABEL. The resulting voltage Vd is, in this case,, the voltage across the diode., Next, Analysis Setup is chosen by either clicking on the Analysis Setup icon (at, the top left edge of the schematic with the horizontal blue bar and the two small, squares and rectangles) or by using the sequence Analysis-Setup. Within the Analysis-Setup dialog box the DC Sweep is enabled (the only one necessary for this exercise), followed by a single click of the DC Sweep rectangle. The DC Sweep dialog box will appear with various inquiries. In this case, we plan to sweep the source, voltage from 0 to 10 V in 0.01-V increments, so the Swept Var. Type is Voltage, Source, the Sweep Type will be linear, the Name E, and the Start Value 0V, the End, Value 10V, and the Increment 0.01V. Then, with an OK followed by a Close of the, 2.13 PSpice Windows, , Figure 2.129 Network to obtain the characteristics of the, D1N4148 diode., , 101
Page 113 :
Analysis Setup box, we are set to obtain the solution. The analysis to be performed, will obtain a complete solution for the network for each value of E from 0 to 10 V, in 0.01-V increments. In other words, the network will be analyzed 1000 times and, the resulting data stored for the plot to be obtained. The analysis is performed by the, sequence Analysis-Run Probe, followed by an immediate appearance of the MicroSim Probe graph showing only a horizontal axis of the source voltage E running, from 0 to 10 V., , Figure 2.130 Characteristics of, the D1N4148 diode., , Since the plot we want is of ID versus VD, we have to change the horizontal, (x-axis) to VD. This is accomplished by selecting Plot and then X-Axis Settings to, obtain the X Axis Settings dialog box. Next, we click Axis Variable and select V(Vd), from the listing. After OK, we return to the dialog box to set the horizontal scale., Choose User Defined, then enter 0V to 1V since this is the range of interest for Vd, with a Linear scale. Click OK and you will find that the horizontal axis is now V(Vd), with a range of 0 to 1.0 V. The vertical axis must now be set to ID by first choosing, Trace (or the Trace icon, which is the red waveform with two sharp peaks and a set, of axis) and then Add to obtain Add Traces. Choosing I(D1) and clicking OK will, result in the plot of Fig. 2.130. In this case, the resulting plot extended from 0 to 10 mA., The range can be reduced or expanded by simply going to Plot-Y-Axis Setting and, defining the range of interest., In the previous analysis, the voltage across the diode was 0.64 V, corresponding, to a current of about 2 mA on the graph (recall the solution of 2.07 mA for the current). If the resulting current had been closer to 6.5 mA, the voltage across the diode, would have been about 0.7 V and the PSpice solution closer to the hand-written approach. If Is had been set to 3.5E-15A and all other parameters removed from the, diode listing, the curve would have shifted to the right and an intersection of 0.7 V, and 2.07 mA would have obtained., , 102, , Chapter 2, , Diode Applications
Page 114 :
PROBLEMS, , § 2.2 Load-Line Analysis, 1. (a) Using the characteristics of Fig. 2.131b, determine ID, VD, and VR for the circuit of Fig., 2.131a., (b) Repeat part (a) using the approximate model for the diode and compare results., (c) Repeat part (a) using the ideal model for the diode and compare results., , Figure 2.131 Problems 1, 2, , 2. (a), (b), (c), (d), , Using the characteristics of Fig. 2.131b, determine ID and VD for the circuit of Fig. 2.132., Repeat part (a) with R 0.47 k., Repeat part (a) with R 0.18 k., Is the level of VD relatively close to 0.7 V in each case?, , Figure 2.132 Problems 2, 3, , How do the resulting levels of ID compare? Comment accordingly., 3. Determine the value of R for the circuit of Fig. 2.132 that will result in a diode current of 10, mA if E 7 V. Use the characteristics of Fig. 2.131b for the diode., 4. (a) Using the approximate characteristics for the Si diode, determine the level of VD, ID, and, VR for the circuit of Fig. 2.133., (b) Perform the same analysis as part (a) using the ideal model for the diode., (c) Do the results obtained in parts (a) and (b) suggest that the ideal model can provide a good, approximation for the actual response under some conditions?, Problems, , Figure 2.133 Problem 4, , 103
Page 115 :
§ 2.4 Series Diode Configurations with DC Inputs, 5. Determine the current I for each of the configurations of Fig. 2.134 using the approximate equivalent model for the diode., , Figure 2.134 Problem 5, , 6. Determine Vo and ID for the networks of Fig. 2.135., , Figure 2.135 Problems 6, 49, , * 7. Determine the level of Vo for each network of Fig. 2.136., , Figure 2.136 Problem 7, , * 8. Determine Vo and ID for the networks of Fig. 2.137., , Figure 2.137 Problem 8, , 104, , Chapter 2, , Diode Applications
Page 116 :
* 9. Determine Vo1 and Vo2 for the networks of Fig. 2.138., , Figure 2.138 Problem 9, , § 2.5 Parallel and Series–Parallel Configurations, 10. Determine Vo and ID for the networks of Fig. 2.139., , Figure 2.139 Problems 10, 50, , * 11. Determine Vo and I for the networks of Fig. 2.140., , Figure 2.140 Problem 11, , Problems, , 105
Page 117 :
12. Determine Vo1, Vo2, and I for the network of Fig. 2.141., * 13. Determine Vo and ID for the network of Fig. 2.142., , Figure 2.141 Problem 12, , Figure 2.142 Problems 13, 51, , § 2.6 AND/OR Gates, 14. Determine Vo for the network of Fig. 2.38 with 0 V on both inputs., 15. Determine Vo for the network of Fig. 2.38 with 10 V on both inputs., 16. Determine Vo for the network of Fig. 2.41 with 0 V on both inputs., 17. Determine Vo for the network of Fig. 2.41 with 10 V on both inputs., 18. Determine Vo for the negative logic OR gate of Fig. 2.143., 19. Determine Vo for the negative logic AND gate of Fig. 2.144., 20. Determine the level of Vo for the gate of Fig. 2.145., Figure 2.143 Problem 18, , 21. Determine Vo for the configuration of Fig. 2.146., , Figure 2.144 Problem 19, , Figure 2.145 Problem 20, , Figure 2.146, , Problem 21, , § 2.7 Sinusoidal Inputs; Half-Wave Rectification, 22. Assuming an ideal diode, sketch vi, vd, and id for the half-wave rectifier of Fig. 2.147. The input is a sinusoidal waveform with a frequency of 60 Hz, * 23. Repeat Problem 22 with a silicon diode (VT 0.7 V)., * 24. Repeat Problem 22 with a 6.8-k load applied as shown in Fig. 2.148. Sketch vL and iL., 25. For the network of Fig. 2.149, sketch vo and determine Vdc., , Figure 2.147 Problems 22, 23,, 24, , Figure 2.148 Problem 24, , 106, , Chapter 2, , Diode Applications, , Figure 2.149 Problem 25
Page 118 :
* 26. For the network of Fig. 2.150, sketch vo and iR., , Figure 2.150 Problem 26, , * 27. (a) Given Pmax 14 mW for each diode of Fig. 2.151, determine the maximum current rating, of each diode (using the approximate equivalent model)., (b) Determine Imax for Vimax 160 V., (c) Determine the current through each diode at Vimax using the results of part (b)., (e) If only one diode were present, determine the diode current and compare it to the maximum, rating., , Figure 2.151 Problem 27, , § 2.8 Full-Wave Rectification, 28. A full-wave bridge rectifier with a 120-V rms sinusoidal input has a load resistor of 1 k., (a) If silicon diodes are employed, what is the dc voltage available at the load?, (b) Determine the required PIV rating of each diode., (c) Find the maximum current through each diode during conduction., (d) What is the required power rating of each diode?, 29. Determine vo and the required PIV rating of each diode for the configuration of Fig. 2.152., , Figure 2.152 Problem 29, , Problems, , 107
Page 119 :
* 30. Sketch vo for the network of Fig. 2.153 and determine the dc voltage available., , Figure 2.153 Problem 30, , * 31. Sketch vo for the network of Fig. 2.154 and determine the dc voltage available., , Figure 2.154 Problem 31, , § 2.9 Clippers, 32. Determine vo for each network of Fig. 2.155 for the input shown., , Figure 2.155 Problem 32, , 33. Determine vo for each network of Fig. 2.156 for the input shown., , Figure 2.156 Problem 33, , 108, , Chapter 2, , Diode Applications
Page 120 :
* 34. Determine vo for each network of Fig. 2.157 for the input shown., , Figure 2.157 Problem 34, , * 35. Determine vo for each network of Fig. 2.158 for the input shown., , Figure 2.158 Problem 35, , 36. Sketch iR and vo for the network of Fig. 2.159 for the input shown., , Figure 2.159 Problem 36, , § 2.10 Clampers, 37. Sketch vo for each network of Fig. 2.160 for the input shown., , Figure 2.160 Problem 37, , Problems, , 109
Page 121 :
38. Sketch vo for each network of Fig. 2.161 for the input shown. Would it be a good approximation to consider the diode to be ideal for both configurations? Why?, , Figure 2.161 Problem 38, , * 39. For the network of Fig. 2.162:, (a), , Calculate 5 ., , (b) Compare 5 to half the period of the applied signal., (c), , Sketch vo., , Figure 2.162 Problem 39, , * 40. Design a clamper to perform the function indicated in Fig. 2.163., , Figure 2.163 Problem 40, , * 41. Design a clamper to perform the function indicated in Fig. 2.164., , Figure 2.164 Problem 41, , 110, , Chapter 2, , Diode Applications
Page 122 :
§ 2.11 Zener Diodes, * 42. (a) Determine VL, IL, IZ, and IR for the network Fig. 2.165 if RL 180 , (b) Repeat part (a) if RL 470 ., (c) Determine the value of RL that will establish maximum power conditions for the Zener, diode., (d) Determine the minimum value of RL to ensure that the Zener diode is in the “on” state., , Figure 2.165 Problem 42, , * 43. (a) Design the network of Fig. 2.166 to maintain VL at 12 V for a load variation (IL) from 0, to 200 mA. That is, determine Rs and VZ., (b) Determine PZmax for the Zener diode of part (a)., * 44. For the network of Fig. 2.167, determine the range of Vi that will maintain VL at 8 V and not, exceed the maximum power rating of the Zener diode., 45. Design a voltage regulator that will maintain an output voltage of 20 V across a 1-k load with, an input that will vary between 30 and 50 V. That is, determine the proper value of Rs and the, maximum current IZM., , Figure 2.166 Problem 43, , 46. Sketch the output of the network of Fig. 2.120 if the input is a 50-V square wave. Repeat for, a 5-V square wave., , § 2.12 Voltage-Multiplier Circuits, 47. Determine the voltage available from the voltage doubler of Fig. 2.121 if the secondary voltage of the transformer is 120 V (rms)., 48. Determine the required PIV ratings of the diodes of Fig. 2.121 in terms of the peak secondary, voltage Vm., , § 2.13 PSpice Windows, , Figure 2.167 Problems 44, 52, , 49. Perform an analysis of the network of Fig. 2.135 using PSpice Windows., 50. Perform an analysis of the network of Fig. 2.139 using PSpice Windows., 51. Perform an analysis of the network of Fig. 2.142 using PSpice Windows., 52. Perform a general analysis of the Zener network of Fig. 2.167 using PSpice Windows., , *, , Please Note: Asterisks indicate more difficult problems., , Problems, , 111
Page 123 :
CHAPTER, , 3, , Bipolar Junction, Transistors, 3.1 INTRODUCTION, During the period 1904–1947, the vacuum tube was undoubtedly the electronic device of interest and development. In 1904, the vacuum-tube diode was introduced by, J. A. Fleming. Shortly thereafter, in 1906, Lee De Forest added a third element, called, the control grid, to the vacuum diode, resulting in the first amplifier, the triode. In, the following years, radio and television provided great stimulation to the tube industry. Production rose from about 1 million tubes in 1922 to about 100 million in, 1937. In the early 1930s the four-element tetrode and five-element pentode gained, prominence in the electron-tube industry. In the years to follow, the industry became, one of primary importance and rapid advances were made in design, manufacturing, techniques, high-power and high-frequency applications, and miniaturization., On December 23, 1947, however, the electronics industry was to experience the, advent of a completely new direction of interest and development. It was on the afternoon of this day that Walter H. Brattain and John Bardeen demonstrated the amplifying action of the first transistor at the Bell Telephone Laboratories. The original, transistor (a point-contact transistor) is shown in Fig. 3.1. The advantages of this threeterminal solid-state device over the tube were immediately obvious: It was smaller, , Co-inventors of the first transistor, at Bell Laboratories: Dr. William, Shockley (seated); Dr. John, Bardeen (left); Dr. Walter H. Brattain. (Courtesy of AT&T, Archives.), Dr. Shockley Born: London,, England, 1910, PhD Harvard,, 1936, Dr. Bardeen Born: Madison,, Wisconsin, 1908, PhD Princeton,, 1936, Dr. Brattain Born: Amoy, China,, 1902, PhD University of, Minnesota, 1928, All shared the Nobel Prize in, 1956 for this contribution., , 112, , Figure 3.1, , The first transistor. (Courtesy Bell Telephone Laboratories.)
Page 124 :
and lightweight; had no heater requirement or heater loss; had rugged construction;, and was more efficient since less power was absorbed by the device itself; it was instantly available for use, requiring no warm-up period; and lower operating voltages, were possible. Note in the discussion above that this chapter is our first discussion of, devices with three or more terminals. You will find that all amplifiers (devices that, increase the voltage, current, or power level) will have at least three terminals with, one controlling the flow between two other terminals., , 3.2 TRANSISTOR CONSTRUCTION, The transistor is a three-layer semiconductor device consisting of either two n- and, one p-type layers of material or two p- and one n-type layers of material. The former, is called an npn transistor, while the latter is called a pnp transistor. Both are shown, in Fig. 3.2 with the proper dc biasing. We will find in Chapter 4 that the dc biasing, is necessary to establish the proper region of operation for ac amplification. The emitter layer is heavily doped, the base lightly doped, and the collector only lightly doped., The outer layers have widths much greater than the sandwiched p- or n-type material. For the transistors shown in Fig. 3.2 the ratio of the total width to that of the center layer is 0.150/0.001 1501. The doping of the sandwiched layer is also considerably less than that of the outer layers (typically, 101 or less). This lower doping, level decreases the conductivity (increases the resistance) of this material by limiting, the number of “free” carriers., For the biasing shown in Fig. 3.2 the terminals have been indicated by the capital letters E for emitter, C for collector, and B for base. An appreciation for this choice, of notation will develop when we discuss the basic operation of the transistor. The, abbreviation BJT, from bipolar junction transistor, is often applied to this threeterminal device. The term bipolar reflects the fact that holes and electrons participate, in the injection process into the oppositely polarized material. If only one carrier is, employed (electron or hole), it is considered a unipolar device. The Schottky diode, of Chapter 20 is such a device., , Figure 3.2 Types of transistors:, (a) pnp; (b) npn., , 3.3 TRANSISTOR OPERATION, The basic operation of the transistor will now be described using the pnp transistor, of Fig. 3.2a. The operation of the npn transistor is exactly the same if the roles played, by the electron and hole are interchanged. In Fig. 3.3 the pnp transistor has been redrawn without the base-to-collector bias. Note the similarities between this situation, and that of the forward-biased diode in Chapter 1. The depletion region has been reduced in width due to the applied bias, resulting in a heavy flow of majority carriers, from the p- to the n-type material., , Figure 3.3 Forward-biased, junction of a pnp transistor., , 3.3 Transistor Operation, , 113
Page 125 :
Let us now remove the base-to-emitter bias of the pnp transistor of Fig. 3.2a as, shown in Fig. 3.4. Consider the similarities between this situation and that of the, reverse-biased diode of Section 1.6. Recall that the flow of majority carriers is zero,, resulting in only a minority-carrier flow, as indicated in Fig. 3.4. In summary, therefore:, One p-n junction of a transistor is reverse biased, while the other is forward, biased., In Fig. 3.5 both biasing potentials have been applied to a pnp transistor, with the, resulting majority- and minority-carrier flow indicated. Note in Fig. 3.5 the widths of, the depletion regions, indicating clearly which junction is forward-biased and which, is reverse-biased. As indicated in Fig. 3.5, a large number of majority carriers will, diffuse across the forward-biased p-n junction into the n-type material. The question, then is whether these carriers will contribute directly to the base current IB or pass, directly into the p-type material. Since the sandwiched n-type material is very thin, and has a low conductivity, a very small number of these carriers will take this path, of high resistance to the base terminal. The magnitude of the base current is typically, on the order of microamperes as compared to milliamperes for the emitter and collector currents. The larger number of these majority carriers will diffuse across the, reverse-biased junction into the p-type material connected to the collector terminal as, indicated in Fig. 3.5. The reason for the relative ease with which the majority carriers can cross the reverse-biased junction is easily understood if we consider that for, the reverse-biased diode the injected majority carriers will appear as minority carriers in the n-type material. In other words, there has been an injection of minority carriers into the n-type base region material. Combining this with the fact that all the, minority carriers in the depletion region will cross the reverse-biased junction of a, diode accounts for the flow indicated in Fig. 3.5., , Figure 3.4 Reverse-biased junction of a pnp, transistor., , Figure 3.5 Majority and minority, carrier flow of a pnp transistor., , Applying Kirchhoff’s current law to the transistor of Fig. 3.5 as if it were a single node, we obtain, IE IC IB, , (3.1), , and find that the emitter current is the sum of the collector and base currents. The, collector current, however, is comprised of two components—the majority and minority carriers as indicated in Fig. 3.5. The minority-current component is called the, leakage current and is given the symbol ICO (IC current with emitter terminal Open)., The collector current, therefore, is determined in total by Eq. (3.2)., IC ICmajority ICOminority, 114, , Chapter 3, , Bipolar Junction Transistors, , (3.2)
Page 126 :
For general-purpose transistors, IC is measured in milliamperes, while ICO is measured in microamperes or nanoamperes. ICO, like Is for a reverse-biased diode, is temperature sensitive and must be examined carefully when applications of wide temperature ranges are considered. It can severely affect the stability of a system at high, temperature if not considered properly. Improvements in construction techniques have, resulted in significantly lower levels of ICO, to the point where its effect can often be, ignored., , 3.4 COMMON-BASE CONFIGURATION, The notation and symbols used in conjunction with the transistor in the majority of, texts and manuals published today are indicated in Fig. 3.6 for the common-base configuration with pnp and npn transistors. The common-base terminology is derived, from the fact that the base is common to both the input and output sides of the configuration. In addition, the base is usually the terminal closest to, or at, ground potential. Throughout this book all current directions will refer to conventional (hole), flow rather than electron flow. This choice was based primarily on the fact that the, vast amount of literature available at educational and industrial institutions employs, conventional flow and the arrows in all electronic symbols have a direction defined, by this convention. Recall that the arrow in the diode symbol defined the direction of, conduction for conventional current. For the transistor:, The arrow in the graphic symbol defines the direction of emitter current (conventional flow) through the device., All the current directions appearing in Fig. 3.6 are the actual directions as defined, by the choice of conventional flow. Note in each case that IE IC IB. Note also, that the applied biasing (voltage sources) are such as to establish current in the direction indicated for each branch. That is, compare the direction of IE to the polarity, or VEE for each configuration and the direction of IC to the polarity of VCC., To fully describe the behavior of a three-terminal device such as the commonbase amplifiers of Fig. 3.6 requires two sets of characteristics—one for the driving, point or input parameters and the other for the output side. The input set for the, common-base amplifier as shown in Fig. 3.7 will relate an input current (IE) to an input voltage (VBE) for various levels of output voltage (VCB)., The output set will relate an output current (IC) to an output voltage (VCB) for various levels of input current (IE) as shown in Fig. 3.8. The output or collector set of, characteristics has three basic regions of interest, as indicated in Fig. 3.8: the active,, , Figure 3.6 Notation and symbols used with the common-base, configuration: (a) pnp transistor;, (b) npn transistor., , Figure 3.7 Input or driving, point characteristics for a, common-base silicon transistor, amplifier., , 3.4 Common-Base Configuration, , 115
Page 127 :
IC (mA), , Active region (unshaded area), 7 mA, , 7, , 6 mA, , 6, , 4, 3, 2, , 5 mA, , Saturation region, , 5, , 4 mA, 3 mA, 2 mA, I E = 1 mA, , 1, , Figure 3.8 Output or collector, characteristics for a common-base, transistor amplifier., , I E = 0 mA, , 0, −1, , 0, , 5, , 10, , 15, , 20, , V CB (V), , Cutoff region, , cutoff, and saturation regions. The active region is the region normally employed for, linear (undistorted) amplifiers. In particular:, In the active region the collector-base junction is reverse-biased, while the, base-emitter junction is forward-biased., , Figure 3.9 Reverse saturation, current., , The active region is defined by the biasing arrangements of Fig. 3.6. At the lower, end of the active region the emitter current (IE) is zero, the collector current is simply that due to the reverse saturation current ICO, as indicated in Fig. 3.8. The current, ICO is so small (microamperes) in magnitude compared to the vertical scale of IC (milliamperes) that it appears on virtually the same horizontal line as IC 0. The circuit, conditions that exist when IE 0 for the common-base configuration are shown in, Fig. 3.9. The notation most frequently used for ICO on data and specification sheets, is, as indicated in Fig. 3.9, ICBO. Because of improved construction techniques, the, level of ICBO for general-purpose transistors (especially silicon) in the low- and midpower ranges is usually so low that its effect can be ignored. However, for higher, power units ICBO will still appear in the microampere range. In addition, keep in mind, that ICBO, like Is, for the diode (both reverse leakage currents) is temperature sensitive. At higher temperatures the effect of ICBO may become an important factor since, it increases so rapidly with temperature., Note in Fig. 3.8 that as the emitter current increases above zero, the collector current increases to a magnitude essentially equal to that of the emitter current as determined by the basic transistor-current relations. Note also the almost negligible effect, of VCB on the collector current for the active region. The curves clearly indicate that, a first approximation to the relationship between IE and IC in the active region is given, by, IC IE, , (3.3), , As inferred by its name, the cutoff region is defined as that region where the collector current is 0 A, as revealed on Fig. 3.8. In addition:, In the cutoff region the collector-base and base-emitter junctions of a transistor are both reverse-biased., 116, , Chapter 3, , Bipolar Junction Transistors
Page 128 :
The saturation region is defined as that region of the characteristics to the left of, VCB 0 V. The horizontal scale in this region was expanded to clearly show the dramatic change in characteristics in this region. Note the exponential increase in collector current as the voltage VCB increases toward 0 V., In the saturation region the collector-base and base-emitter junctions are, forward-biased., The input characteristics of Fig. 3.7 reveal that for fixed values of collector voltage (VCB), as the base-to-emitter voltage increases, the emitter current increases in a, manner that closely resembles the diode characteristics. In fact, increasing levels of, VCB have such a small effect on the characteristics that as a first approximation the, change due to changes in VCB can be ignored and the characteristics drawn as shown, in Fig. 3.10a. If we then apply the piecewise-linear approach, the characteristics of, Fig. 3.10b will result. Taking it a step further and ignoring the slope of the curve and, therefore the resistance associated with the forward-biased junction will result in the, characteristics of Fig. 3.10c. For the analysis to follow in this book the equivalent, model of Fig. 3.10c will be employed for all dc analysis of transistor networks. That, is, once a transistor is in the “on” state, the base-to-emitter voltage will be assumed, to be the following:, VBE 0.7 V, , (3.4), , In other words, the effect of variations due to VCB and the slope of the input characteristics will be ignored as we strive to analyze transistor networks in a manner that, will provide a good approximation to the actual response without getting too involved, with parameter variations of less importance., I E (mA), , I E (mA), , I E (mA), , 8, , 8, , 7, , 7, , 6, , 6, , 6, , 5, , 5, , 5, , 4, , 4, , 4, , 3, , 3, , 3, , 2, , 2, , 2, , 1, , 1, , 8, 7, Any V CB, , 0, , 0.2, , 0.4, , 0.6 0.8, (a), , 1, , VBE (V), , 0, , 1, , 0.7 V, 0.2, , 0.4, , 0.6 0.8, , 1, , VBE (V), , 0, , (b), , 0.7 V, 0.2, , 0.4, , 0.6 0.8, , 1, , VBE (V), , (c), , Figure 3.10 Developing the equivalent model to be employed for the base-toemitter region of an amplifier in the dc mode., , It is important to fully appreciate the statement made by the characteristics of Fig., 3.10c. They specify that with the transistor in the “on” or active state the voltage from, base to emitter will be 0.7 V at any level of emitter current as controlled by the external network. In fact, at the first encounter of any transistor configuration in the dc, mode, one can now immediately specify that the voltage from base to emitter is 0.7 V, if the device is in the active region—a very important conclusion for the dc analysis, to follow., 3.4 Common-Base Configuration, , 117
Page 129 :
EXAMPLE 3.1, , (a) Using the characteristics of Fig. 3.8, determine the resulting collector current if, IE 3 mA and VCB 10 V., (b) Using the characteristics of Fig. 3.8, determine the resulting collector current if, IE remains at 3 mA but VCB is reduced to 2 V., (c) Using the characteristics of Figs. 3.7 and 3.8, determine VBE if IC 4 mA and, VCB 20 V., (d) Repeat part (c) using the characteristics of Figs. 3.8 and 3.10c., , Solution, (a) The characteristics clearly indicate that IC IE 3 mA., (b) The effect of changing VCB is negligible and IC continues to be 3 mA., (c) From Fig. 3.8, IE IC 4 mA. On Fig. 3.7 the resulting level of VBE is about, 0.74 V., (d) Again from Fig. 3.8, IE IC 4 mA. However, on Fig. 3.10c, VBE is 0.7 V for, any level of emitter current., , Alpha (), In the dc mode the levels of IC and IE due to the majority carriers are related by a, quantity called alpha and defined by the following equation:, I, dc C, IE, , (3.5), , where IC and IE are the levels of current at the point of operation. Even though the, characteristics of Fig. 3.8 would suggest that 1, for practical devices the level of, alpha typically extends from 0.90 to 0.998, with most approaching the high end of, the range. Since alpha is defined solely for the majority carriers, Eq. (3.2) becomes, IC IE ICBO, , (3.6), , For the characteristics of Fig. 3.8 when IE 0 mA, IC is therefore equal to ICBO,, but as mentioned earlier, the level of ICBO is usually so small that it is virtually undetectable on the graph of Fig. 3.8. In other words, when IE 0 mA on Fig. 3.8, IC, also appears to be 0 mA for the range of VCB values., For ac situations where the point of operation moves on the characteristic curve,, an ac alpha is defined by, IC, ac , IE, , , , VCB constant, , (3.7), , The ac alpha is formally called the common-base, short-circuit, amplification factor,, for reasons that will be more obvious when we examine transistor equivalent circuits, in Chapter 7. For the moment, recognize that Eq. (3.7) specifies that a relatively small, change in collector current is divided by the corresponding change in IE with the, collector-to-base voltage held constant. For most situations the magnitudes of ac and, dc are quite close, permitting the use of the magnitude of one for the other. The use, of an equation such as (3.7) will be demonstrated in Section 3.6., , Biasing, The proper biasing of the common-base configuration in the active region can be determined quickly using the approximation IC IE and assuming for the moment that, 118, , Chapter 3, , Bipolar Junction Transistors
Page 130 :
Figure 3.11 Establishing the, proper biasing management for a, common-base pnp transistor in, the active region., , IB 0 A. The result is the configuration of Fig. 3.11 for the pnp transistor. The arrow of the symbol defines the direction of conventional flow for IE IC. The dc supplies are then inserted with a polarity that will support the resulting current direction., For the npn transistor the polarities will be reversed., Some students feel that they can remember whether the arrow of the device symbol in pointing in or out by matching the letters of the transistor type with the appropriate letters of the phrases “pointing in” or “not pointing in.” For instance, there, is a match between the letters npn and the italic letters of not pointing in and the letters pnp with pointing in., , 3.5 TRANSISTOR AMPLIFYING ACTION, Now that the relationship between IC and IE has been established in Section 3.4, the, basic amplifying action of the transistor can be introduced on a surface level using, the network of Fig. 3.12. The dc biasing does not appear in the figure since our interest will be limited to the ac response. For the common-base configuration the ac, input resistance determined by the characteristics of Fig. 3.7 is quite small and typically varies from 10 to 100 . The output resistance as determined by the curves of, Fig. 3.8 is quite high (the more horizontal the curves the higher the resistance) and, typically varies from 50 k to 1 M (100 k for the transistor of Fig. 3.12). The difference in resistance is due to the forward-biased junction at the input (base to emitter) and the reverse-biased junction at the output (base to collector). Using a common, value of 20 for the input resistance, we find that, V, 200 mV, Ii i 10 mA, Ri, 20 , If we assume for the moment that ac 1 (Ic Ie),, IL Ii 10 mA, VL ILR, , and, , (10 mA)(5 k), 50 V, pnp, , Ii, , E, , +, V i = 200 mV, , C, , IL, , +, , B, Ri, , Ro, , 20 Ω, , 100 k Ω, , R, , 5 k Ω VL, , –, , –, , Figure 3.12 Basic voltage amplification action of the common-base, configuration., , 3.5 Transistor Amplifying Action, , 119
Page 131 :
The voltage amplification is, 50 V, VL, Av , 250, 200 mV, Vi, Typical values of voltage amplification for the common-base configuration vary, from 50 to 300. The current amplification (IC/IE) is always less than 1 for the common-base configuration. This latter characteristic should be obvious since IC IE, and is always less than 1., The basic amplifying action was produced by transferring a current I from a lowto a high-resistance circuit. The combination of the two terms in italics results in the, label transistor; that is,, transfer resistor → transistor, , 3.6 COMMON-EMITTER CONFIGURATION, The most frequently encountered transistor configuration appears in Fig. 3.13 for the, pnp and npn transistors. It is called the common-emitter configuration since the emitter is common or reference to both the input and output terminals (in this case common to both the base and collector terminals). Two sets of characteristics are again, necessary to describe fully the behavior of the common-emitter configuration: one for, the input or base-emitter circuit and one for the output or collector-emitter circuit., Both are shown in Fig. 3.14., , Figure 3.13 Notation and symbols used with the common-emitter configuration: (a) npn transistor; (b) pnp transistor., , The emitter, collector, and base currents are shown in their actual conventional, current direction. Even though the transistor configuration has changed, the current, relations developed earlier for the common-base configuration are still applicable., That is, IE IC IB and IC IE., For the common-emitter configuration the output characteristics are a plot of the, output current (IC) versus output voltage (VCE) for a range of values of input current, (IB). The input characteristics are a plot of the input current (IB) versus the input voltage (VBE) for a range of values of output voltage (VCE)., 120, , Chapter 3, , Bipolar Junction Transistors
Page 132 :
IC (mA), 8, 90 µA, 80 µA, , 7, , 70 µA, 6, , I B (µA), 50 µA, , (Saturation region) 5, , 40 µA, , 90, , VCE = 20 V, , 80, , 4, , 70, , 30 µA, , 60, , 3, , (Active region), , 50, , 20 µA, , 40, , 2, , 30, , 10 µA, , 20, , 1, I B = 0 µA, 0, , 100, , VCE = 1 V, VCE = 10 V, , 60 µA, , VCEsat, , 10, , 5, , 15, , 20 VCE (V), , 10, 0, , 0.2, , 0.4, , 0.6, , 0.8, , 1.0, , VBE (V), , (Cutoff region), , ~ β I CBO, I CEO =, (a), , (b), , Figure 3.14 Characteristics of a silicon transistor in the common-emitter configuration: (a) collector characteristics; (b) base characteristics., , Note that on the characteristics of Fig. 3.14 the magnitude of IB is in microamperes, compared to milliamperes of IC. Consider also that the curves of IB are not as, horizontal as those obtained for IE in the common-base configuration, indicating that, the collector-to-emitter voltage will influence the magnitude of the collector current., The active region for the common-emitter configuration is that portion of the, upper-right quadrant that has the greatest linearity, that is, that region in which the, curves for IB are nearly straight and equally spaced. In Fig. 3.14a this region exists, to the right of the vertical dashed line at VCEsat and above the curve for IB equal to, zero. The region to the left of VCEsat is called the saturation region., In the active region of a common-emitter amplifier the collector-base junction, is reverse-biased, while the base-emitter junction is forward-biased., You will recall that these were the same conditions that existed in the active region of the common-base configuration. The active region of the common-emitter, configuration can be employed for voltage, current, or power amplification., The cutoff region for the common-emitter configuration is not as well defined as, for the common-base configuration. Note on the collector characteristics of Fig. 3.14, that IC is not equal to zero when IB is zero. For the common-base configuration, when, the input current IE was equal to zero, the collector current was equal only to the reverse saturation current ICO, so that the curve IE 0 and the voltage axis were, for, all practical purposes, one., The reason for this difference in collector characteristics can be derived through, the proper manipulation of Eqs. (3.3) and (3.6). That is,, Eq. (3.6):, Substitution gives, Rearranging yields, , Eq. (3.3):, , IC IE ICBO, , IC (IC IB) ICBO, , IB, ICBO, IC , , , 1 , 1 , , (3.8), , 3.6 Common-Emitter Configuration, , 121
Page 133 :
If we consider the case discussed above, where IB 0 A, and substitute a typical, value of such as 0.996, the resulting collector current is the following:, , (0 A), ICBO, IC , , 1 , 1 0.996, ICBO, , 250ICBO, 0.004, If ICBO were 1 A, the resulting collector current with IB 0 A would be, 250(1 A) 0.25 mA, as reflected in the characteristics of Fig. 3.14., For future reference, the collector current defined by the condition IB 0 A will, be assigned the notation indicated by Eq. (3.9)., ICBO, , ICEO , 1 , , , , IB 0 A, , (3.9), , In Fig. 3.15 the conditions surrounding this newly defined current are demonstrated, with its assigned reference direction., For linear (least distortion) amplification purposes, cutoff for the commonemitter configuration will be defined by IC ICEO., In other words, the region below IB 0 A is to be avoided if an undistorted output signal is required., When employed as a switch in the logic circuitry of a computer, a transistor will, have two points of operation of interest: one in the cutoff and one in the saturation, region. The cutoff condition should ideally be IC 0 mA for the chosen VCE voltage., Since ICEO is typically low in magnitude for silicon materials, cutoff will exist for, switching purposes when IB 0 A or IC ICEO for silicon transistors only. For germanium transistors, however, cutoff for switching purposes will be defined as those, conditions that exist when IC ICBO. This condition can normally be obtained for, germanium transistors by reverse-biasing the base-to-emitter junction a few tenths of, a volt., Recall for the common-base configuration that the input set of characteristics was, approximated by a straight-line equivalent that resulted in VBE 0.7 V for any level, of IE greater than 0 mA. For the common-emitter configuration the same approach, can be taken, resulting in the approximate equivalent of Fig. 3.16. The result supports, our earlier conclusion that for a transistor in the “on” or active region the base-toemitter voltage is 0.7 V. In this case the voltage is fixed for any level of base current., I B (µA), , 100, 90, 80, 70, 60, 50, 40, 30, 20, 10, 0, , Figure 3.15 Circuit conditions, related to ICEO., , 122, , 0.2, , 0.4, , 0.6, , 0.8, , 0.7 V, , Chapter 3, , Bipolar Junction Transistors, , 1, , V BE (V), , Figure 3.16 Piecewise-linear, equivalent for the diode characteristics of Fig. 3.14b.
Page 134 :
(a) Using the characteristics of Fig. 3.14, determine IC at IB 30 A and VCE , 10 V., (b) Using the characteristics of Fig. 3.14, determine IC at VBE 0.7 V and VCE , 15 V., , EXAMPLE 3.2, , Solution, (a) At the intersection of IB 30 A and VCE 10 V, IC 3.4 mA., (b) Using Fig. 3.14b, IB 20 A at VBE 0.7 V. From Fig. 3.14a we find that IC , 2.5 mA at the intersection of IB 20 A and VCE 15 V., , Beta ( ), In the dc mode the levels of IC and IB are related by a quantity called beta and defined by the following equation:, I, C, IB, , dc, , (3.10), , where IC and IB are determined at a particular operating point on the characteristics., For practical devices the level of typically ranges from about 50 to over 400, with, most in the midrange. As for , certainly reveals the relative magnitude of one current to the other. For a device with a of 200, the collector current is 200 times the, magnitude of the base current., On specification sheets dc is usually included as hFE with the h derived from an, ac hybrid equivalent circuit to be introduced in Chapter 7. The subscripts FE are derived from forward-current amplification and common-emitter configuration, respectively., For ac situations an ac beta has been defined as follows:, ac, , IC, , IB, , , , VCE constant, , (3.11), , The formal name for ac is common-emitter, forward-current, amplification factor., Since the collector current is usually the output current for a common-emitter configuration and the base current the input current, the term amplification is included, in the nomenclature above., Equation (3.11) is similar in format to the equation for ac in Section 3.4. The, procedure for obtaining ac from the characteristic curves was not described because, of the difficulty of actually measuring changes of IC and IE on the characteristics., Equation (3.11), however, is one that can be described with some clarity, and in fact,, the result can be used to find ac using an equation to be derived shortly., On specification sheets ac is normally referred to as hfe. Note that the only difference between the notation used for the dc beta, specifically, dc hFE, is the type, of lettering for each subscript quantity. The lowercase letter h continues to refer to, the hybrid equivalent circuit to be described in Chapter 7 and the fe to the forward, current gain in the common-emitter configuration., The use of Eq. (3.11) is best described by a numerical example using an actual, set of characteristics such as appearing in Fig. 3.14a and repeated in Fig. 3.17. Let, us determine ac for a region of the characteristics defined by an operating point of, IB 25 A and VCE 7.5 V as indicated on Fig. 3.17. The restriction of VCE constant requires that a vertical line be drawn through the operating point at VCE 7.5 V., At any location on this vertical line the voltage VCE is 7.5 V, a constant. The change, 3.6 Common-Emitter Configuration, , 123
Page 135 :
I C (mA), 9, , 90 µA, , 8, , 80 µA, 7, , 70 µA, 60 µA, , 6, , 50 µA, 5, 40 µA, 4, IC2, ∆ IC, IC1, , 30 µA, , IB 2, 3, , 25 µA, 20 µA, , Q - pt., IB1, , 2, , 10 µA, 1, IB = 0 µA, 0, , 5, , 10, , 15, , 20, , VCE = 7.5 V, , Figure 3.17 Determining, , ac, , and, , dc, , 25, , VCE (V), , from the collector characteristics., , in IB (IB) as appearing in Eq. (3.11) is then defined by choosing two points on either side of the Q-point along the vertical axis of about equal distances to either side, of the Q-point. For this situation the IB 20 A and 30 A curves meet the requirement without extending too far from the Q-point. They also define levels of IB, that are easily defined rather than have to interpolate the level of IB between the curves., It should be mentioned that the best determination is usually made by keeping the, chosen IB as small as possible. At the two intersections of IB and the vertical axis,, the two levels of IC can be determined by drawing a horizontal line over to the vertical axis and reading the resulting values of IC. The resulting ac for the region can, then be determined by, IC2 IC1, IC, , ac , IB VCE constant, IB2 IB1, , , , 1 mA, 3.2 mA 2.2 mA, , 10 A, 30 A 20 A, 100, The solution above reveals that for an ac input at the base, the collector current will, be about 100 times the magnitude of the base current., If we determine the dc beta at the Q-point:, dc, , 124, , Chapter 3, , I, 2.7 mA, C 108, IB, 25 A, , Bipolar Junction Transistors
Page 136 :
Although not exactly equal, the levels of ac and dc are usually reasonably close, and are often used interchangeably. That is, if ac is known, it is assumed to be about, the same magnitude as dc, and vice versa. Keep in mind that in the same lot, the, value of ac will vary somewhat from one transistor to the next even though each, transistor has the same number code. The variation may not be significant but for the, majority of applications, it is certainly sufficient to validate the approximate approach, above. Generally, the smaller the level of ICEO, the closer the magnitude of the two, betas. Since the trend is toward lower and lower levels of ICEO, the validity of the, foregoing approximation is further substantiated., If the characteristics had the appearance of those appearing in Fig. 3.18, the level, of ac would be the same in every region of the characteristics. Note that the step in, IB is fixed at 10 A and the vertical spacing between curves is the same at every point, in the characteristics—namely, 2 mA. Calculating the ac at the Q-point indicated will, result in, ac, , IC, , IB, , , , VCE constant, , 9 mA 7 mA, 2 mA, 200, 45 A 35 A, 10 A, , Determining the dc beta at the same Q-point will result in, dc, , 8 mA, I, C 200, 40 A, IB, , revealing that if the characteristics have the appearance of Fig. 3.18, the magnitude, of ac and dc will be the same at every point on the characteristics. In particular, note, that ICEO 0 A., Although a true set of transistor characteristics will never have the exact appearance of Fig. 3.18, it does provide a set of characteristics for comparison with those, obtained from a curve tracer (to be described shortly)., , Figure 3.18 Characteristics in which, , ac, , is the same everywhere and, , ac, , , , dc., , For the analysis to follow the subscript dc or ac will not be included with to, avoid cluttering the expressions with unnecessary labels. For dc situations it will simply be recognized as dc and for any ac analysis as ac. If a value of is specified, for a particular transistor configuration, it will normally be used for both the dc and, ac calculations., 3.6 Common-Emitter Configuration, , 125
Page 137 :
A relationship can be developed between and using the basic relationships, introduced thus far. Using IC/IB we have IB IC/ , and from IC/IE we have, IE IC/. Substituting into, IE IC IB, I, I, C IC C, , , we have, , and dividing both sides of the equation by IC will result in, 1, 1, 1 , , ( 1), , or, so that, , , 1, , (3.12a), , , , 1 , , (3.12b), , or, In addition, recall that, , ICBO, ICEO , , 1 , but using an equivalence of, 1, , 1 , , 1, , derived from the above, we find that, ICEO ( 1)ICBO, or, , ICEO ICBO, , (3.13), , as indicated on Fig. 3.14a. Beta is a particularly important parameter because it, provides a direct link between current levels of the input and output circuits for a, common-emitter configuration. That is,, IC IB, and since, , (31.4), , IE IC IB, IB IB, , we have, , IE ( 1)IB, , (3.15), , Both of the equations above play a major role in the analysis in Chapter 4., , Biasing, The proper biasing of a common-emitter amplifier can be determined in a manner, similar to that introduced for the common-base configuration. Let us assume that we, are presented with an npn transistor such as shown in Fig. 3.19a and asked to apply, the proper biasing to place the device in the active region., The first step is to indicate the direction of IE as established by the arrow in the, transistor symbol as shown in Fig. 3.19b. Next, the other currents are introduced as, 126, , Chapter 3, , Bipolar Junction Transistors
Page 138 :
Figure 3.19 Determining the proper biasing arrangement for a commonemitter npn transistor configuration., , shown, keeping in mind the Kirchhoff’s current law relationship: IC IB IE. Finally, the supplies are introduced with polarities that will support the resulting directions of IB and IC as shown in Fig. 3.19c to complete the picture. The same approach, can be applied to pnp transistors. If the transistor of Fig. 3.19 was a pnp transistor,, all the currents and polarities of Fig. 3.19c would be reversed., , 3.7 COMMON-COLLECTOR, CONFIGURATION, The third and final transistor configuration is the common-collector configuration,, shown in Fig. 3.20 with the proper current directions and voltage notation. The, common-collector configuration is used primarily for impedance-matching purposes, since it has a high input impedance and low output impedance, opposite to that of the, common-base and common-emitter configurations., , IE, , IE, , E, , p, , IB, , V EE, , p, , p, , B, , V EE, , n, , V BB, , V BB, C, , n, , IB, , n, , B, , E, , C, , IC, , IC, , IE, , IE, E, , E, IB, , IB, B, , B, IC, , IC, C, , C, , (a), , (b), , 3.7 Common-Collector Configuration, , Figure 3.20 Notation and symbols used with the common-collector configuration: (a) pnp transistor; (b) npn transistor., , 127
Page 139 :
C, B, E, R, , Figure 3.21 Common-collector, configuration used for, impedance-matching purposes., , A common-collector circuit configuration is provided in Fig. 3.21 with the load, resistor connected from emitter to ground. Note that the collector is tied to ground, even though the transistor is connected in a manner similar to the common-emitter, configuration. From a design viewpoint, there is no need for a set of commoncollector characteristics to choose the parameters of the circuit of Fig. 3.21. It can, be designed using the common-emitter characteristics of Section 3.6. For all practical purposes, the output characteristics of the common-collector configuration are the, same as for the common-emitter configuration. For the common-collector configuration the output characteristics are a plot of IE versus VEC for a range of values of IB., The input current, therefore, is the same for both the common-emitter and commoncollector characteristics. The horizontal voltage axis for the common-collector configuration is obtained by simply changing the sign of the collector-to-emitter voltage, of the common-emitter characteristics. Finally, there is an almost unnoticeable change, in the vertical scale of IC of the common-emitter characteristics if IC is replaced by, IE for the common-collector characteristics (since 1). For the input circuit of the, common-collector configuration the common-emitter base characteristics are sufficient for obtaining the required information., , 3.8 LIMITS OF OPERATION, For each transistor there is a region of operation on the characteristics which will ensure that the maximum ratings are not being exceeded and the output signal exhibits, minimum distortion. Such a region has been defined for the transistor characteristics, of Fig. 3.22. All of the limits of operation are defined on a typical transistor specification sheet described in Section 3.9., Some of the limits of operation are self-explanatory, such as maximum collector, current (normally referred to on the specification sheet as continuous collector current) and maximum collector-to-emitter voltage (often abbreviated as VCEO or V(BR)CEO, on the specification sheet). For the transistor of Fig. 3.22, ICmax was specified as 50 mA, and VCEO as 20 V. The vertical line on the characteristics defined as VCEsat specifies, , Figure 3.22 Defining the linear, (undistorted) region of operation, for a transistor., , 128, , Chapter 3, , Bipolar Junction Transistors
Page 140 :
the minimum VCE that can be applied without falling into the nonlinear region labeled, the saturation region. The level of VCEsat is typically in the neighborhood of the 0.3 V, specified for this transistor., The maximum dissipation level is defined by the following equation:, PCmax VCEIC, , (3.16), , For the device of Fig. 3.22, the collector power dissipation was specified as, 300 mW. The question then arises of how to plot the collector power dissipation curve, specified by the fact that, PCmax VCEIC 300 mW, or, , VCEIC 300 mW, , At any point on the characteristics the product of VCE and IC must be equal to, 300 mW. If we choose IC to be the maximum value of 50 mA and substitute into the, relationship above, we obtain, VCEIC 300 mW, VCE (50 mA) 300 mW, 300 mW, VCE 6 V, 50 mA, As a result we find that if IC 50 mA, then VCE 6 V on the power dissipation, curve as indicated in Fig. 3.22. If we now choose VCE to be its maximum value of, 20 V, the level of IC is the following:, (20 V)IC 300 mW, 300 mW, IC 15 mA, 20 V, defining a second point on the power curve., If we now choose a level of IC in the midrange such as 25 mA, and solve for the, resulting level of VCE, we obtain, VCE(25 mA) 300 mW, and, , 300 mW, VCE 12 V, 25 mA, , as also indicated on Fig. 3.22., A rough estimate of the actual curve can usually be drawn using the three points, defined above. Of course, the more points you have, the more accurate the curve, but, a rough estimate is normally all that is required., The cutoff region is defined as that region below IC ICEO. This region must also, be avoided if the output signal is to have minimum distortion. On some specification, sheets only ICBO is provided. One must then use the equation ICEO ICBO to establish some idea of the cutoff level if the characteristic curves are unavailable. Operation in the resulting region of Fig. 3.22 will ensure minimum distortion of the output signal and current and voltage levels that will not damage the device., If the characteristic curves are unavailable or do not appear on the specification, sheet (as is often the case), one must simply be sure that IC, VCE, and their product, VCEIC fall into the range appearing in Eq. (3.17)., 3.8 Limits of Operation, , 129
Page 141 :
ICEO, VCEsat, , IC, VCE, , VCEIC, , ICmax, VCEmax, , (3.17), , PCmax, , For the common-base characteristics the maximum power curve is defined by the following product of output quantities:, PCmax VCBIC, , (3.18), , 3.9 TRANSISTOR SPECIFICATION SHEET, Since the specification sheet is the communication link between the manufacturer and, user, it is particularly important that the information provided be recognized and correctly understood. Although all the parameters have not been introduced, a broad number will now be familiar. The remaining parameters will be introduced in the chapters that follow. Reference will then be made to this specification sheet to review the, manner in which the parameter is presented., The information provided as Fig. 3.23 is taken directly from the Small-Signal, Transistors, FETs, and Diodes publication prepared by Motorola Inc. The 2N4123 is, a general-purpose npn transistor with the casing and terminal identification appearing in the top-right corner of Fig. 3.23a. Most specification sheets are broken down, into maximum ratings, thermal characteristics, and electrical characteristics. The, electrical characteristics are further broken down into “on,” “off,” and small-signal, characteristics. The “on” and “off” characteristics refer to dc limits, while the smallsignal characteristics include the parameters of importance to ac operation., Note in the maximum rating list that VCEmax VCEO 30 V with ICmax 200 mA., The maximum collector dissipation PCmax PD 625 mW. The derating factor under the maximum rating specifies that the maximum rating must be decreased 5 mW, for every 1° rise in temperature above 25°C. In the “off” characteristics ICBO is specified as 50 nA and in the “on” characteristics VCEsat 0.3 V. The level of hFE has a, range of 50 to 150 at IC 2 mA and VCE 1 V and a minimum value of 25 at a, higher current of 50 mA at the same voltage., The limits of operation have now been defined for the device and are repeated below in the format of Eq. (3.17) using hFE 150 (the upper limit) and ICEO ICBO , (150)(50 nA) 7.5 A. Certainly, for many applications the 7.5 A 0.0075 mA, can be considered to be 0 mA on an approximate basis., Limits of Operation, 7.5 mA IC 200 mA, 0.3 V, , VCE, VCEIC, , 30 V, 650 mW, , In the small-signal characteristics the level of hfe ( ac) is provided along with a, plot of how it varies with collector current in Fig. 3.23f. In Fig. 3.23j the effect of, temperature and collector current on the level of hFE ( ac) is demonstrated. At room, temperature (25°C), note that hFE ( dc) is a maximum value of 1 in the neighborhood, of about 8 mA. As IC increased beyond this level, hFE drops off to one-half the value, with IC equal to 50 mA. It also drops to this level if IC decreases to the low level of, 0.15 mA. Since this is a normalized curve, if we have a transistor with dc hFE , 50 at room temperature, the maximum value at 8 mA is 50. At IC 50 mA it has, dropped to 50/2 25. In other words, normalizing reveals that the actual level of hFE, 130, , Chapter 3, , Bipolar Junction Transistors
Page 142 :
at any level of IC has been divided by the maximum value of hFE at that temperature, and IC 8 mA. Note also that the horizontal scale of Fig. 3.23j is a log scale. Log, scales are examined in depth in Chapter 11. You may want to look back at the plots, of this section when you find time to review the first few sections of Chapter 11., , Figure 3.23 Transistor specification sheet., , 3.9 Transistor Specification Sheet, , 131
Page 143 :
Before leaving this description of the characteristics, take note of the fact that the, actual collector characteristics are not provided. In fact, most specification sheets as, provided by the range of manufacturers fail to provide the full characteristics. It is, expected that the data provided are sufficient to use the device effectively in the design process., As noted in the introduction to this section, all the parameters of the specification, sheet have not been defined in the preceding sections or chapters. However, the specification sheet provided in Fig. 3.23 will be referenced continually in the chapters to, follow as parameters are introduced. The specification sheet can be a very valuable, tool in the design or analysis mode, and every effort should be made to be aware of, the importance of each parameter and how it may vary with changing levels of current, temperature, and so on., Figure 1 – Capacitance, , Figure 2 – Switching Times, , 10, , 200, ts, 100, , 5.0, , 70, 50, , C ibo, Time (ns), , Capacitance (pF), , 7.0, , 3.0, , 20, , Cobo, , 2.0, , 10.0, 7.0, 1.0, 0.1, , 0.2 0.3 0.5 0.7 1.0, 2.0 3.0 5.0 7.0 10, Reverse bias voltage (V), , 20 30 40, , td, tr, , 30, , tf, VCC = 3 V, IC / IB = 10, VEB (off) = 0.5 V, , 5.0, 1.0, , 2.0 3.0, , 5.0, 10, 20 30 50, I C , Collector current (mA), , (b), , 100, , 200, , (c), , AUDIO SMALL SIGNAL CHARACTERISTICS, NOISE FIGURE, (VCE = 5 Vdc, TA = 25°C), Bandwidth = 1.0 Hz, Figure 3 – Frequency Variations, , Figure 4 – Source Resistance, , 12, , 14, f = 1 kHz, Source resistance = 200 Ω, IC = 1 mA, Source resistance = 200 Ω, IC = 0.5 mA, , 8, , MF, Noise figure (dB), , MF, Noise figure (dB), , 10, , 12, , Source resistance = 1 k Ω, IC = 50 µ A, , 6, 4, 2, 0, 0.1, , 0.4, , 1, , 8, , IC = 50 µ A, , 6, 4, , 2, 4, 10, f, Frequency (kHz), , 20, , 40, , 100, , 0, 0.1, , (d), , IC = 100 µ A, , 0.2, , 0.4, , 1.0 2.0 4.0, 10 20, R S , Source Resistance (kΩ ), (e), , Figure 3.23 Continued., , 132, , IC = 0.5 mA, , 2, , Source resistance = 500 Ω, IC = 100 µ A, 0.2, , IC = 1 mA, , 10, , Chapter 3, , Bipolar Junction Transistors, , 40, , 100
Page 144 :
h PARAMETERS, VCE = 10 V, f = 1 kHz, TA = 25°C, Figure 5 – Current Gain, , Figure 6 – Output Admittance, 100, , h oe Output admittance (µ mhos), , 300, , h fe Current gain, , 200, , 100, 70, 50, 30, 0.1, , 0.2, , 0.5, 1.0, 2.0, I C , Collector current (mA), , 5.0, , 50, 20, 10, 5.0, 2.0, 1.0, 0.1, , 10, , 0.2, , 0.5, 1.0, 2.0, I C , Collector current (mA), , (f), , 10, , (g), , Figure 7 – Input Impedance, , Figure 8 – Voltage Feedback Ratio, 10, , h re Voltage feedback ratio (× 10−4 ), , 20, , h ie Input impedance (kΩ), , 5.0, , 10, 5.0, 2.0, 1.0, 0.5, 0.2, 0.1, , 0.2, , 0.5, 1.0, 2.0, I C , Collector current (mA), , 5.0, , (h), , 10, , 7.0, 5.0, 3.0, 2.0, , 1.0, 0.7, 0.5, 0.1, , 0.2, , 0.5, 1.0, 2.0, I C , Collector current (mA), , 10, , (i), , STATIC CHARACTERISTICS, , (h), , 5.0, , (i), , STATIC CHARACTERISTICS, Figure 9 – DC Current Gain, , h FE DC Current gain (normalized), , 2.0, , VCE = 1 V, , TJ = +125° C, +25° C, , 1.0, 0.7, , –55°C, , 0.5, 0.3, 0.2, 0.1, 0.1, , 0.2 0.3, , 0.5 0.7 1.0, , 2.0 3.0, 5.0 7.0 10, I C , Collector current (mA), , 20, , 30, , 50, , 70 100, , 200, , (j), , Figure 3.23 Continued., , 3.9 Transistor Specification Sheet, , 133
Page 145 :
3.10 TRANSISTOR TESTING, As with diodes, there are three routes one can take to check a transistor: curve tracer,, digital meter, and ohmmeter., , Curve Tracer, The curve tracer of Fig. 1.45 will provide the display of Fig. 3.24 once all the controls have been properly set. The smaller displays to the right reveal the scaling to be, applied to the characteristics. The vertical sensitivity is 2 mA/div, resulting in the scale, shown to the left of the monitor’s display. The horizontal sensitivity is 1 V/div, resulting in the scale shown below the characteristics. The step function reveals that the, curves are separated by a difference of 10 A, starting at 0 A for the bottom curve., The last scale factor provided can be used to quickly determine the ac for any region of the characteristics. Simply multiply the displayed factor by the number of divisions between IB curves in the region of interest. For instance, let us determine ac, at a Q-point of IC 7 mA and VCE 5 V. In this region of the display, the distance, between IB curves is 190 of a division, as indicated on Fig. 3.25. Using the factor specified, we find that, ac, , , , 9, 200, div 180, 10, div, , 20 mA, Vertical, per div, 2 mA, , 18 mA, 80 µ A, 16 mA, 70 µA, 14 mA, , Horizontal, per div, 1V, , 60 µA, 12 mA, 50 µA, 10 mA, 40 µA, , Per Step, 10 µ A, , 8 mA, 30 µA, 6 mA, 20 µA, 4 mA, , B or gm, per div, 200, , 10 µA, 2 mA, , Figure 3.24 Curve tracer, response to 2N3904 npn, transistor., , 0 µA, , 0 mA, 0V, , 1V, , 2V, , 3V, , 4V, , 5V, , 6V, , 7V, , 8V, , IC = 8 mA, , 9V, , 10 V, , IB 2 = 40 µ A, , IC 2 = 8.2 mA, , ∆ IC, , Figure 3.25 Determining ac, for the transistor characteristics of, Fig. 3.24 at IC 7 mA and, VCE 5 V., , 134, , 9 div, ≅ 10, , IC 1 = 6.4 mA, IC = 6 mA, , Chapter 3, , Bipolar Junction Transistors, , Q-point, ( IC = 7 m A, VCE = 5 V), IB 1 = 30 µ A, , VCE = 5 V
Page 146 :
Using Eq. (3.11) gives us, ac, , IC, , IB, , IC2 IC1, 8.2 mA 6.4 mA, , , 40 A 30 A, I, I, VCE constant, B2, B1, , , , 1.8 mA, 180, 10 A, verifying the determination above., , Advanced Digital Meters, Advanced digital meters such as that shown in Fig. 3.26 are now available that can, provide the level of hFE using the lead sockets appearing at the bottom left of the dial., Note the choice of pnp or npn and the availability of two emitter connections to handle the sequence of leads as connected to the casing. The level of hFE is determined, at a collector current of 2 mA for the Testmate 175A, which is also provided on the, digital display. Note that this versatile instrument can also check a diode. It can measure capacitance and frequency in addition to the normal functions of voltage, current, and resistance measurements., In fact, in the diode testing mode it can be used to check the p-n junctions of a, transistor. With the collector open the base-to-emitter junction should result in a low, voltage of about 0.7 V with the red (positive) lead connected to the base and the black, (negative) lead connected to the emitter. A reversal of the leads should result in an, OL indication to represent the reverse-biased junction. Similarly, with the emitter, open, the forward- and reverse-bias states of the base-to-collector junction can be, checked., , Figure 3.26 Transistor tester., (Courtesy Computronics Technology, Inc.), , Ohmmeter, An ohmmeter or the resistance scales of a DMM can be used to check the state of a, transistor. Recall that for a transistor in the active region the base-to-emitter junction, is forward-biased and the base-to-collector junction is reverse-biased. Essentially,, therefore, the forward-biased junction should register a relatively low resistance while, the reverse-biased junction shows a much higher resistance. For an npn transistor, the, forward-biased junction (biased by the internal supply in the resistance mode) from, base to emitter should be checked as shown in Fig. 3.27 and result in a reading that, will typically fall in the range of 100 to a few kilohms. The reverse-biased baseto-collector junction (again reverse-biased by the internal supply) should be checked, as shown in Fig. 3.28 with a reading typically exceeding 100 k. For a pnp transistor the leads are reversed for each junction. Obviously, a large or small resistance in, both directions (reversing the leads) for either junction of an npn or pnp transistor indicates a faulty device., If both junctions of a transistor result in the expected readings the type of transistor can also be determined by simply noting the polarity of the leads as applied to, the base-emitter junction. If the positive () lead is connected to the base and the, negative lead ( ) to the emitter a low resistance reading would indicate an npn transistor. A high resistance reading would indicate a pnp transistor. Although an ohmmeter can also be used to determine the leads (base, collector and emitter) of a transistor it is assumed that this determination can be made by simply looking at the, orientation of the leads on the casing., 3.10 Transistor Testing, , Low R, Open, Ω, + –, , B, , E, , Figure 3.27 Checking the, forward-biased base-to-emitter, junction of an npn transistor., High R, Ω, + –, , C, , B, E, , Figure 3.28 Checking the, reverse-biased base-to-collector, junction of an npn transistor., , 135
Page 147 :
3.11 TRANSISTOR CASING AND, TERMINAL IDENTIFICATION, After the transistor has been manufactured using one of the techniques described in, Chapter 12, leads of, typically, gold, aluminum, or nickel are then attached and the, entire structure is encapsulated in a container such as that shown in Fig. 3.29. Those, with the heavy duty construction are high-power devices, while those with the small, can (top hat) or plastic body are low- to medium-power devices., , Figure 3.29 Various types of transistors: (a) Courtesy General Electric Company;, (b) and (c) Courtesy of Motorola Inc.; (d) Courtesy International Rectifier Corporation., , Whenever possible, the transistor casing will have some marking to indicate which, leads are connected to the emitter, collector, or base of a transistor. A few of the methods commonly used are indicated in Fig. 3.30., , Figure 3.30 Transistor terminal identification., , The internal construction of a TO-92 package in the Fairchild line appears in Fig., 3.31. Note the very small size of the actual semiconductor device. There are gold, bond wires, a copper frame, and an epoxy encapsulation., Four (quad) individual pnp silicon transistors can be housed in the 14-pin plastic, dual-in-line package appearing in Fig. 3.32a. The internal pin connections appear in, Fig. 3.32b. As with the diode IC package, the indentation in the top surface reveals, the number 1 and 14 pins., 136, , Chapter 3, , Bipolar Junction Transistors
Page 148 :
Figure 3.31 Internal construction of a Fairchild transistor in a TO-92 package., (Courtesy Fairchild Camera and Instrument Corporation.), , (Top View), C, , B, , E, , NC, , E, , B, , C, , 14, , 13, , 12, , 11, , 10, , 9, , 8, , 1, , 2, , 3, , 4, , 5, , 6, , 7, , C, , B, , E, , NC, , E, , B, , C, , NC – No internal connection, (a), , (b), , Figure 3.32 Type Q2T2905 Texas Instruments quad pnp silicon transistors:, (a) appearance; (b) pin connections. (Courtesy Texas Instruments Incorporated.), , 3.11 Transistor Casing and Terminal Identification, , 137
Page 149 :
3.12 PSPICE WINDOWS, Since the transistor characteristics were introduced in this chapter it seems appropriate that a procedure for obtaining those characteristics using PSpice Windows should, be examined. The transistors are listed in the EVAL.slb library and start with the letter Q. The library includes two npn transistors and two pnp transistors. The fact that, there are a series of curves defined by the levels of IB will require that a sweep of IB, values (a nested sweep) occur within a sweep of collector-to-emitter voltages. This is, unnecessary for the diode, however, since only one curve would result., First, the network in Fig. 3.33 is established using the same procedure defined in, Chapter 2. The voltage VCC will establish our main sweep while the voltage VBB will, determine the nested sweep. For future reference, note the panel at the top right of, the menu bar with the scroll control when building networks. This option allows you, to retrieve elements that have been used in the past. For instance, if you placed a resistor a few elements ago, simply return to the scroll bar and scroll until the resistor, R appears. Click the location once, and the resistor will appear on the screen., , Figure 3.33 Network employed to obtain the collector characteristics of the, Q2N2222 transistor., , Next, choose the Analysis Setup icon and enable the DC Sweep. Click on DC, Sweep, and choose Voltage Source and Linear. Type in the Name VCC with a Start, Value of 0 V and an End Value of 10 V. Use an Increment of 0.01 V to ensure a continuous, detailed plot. Rather than click OK, this time we have to choose the Nested, Sweep at the bottom left of the dialog box. When chosen, a DC Nested Sweep dialog, box will appear and ask us to repeat the choices just made for the voltage VBB. Again,, Voltage Source and Linear are chosen, and the name is inserted as VBB. The Start Value, will now be 2.7 V to correspond with an initial current of 20 A as determined by, VBB VBE, 2.7 V 0.7 V, 20 A, IB , RB, 100 k, The Increment will be 2V, corresponding with a change in base current of 20 A, between IB levels. The final value will be 10.7 V, corresponding with a current of 100, A. Before leaving the dialog box, be sure to enable the nested sweep. Then, choose, OK, followed by a closing of the Analysis Setup, and we are ready for the analysis., This time we will automatically Run Probe after the analysis by choosing AnalysisProbe Setup, followed by selecting Automatically run Probe after simulation. After choosing OK, followed by a clicking of the Simulation icon (recall that it was the, 138, , Chapter 3, , Bipolar Junction Transistors
Page 150 :
icon with the yellow background and two waveforms), the OrCAD MicroSim Probe, screen will automatically appear. This time, since VCC is the collector-to-emitter voltage, there is no need to label the voltage at the collector. In fact, since it appears as, the horizontal axis of the Probe response, there is no need to touch the X-Axis Settings at all if we recognize that VCC is the collector-to-emitter voltage. For the vertical axis, we turn to Trace-Add and obtain the Add Traces dialog box. Choosing, IC(Q1) and OK, we obtain the transistor characteristics. Unfortunately, however, they, extend from 10 to 20 mA on the vertical axis. This can be corrected by choosing, Plot and then Y-Axis Settings to obtain the Y-Axis Settings dialog box. By choosing User Defined, the range can be set from 0 to 20 mA with a Linear scale. Choose, OK again, and the characteristics of Fig. 3.34 result., , Figure 3.34 Collector characteristics for the transistor of Figure 3.33., , Using the ABC icon on the menu bar, the various levels of IB can be inserted, along with the axis labels VCE and IC. Simply click on the icon, and a dialog box appears asking for the text material. Enter the desired text, click OK, and it will appear, on the screen. It can then be placed in the desired location., If the ac beta is determined in the middle of the graph, you will find that its value is, about 190—even though Bf in the list of specifications is 255.9. Again, like the diode,, the other parameters of the element have a noticeable effect on the total operation., However, if we return to the diode specifications through Edit-Model-Edit, Instance Model (Text) and remove all parameters of the device except Bf 255.9 (don’t, forget the close parentheses at the end of the listing) and follow with an OK and a Simulation, a new set of curves will result. An adjustment of the range of the y-axis to, 0–30 mA using the Y-Axis Settings will result in the characteristic curves of Fig. 3.35., Note first that the curves are all horizontal, meaning that the element is void of, any resistive elements. In addition, the equal spacing of the curves throughout reveals, that beta is the same everywhere (as specified by our new device characteristics). Using a difference of 5 mA between any two curves and dividing by the difference in, IB of 20 A will result in a of 250, which is essentially the same as that specified, for the device., 3.12 PSpice Windows, , 139
Page 151 :
FIGURE 3.35 Ideal collector, characteristics for the transistor of, Figure 3.33., , PROBLEMS, , § 3.2 Transistor Construction, 1. What names are applied to the two types of BJT transistors? Sketch the basic construction of, each and label the various minority and majority carriers in each. Draw the graphic symbol next, to each. Is any of this information altered by changing from a silicon to a germanium base?, 2. What is the major difference between a bipolar and a unipolar device?, , § 3.3 Transistor Operation, 3. How must the two transistor junctions be biased for proper transistor amplifier operation?, 4. What is the source of the leakage current in a transistor?, 5. Sketch a figure similar to Fig. 3.3 for the forward-biased junction of an npn transistor. Describe, the resulting carrier motion., 6. Sketch a figure similar to Fig. 3.4 for the reverse-biased junction of an npn transistor. Describe, the resulting carrier motion., 7. Sketch a figure similar to Fig. 3.5 for the majority- and minority-carrier flow of an npn transistor. Describe the resulting carrier motion., 8. Which of the transistor currents is always the largest? Which is always the smallest? Which, two currents are relatively close in magnitude?, 9. If the emitter current of a transistor is 8 mA and IB is 1/100 of IC, determine the levels of IC, and IB., , § 3.4 Common-Base Configuration, 10. From memory, sketch the transistor symbol for a pnp and an npn transistor, and then insert the, conventional flow direction for each current., 11. Using the characteristics of Fig. 3.7, determine VBE at IE 5 mA for VCB 1, 10, and 20 V., Is it reasonable to assume on an approximate basis that VCB has only a slight effect on the relationship between VBE and IE?, 12. (a) Determine the average ac resistance for the characteristics of Fig. 3.10b., (b) For networks in which the magnitude of the resistive elements is typically in kilohms, is, the approximation of Fig. 3.10c a valid one [based on the results of part (a)]?, , 140, , Chapter 3, , Bipolar Junction Transistors
Page 152 :
13. (a) Using the characteristics of Fig. 3.8, determine the resulting collector current if IE 4.5 mA, and VCB 4 V., (b) Repeat part (a) for IE 4.5 mA and VCB 16 V., (c) How have the changes in VCB affected the resulting level of IC?, (d) On an approximate basis, how are IE and IC related based on the results above?, 14. (a) Using the characteristics of Figs. 3.7 and 3.8, determine IC if VCB 10 V and VBE , 800 mV., (b) Determine VBE if IC 5 mA and VCB 10 V., (c) Repeat part (b) using the characteristics of Fig. 3.10b., (d) Repeat part (b) using the characteristics of Fig. 3.10c., (e) Compare the solutions for VBE for parts (b), (c), and (d). Can the difference be ignored if, voltage levels greater than a few volts are typically encountered?, 15. (a) Given an dc of 0.998, determine IC if IE 4 mA., (b) Determine dc if IE 2.8 mA and IB 20 A., (c) Find IE if IB 40 A and dc is 0.98., 16. From memory, and memory only, sketch the common-base BJT transistor configuration (for, npn and pnp) and indicate the polarity of the applied bias and resulting current directions., , § 3.5 Transistor Amplifying Action, 17. Calculate the voltage gain (Av VL/Vi) for the network of Fig. 3.12 if Vi 500 mV and, R 1 k. (The other circuit values remain the same.), 18. Calculate the voltage gain (Av VL/Vi) for the network of Fig. 3.12 if the source has an internal resistance of 100 in series with Vi., , § 3.6 Common-Emitter Configuration, 19. Define ICBO and ICEO. How are they different? How are they related? Are they typically close, in magnitude?, 20. Using the characteristics of Fig. 3.14:, (a) Find the value of IC corresponding to VBE 750 mV and VCE 5 V., (b) Find the value of VCE and VBE corresponding to IC 3 mA and IB 30 A., * 21. (a) For the common-emitter characteristics of Fig. 3.14, find the dc beta at an operating point, of VCE 8 V and IC 2 mA., (b) Find the value of corresponding to this operating point., (c) At VCE 8 V, find the corresponding value of ICEO., (d) Calculate the approximate value of ICBO using the dc beta value obtained in part (a)., * 22. (a) Using the characteristics of Fig. 3.14a, determine ICEO at VCE 10 V., (b) Determine dc at IB 10 A and VCE 10 V., (c) Using the dc determined in part (b), calculate ICBO., 23. (a), (b), (c), (d), , Using the characteristics of Fig. 3.14a, determine dc at IB 80 A and VCE 5 V., Repeat part (a) at IB 5 A and VCE 15 V., Repeat part (a) at IB 30 A and VCE 10 V., Reviewing the results of parts (a) through (c), does the value of dc change from point to, point on the characteristics? Where were the higher values found? Can you develop any, general conclusions about the value of dc on a set of characteristics such as those provided in Fig. 3.14a?, , Using the characteristics of Fig. 3.14a, determine ac at IB 80 A and VCE 5 V., Repeat part (a) at IB 5 A and VCE 15 V., Repeat part (a) at IB 30 A and VCE 10 V., Reviewing the results of parts (a) through (c), does the value of ac change from point to, point on the characteristics? Where are the high values located? Can you develop any general conclusions about the value of ac on a set of collector characteristics?, (e) The chosen points in this exercise are the same as those employed in Problem 23. If Problem 23 was performed, compare the levels of dc and ac for each point and comment on, the trend in magnitude for each quantity., , * 24. (a), (b), (c), (d), , Problems, , 141
Page 153 :
25. Using the characteristics of Fig. 3.14a, determine dc at IB 25 A and VCE 10 V. Then calculate dc and the resulting level of IE. (Use the level of IC determined by IC dcIB.), 26. (a) Given that dc 0.987, determine the corresponding value of, (b) Given dc 120, determine the corresponding value of ., (c) Given that dc 180 and IC 2.0 mA, find IE and IB., , dc., , 27. From memory, and memory only, sketch the common-emitter configuration (for npn and pnp), and insert the proper biasing arrangement with the resulting current directions for IB, IC, and, IE., , § 3.7 Common-Collector Configuration, 28. An input voltage of 2 V rms (measured from base to ground) is applied to the circuit of Fig., 3.21. Assuming that the emitter voltage follows the base voltage exactly and that Vbe (rms) , 0.1 V, calculate the circuit voltage amplification (Av Vo /Vi ) and emitter current for RE 1 k., 29. For a transistor having the characteristics of Fig. 3.14, sketch the input and output characteristics of the common-collector configuration., , § 3.8 Limits of Operation, 30. Determine the region of operation for a transistor having the characteristics of Fig. 3.14 if, ICmax 7 mA, VCEmax 17 V, and PCmax 40 mW., 31. Determine the region of operation for a transistor having the characteristics of Fig. 3.8 if, ICmax 6 mA, VCBmax 15 V, and PCmax 30 mW., , § 3.9 Transistor Specification Sheet, 32. Referring to Fig. 3.23, determine the temperature range for the device in degrees Fahrenheit., 33. Using the information provided in Fig. 3.23 regarding PDmax, VCEmax, ICmax and VCEsat, sketch the, boundaries of operation for the device., 34. Based on the data of Fig. 3.23, what is the expected value of ICEO using the average value of, dc?, 35. How does the range of hFE (Fig. 3.23(j), normalized from hFE 100) compare with the range, of hfe (Fig. 3.23(f)) for the range of IC from 0.1 to 10 mA?, 36. Using the characteristics of Fig. 3.23b, determine whether the input capacitance in the, common-base configuration increases or decreases with increasing levels of reverse-bias potential. Can you explain why?, * 37. Using the characteristics of Fig. 3.23f, determine how much the level of hfe has changed from, its value at 1 mA to its value at 10 mA. Note that the vertical scale is a log scale that may require reference to Section 11.2. Is the change one that should be considered in a design situation?, * 38. Using the characteristics of Fig. 3.23j, determine the level of dc at IC 10 mA at the three, levels of temperature appearing in the figure. Is the change significant for the specified temperature range? Is it an element to be concerned about in the design process?, , § 3.10 Transistor Testing, 39. (a), (b), (c), (d), (e), (f), , Using the characteristics of Fig. 3.24, determine ac at IC 14 mA and VCE 3 V., Determine dc at IC 1 mA and VCE 8 V., Determine ac at IC 14 mA and VCE 3 V., Determine dc at IC 1 mA and VCE 8 V., How does the level of ac and dc compare in each region?, Is the approximation dc ac a valid one for this set of characteristics?, , *Please Note: Asterisks indicate more difficult problems., , 142, , Chapter 3, , Bipolar Junction Transistors
Page 154 :
CHAPTER, , DC Biasing—BJTs, , 4, , 4.1 INTRODUCTION, The analysis or design of a transistor amplifier requires a knowledge of both the dc, and ac response of the system. Too often it is assumed that the transistor is a magical device that can raise the level of the applied ac input without the assistance of an, external energy source. In actuality, the improved output ac power level is the result, of a transfer of energy from the applied dc supplies. The analysis or design of any, electronic amplifier therefore has two components: the dc portion and the ac portion., Fortunately, the superposition theorem is applicable and the investigation of the dc, conditions can be totally separated from the ac response. However, one must keep in, mind that during the design or synthesis stage the choice of parameters for the required dc levels will affect the ac response, and vice versa., The dc level of operation of a transistor is controlled by a number of factors, including the range of possible operating points on the device characteristics. In Section 4.2 we specify the range for the BJT amplifier. Once the desired dc current and, voltage levels have been defined, a network must be constructed that will establish, the desired operating point—a number of these networks are analyzed in this chapter. Each design will also determine the stability of the system, that is, how sensitive, the system is to temperature variations—another topic to be investigated in a later, section of this chapter., Although a number of networks are analyzed in this chapter, there is an underlying similarity between the analysis of each configuration due to the recurring use of, the following important basic relationships for a transistor:, VBE 0.7 V, , (4.1), , IE ( 1)IB IC, , (4.2), , IC IB, , (4.3), , In fact, once the analysis of the first few networks is clearly understood, the path, toward the solution of the networks to follow will begin to become quite apparent. In, most instances the base current IB is the first quantity to be determined. Once IB is, known, the relationships of Eqs. (4.1) through (4.3) can be applied to find the remaining quantities of interest. The similarities in analysis will be immediately obvious as we progress through the chapter. The equations for IB are so similar for a num-, , 143
Page 155 :
ber of configurations that one equation can be derived from another simply by dropping or adding a term or two. The primary function of this chapter is to develop a, level of familiarity with the BJT transistor that would permit a dc analysis of any system that might employ the BJT amplifier., , 4.2 OPERATING POINT, The term biasing appearing in the title of this chapter is an all-inclusive term for the, application of dc voltages to establish a fixed level of current and voltage. For transistor amplifiers the resulting dc current and voltage establish an operating point on, the characteristics that define the region that will be employed for amplification of, the applied signal. Since the operating point is a fixed point on the characteristics, it, is also called the quiescent point (abbreviated Q-point). By definition, quiescent means, quiet, still, inactive. Figure 4.1 shows a general output device characteristic with four, operating points indicated. The biasing circuit can be designed to set the device operation at any of these points or others within the active region. The maximum ratings are indicated on the characteristics of Fig. 4.1 by a horizontal line for the maximum collector current ICmax and a vertical line at the maximum collector-to-emitter, voltage VCEmax. The maximum power constraint is defined by the curve PCmax in the, same figure. At the lower end of the scales are the cutoff region, defined by IB , 0 , and the saturation region, defined by VCE VCEsat., The BJT device could be biased to operate outside these maximum limits, but the, result of such operation would be either a considerable shortening of the lifetime of, the device or destruction of the device. Confining ourselves to the active region, one, can select many different operating areas or points. The chosen Q-point often depends, on the intended use of the circuit. Still, we can consider some differences among the, , IC (mA), , 80 µA, 70 µA, , IC max 25, 60 µA, 50 µA, , 20, , 40 µA, , PC max, 15, , 30 µA, Saturation, , B, , 10, , 20 µA, , D, , 10 µA, , 5, , C, I B = 0 µA, , A, 0, , VCE sat, , 5, , 10, , 15, , 20, , Cutoff, VCE max, , Figure 4.1 Various operating points within the limits of operation of a transistor., , 144, , Chapter 4, , DC Biasing—BJTs, , VCE (V)
Page 156 :
various points shown in Fig. 4.1 to present some basic ideas about the operating point, and, thereby, the bias circuit., If no bias were used, the device would initially be completely off, resulting in a, Q-point at A—namely, zero current through the device (and zero voltage across it)., Since it is necessary to bias a device so that it can respond to the entire range of an, input signal, point A would not be suitable. For point B, if a signal is applied to the, circuit, the device will vary in current and voltage from operating point, allowing the, device to react to (and possibly amplify) both the positive and negative excursions of, the input signal. If the input signal is properly chosen, the voltage and current of the, device will vary but not enough to drive the device into cutoff or saturation. Point C, would allow some positive and negative variation of the output signal, but the peakto-peak value would be limited by the proximity of VCE 0V/IC 0 mA. Operating, at point C also raises some concern about the nonlinearities introduced by the fact, that the spacing between IB curves is rapidly changing in this region. In general, it is, preferable to operate where the gain of the device is fairly constant (or linear) to ensure that the amplification over the entire swing of input signal is the same. Point B, is a region of more linear spacing and therefore more linear operation, as shown in, Fig. 4.1. Point D sets the device operating point near the maximum voltage and power, level. The output voltage swing in the positive direction is thus limited if the maximum voltage is not to be exceeded. Point B therefore seems the best operating point, in terms of linear gain and largest possible voltage and current swing. This is usually, the desired condition for small-signal amplifiers (Chapter 8) but not the case necessarily for power amplifiers, which will be considered in Chapter 16. In this discussion, we will be concentrating primarily on biasing the transistor for small-signal amplification operation., One other very important biasing factor must be considered. Having selected and, biased the BJT at a desired operating point, the effect of temperature must also be, taken into account. Temperature causes the device parameters such as the transistor, current gain (ac) and the transistor leakage current (ICEO) to change. Higher temperatures result in increased leakage currents in the device, thereby changing the operating condition set by the biasing network. The result is that the network design, must also provide a degree of temperature stability so that temperature changes result in minimum changes in the operating point. This maintenance of the operating, point can be specified by a stability factor, S, which indicates the degree of change, in operating point due to a temperature variation. A highly stable circuit is desirable,, and the stability of a few basic bias circuits will be compared., For the BJT to be biased in its linear or active operating region the following must, be true:, 1. The base–emitter junction must be forward-biased (p-region voltage more positive), with a resulting forward-bias voltage of about 0.6 to 0.7 V., 2. The base–collector junction must be reverse-biased (n-region more positive), with, the reverse-bias voltage being any value within the maximum limits of the device., [Note that for forward bias the voltage across the p-n junction is p-positive, while for, reverse bias it is opposite (reverse) with n-positive. This emphasis on the initial letter should provide a means of helping memorize the necessary voltage polarity.], Operation in the cutoff, saturation, and linear regions of the BJT characteristic are, provided as follows:, 1. Linear-region operation:, Base–emitter junction forward biased, Base–collector junction reverse biased, 4.2 Operating Point, , 145
Page 157 :
2. Cutoff-region operation:, Base–emitter junction reverse biased, 3. Saturation-region operation:, Base–emitter junction forward biased, Base–collector junction forward biased, , 4.3 FIXED-BIAS CIRCUIT, The fixed-bias circuit of Fig. 4.2 provides a relatively straightforward and simple introduction to transistor dc bias analysis. Even though the network employs an npn, transistor, the equations and calculations apply equally well to a pnp transistor configuration merely by changing all current directions and voltage polarities. The current directions of Fig. 4.2 are the actual current directions, and the voltages are defined by the standard double-subscript notation. For the dc analysis the network can, be isolated from the indicated ac levels by replacing the capacitors with an opencircuit equivalent. In addition, the dc supply VCC can be separated into two supplies, (for analysis purposes only) as shown in Fig. 4.3 to permit a separation of input and, output circuits. It also reduces the linkage between the two to the base current IB. The, separation is certainly valid, as we note in Fig. 4.3 that VCC is connected directly to, RB and RC just as in Fig. 4.2., VCC, , IC, , RC, RB, C, ac, input, signal, , IB, C1, , B, , C2, , +, , ac, output, signal, , VCE, , +, VBE, , –, , –, E, , Figure 4.2 Fixed-bias circuit., , Figure 4.3 dc equivalent of, Fig. 4.2., , Forward Bias of Base–Emitter, Consider first the base–emitter circuit loop of Fig. 4.4. Writing Kirchhoff’s voltage, equation in the clockwise direction for the loop, we obtain, VCC IBRB VBE 0, Note the polarity of the voltage drop across RB as established by the indicated direction of IB. Solving the equation for the current IB will result in the following:, IB , , VCC VBE, RB, , (4.4), , Figure 4.4 Base–emitter loop., , Equation (4.4) is certainly not a difficult one to remember if one simply keeps in, mind that the base current is the current through RB and by Ohm’s law that current, is the voltage across RB divided by the resistance RB. The voltage across RB is the applied voltage VCC at one end less the drop across the base-to-emitter junction (VBE)., , 146, , Chapter 4, , DC Biasing—BJTs
Page 158 :
In addition, since the supply voltage VCC and the base–emitter voltage VBE are constants, the selection of a base resistor, RB, sets the level of base current for the operating point., , Collector–Emitter Loop, The collector–emitter section of the network appears in Fig. 4.5 with the indicated, direction of current IC and the resulting polarity across RC. The magnitude of the collector current is related directly to IB through, IC IB, , (4.5), , It is interesting to note that since the base current is controlled by the level of RB, and IC is related to IB by a constant , the magnitude of IC is not a function of the, resistance RC. Change RC to any level and it will not affect the level of IB or IC as, long as we remain in the active region of the device. However, as we shall see, the, level of RC will determine the magnitude of VCE, which is an important parameter., Applying Kirchhoff’s voltage law in the clockwise direction around the indicated, closed loop of Fig. 4.5 will result in the following:, , Figure 4.5 Collector–emitter, loop., , VCE ICRC VCC 0, and, , VCE VCC ICRC, , (4.6), , which states in words that the voltage across the collector–emitter region of a transistor in the fixed-bias configuration is the supply voltage less the drop across RC., As a brief review of single- and double-subscript notation recall that, VCE VC VE, , (4.7), , where VCE is the voltage from collector to emitter and VC and VE are the voltages, from collector and emitter to ground respectively. But in this case, since VE 0 V,, we have, VCE VC, , (4.8), , VBE VB VE, , (4.9), , VBE VB, , (4.10), , In addition, since, , and VE 0 V, then, , Keep in mind that voltage levels such as VCE are determined by placing the red, (positive) lead of the voltmeter at the collector terminal with the black (negative) lead, at the emitter terminal as shown in Fig. 4.6. VC is the voltage from collector to ground, and is measured as shown in the same figure. In this case the two readings are identical, but in the networks to follow the two can be quite different. Clearly understanding the difference between the two measurements can prove to be quite important in the troubleshooting of transistor networks., Determine the following for the fixed-bias configuration of Fig. 4.7., (a) IBQ and ICQ., (b) VCEQ., (c) VB and VC., (d) VBC., 4.3 Fixed-Bias Circuit, , Figure 4.6 Measuring VCE and, VC., , EXAMPLE 4.1, , 147
Page 159 :
Figure 4.7 dc fixed-bias circuit for Example 4.1., , Solution, VCC VBE, 12 V 0.7 V, , 47.08 A, RB, 240 k, Eq. (4.5): ICQ IBQ (50)(47.08 A) 2.35 mA, (b) Eq. (4.6): VCEQ VCC ICRC, 12 V (2.35 mA)(2.2 k ), 6.83 V, (c) VB VBE 0.7 V, VC VCE 6.83 V, (d) Using double-subscript notation yields, , (a) Eq. (4.4): IBQ , , VBC VB VC 0.7 V 6.83 V, 6.13 V, with the negative sign revealing that the junction is reversed-biased, as it should be, for linear amplification., , Transistor Saturation, The term saturation is applied to any system where levels have reached their maximum values. A saturated sponge is one that cannot hold another drop of liquid. For, a transistor operating in the saturation region, the current is a maximum value for the, particular design. Change the design and the corresponding saturation level may rise, or drop. Of course, the highest saturation level is defined by the maximum collector, current as provided by the specification sheet., Saturation conditions are normally avoided because the base–collector junction is, no longer reverse-biased and the output amplified signal will be distorted. An operating point in the saturation region is depicted in Fig. 4.8a. Note that it is in a region, where the characteristic curves join and the collector-to-emitter voltage is at or below VCEsat. In addition, the collector current is relatively high on the characteristics., If we approximate the curves of Fig. 4.8a by those appearing in Fig. 4.8b, a quick,, direct method for determining the saturation level becomes apparent. In Fig. 4.8b, the, current is relatively high and the voltage VCE is assumed to be zero volts. Applying, Ohm’s law the resistance between collector and emitter terminals can be determined, as follows:, 0V, V, 0, RCE CE , ICsat, IC, 148, , Chapter 4, , DC Biasing—BJTs
Page 160 :
IC, , IC, I C sat –, , 0, , Q-point, , I C sat –, , 0, , VCE, , VCE sat, , Q-point, , VCE, , (a), , (b), , Figure 4.8 Saturation regions: (a) actual; (b) approximate., , Applying the results to the network schematic would result in the configuration of, Fig. 4.9., For the future, therefore, if there were an immediate need to know the approximate maximum collector current (saturation level) for a particular design, simply insert a short-circuit equivalent between collector and emitter of the transistor and calculate the resulting collector current. In short, set VCE 0 V. For the fixed-bias, configuration of Fig. 4.10, the short circuit has been applied, causing the voltage across, RC to be the applied voltage VCC. The resulting saturation current for the fixed-bias, configuration is, ICsat , , VCC, RC, , Figure 4.9 Determining ICsat., , (4.11), , Figure 4.10 Determining ICsat, for the fixed-bias configuration., , Once ICsat is known, we have some idea of the maximum possible collector current, for the chosen design and the level to stay below if we expect linear amplification., , EXAMPLE 4.2, , Determine the saturation level for the network of Fig. 4.7., , Solution, ICsat , , VCC, 12 V, , 5.45 mA, RC, 2.2 k, , 4.3 Fixed-Bias Circuit, , 149
Page 161 :
The design of Example 4.1 resulted in ICQ 2.35 mA, which is far from the saturation level and about one-half the maximum value for the design., , Load-Line Analysis, The analysis thus far has been performed using a level of corresponding with the, resulting Q-point. We will now investigate how the network parameters define the, possible range of Q-points and how the actual Q-point is determined. The network of, Fig. 4.11a establishes an output equation that relates the variables IC and VCE in the, following manner:, VCE VCC ICRC, , (4.12), , The output characteristics of the transistor also relate the same two variables IC and, VCE as shown in Fig. 4.11b., In essence, therefore, we have a network equation and a set of characteristics that, employ the same variables. The common solution of the two occurs where the constraints established by each are satisfied simultaneously. In other words, this is similar to finding the solution of two simultaneous equations: one established by the network and the other by the device characteristics., The device characteristics of IC versus VCE are provided in Fig. 4.11b. We must, now superimpose the straight line defined by Eq. (4.12) on the characteristics. The, most direct method of plotting Eq. (4.12) on the output characteristics is to use the, fact that a straight line is defined by two points. If we choose IC to be 0 mA, we are, specifying the horizontal axis as the line on which one point is located. By substituting IC 0 mA into Eq. (4.12), we find that, VCE VCC (0)RC, VCE VCC IC0 mA, , and, , (4.13), , defining one point for the straight line as shown in Fig. 4.12., , IC (mA), 50 µA, , 8, 7, , 40 µA, , 6, 30 µA, , 5, V CC, IC, , +, RB, , 4, , RC, , 3, , +, , 2, , 20 µA, , –, VCE, IB, , –, , 10 µA, I B = 0 µA, , 1, , 0, , 5, , 10, , 15, , ICEO, (a), , (b), , Figure 4.11 Load-line analysis: (a) the network; (b) the device characteristics., , 150, , Chapter 4, , DC Biasing—BJTs, , VCE (V)
Page 162 :
IC, , VCC, RC, , Q-point, , IB, , VCE = 0 V, , Q, , Load line, , 0, , VCC, IC = 0 mA, , VCE, , Figure 4.12 Fixed-bias, load line., , If we now choose VCE to be 0 V, which establishes the vertical axis as the line on, which the second point will be defined, we find that IC is determined by the following equation:, 0 VCC ICRC, and, , IC , , VCC, RC, , , , VCE 0 V, , (4.14), , as appearing on Fig. 4.12., By joining the two points defined by Eqs. (4.13) and (4.14), the straight line established by Eq. (4.12) can be drawn. The resulting line on the graph of Fig. 4.12 is, called the load line since it is defined by the load resistor RC. By solving for the resulting level of IB, the actual Q-point can be established as shown in Fig. 4.12., If the level of IB is changed by varying the value of RB the Q-point moves up or, down the load line as shown in Fig. 4.13. If VCC is held fixed and RC changed, the, load line will shift as shown in Fig. 4.14. If IB is held fixed, the Q-point will move, as shown in the same figure. If RC is fixed and VCC varied, the load line shifts as, shown in Fig. 4.15., , Figure 4.13 Movement of Q-point with increasing levels of IB., , Figure 4.14 Effect of increasing levels of RC on the load, line and Q-point., , 4.3 Fixed-Bias Circuit, , 151
Page 164 :
4.4 EMITTER-STABILIZED BIAS CIRCUIT, The dc bias network of Fig. 4.17 contains an emitter resistor to improve the stability, level over that of the fixed-bias configuration. The improved stability will be demonstrated through a numerical example later in the section. The analysis will be performed by first examining the base–emitter loop and then using the results to investigate the collector–emitter loop., , Figure 4.17 BJT bias circuit, with emitter resistor., , Base–Emitter Loop, The base–emitter loop of the network of Fig. 4.17 can be redrawn as shown in Fig., 4.18. Writing Kirchhoff’s voltage law around the indicated loop in the clockwise direction will result in the following equation:, VCC IBRB VBE IERE 0, , (4.15), , Recall from Chapter 3 that, IE ( 1)IB, , (4.16), , Substituting for IE in Eq. (4.15) will result in, VCC IBRB VBE ( I)IBRE 0, Grouping terms will then provide the following:, IB(RB ( 1)RE) VCC VBE 0, Multiplying through by (1) we have, with, , IB(RB ( 1)RE)VCC VBE 0, IB(RB ( 1)RE) VCC VBE, , and solving for IB gives, IB , , VCC VBE, RB ( 1)RE, , (4.17), , Note that the only difference between this equation for IB and that obtained for the, fixed-bias configuration is the term ( 1)RE., There is an interesting result that can be derived from Eq. (4.17) if the equation, is used to sketch a series network that would result in the same equation. Such is, 4.4 Emitter-Stabilized Bias Circuit, , Figure 4.18 Base–emitter loop., , 153
Page 165 :
Figure 4.20 Reflected impedance, level of RE., , Figure 4.19 Network derived, from Eq. (4.17)., , the case for the network of Fig. 4.19. Solving for the current IB will result in the same, equation obtained above. Note that aside from the base-to-emitter voltage VBE, the, resistor RE is reflected back to the input base circuit by a factor ( 1). In other, words, the emitter resistor, which is part of the collector–emitter loop, “appears as”, ( 1)RE in the base–emitter loop. Since is typically 50 or more, the emitter resistor appears to be a great deal larger in the base circuit. In general, therefore, for, the configuration of Fig. 4.20,, Ri ( 1)RE, , (4.18), , Equation (4.18) is one that will prove useful in the analysis to follow. In fact, it, provides a fairly easy way to remember Eq. (4.17). Using Ohm’s law, we know that, the current through a system is the voltage divided by the resistance of the circuit., For the base–emitter circuit the net voltage is VCC VBE. The resistance levels are, RB plus RE reflected by ( 1). The result is Eq. (4.17)., , Collector–Emitter Loop, The collector–emitter loop is redrawn in Fig. 4.21. Writing Kirchhoff’s voltage law, for the indicated loop in the clockwise direction will result in, IERE VCE ICRC VCC 0, Substituting IE IC and grouping terms gives, VCE VCC IC (RC RE) 0, VCE VCC IC (RC RE), , and, , (4.19), , The single-subscript voltage VE is the voltage from emitter to ground and is determined by, VE IERE, Figure 4.21 Collector–emitter, loop., , (4.20), , while the voltage from collector to ground can be determined from, VCE VC VE, and, or, , VC VCE VE, , (4.21), , VC VCC ICRC, , (4.22), , The voltage at the base with respect to ground can be determined from, , or, 154, , Chapter 4, , DC Biasing—BJTs, , VB VCC IBRB, , (4.23), , VB VBE VE, , (4.24)
Page 166 :
For the emitter bias network of Fig. 4.22, determine:, (a) IB., (b) IC., (c) VCE., (d) VC., (e) VE., (f) VB., (g) VBC., , EXAMPLE 4.4, , Figure 4.22 Emitter-stabilized, bias circuit for Example 4.4., , Solution, 20 V 0.7 V, VCC VBE, , 430 k (51)(1 k ), RB ( 1)RE, 19.3 V, , 40.1 A, 481 k, , (a) Eq. (4.17): IB , , (b) IC IB, (50)(40.1 A), 2.01 mA, (c) Eq. (4.19): VCE VCC IC (RC RE), 20 V (2.01 mA)(2 k 1 k ) 20 V 6.03 V, 13.97 V, (d) VC VCC ICRC, 20 V (2.01 mA)(2 k ) 20 V 4.02 V, 15.98 V, (e) VE VC VCE, 15.98 V 13.97 V, 2.01 V, or VE IERE ICRE, (2.01 mA)(1 k ), 2.01 V, (f) VB VBE VE, 0.7 V 2.01 V, 2.71 V, (g) VBC VB VC, 2.71 V 15.98 V, 13.27 V (reverse-biased as required), , 4.4 Emitter-Stabilized Bias Circuit, , 155
Page 167 :
Improved Bias Stability, The addition of the emitter resistor to the dc bias of the BJT provides improved stability, that is, the dc bias currents and voltages remain closer to where they were set, by the circuit when outside conditions, such as temperature, and transistor beta,, change. While a mathematical analysis is provided in Section 4.12, some comparison, of the improvement can be obtained as demonstrated by Example 4.5., , EXAMPLE 4.5, , Prepare a table and compare the bias voltage and currents of the circuits of Figs. 4.7, and Fig. 4.22 for the given value of 50 and for a new value of 100. Compare the changes in IC and VCE for the same increase in ., , Solution, Using the results calculated in Example 4.1 and then repeating for a value of 100, yields the following:, , , IB (A), , IC (mA), , VCE (V), , 50, 100, , 47.08, 47.08, , 2.35, 4.71, , 6.83, 1.64, , The BJT collector current is seen to change by 100% due to the 100% change in the, value of . IB is the same and VCE decreased by 76%., Using the results calculated in Example 4.4 and then repeating for a value of, 100, we have the following:, , , IB (A), , IC (mA), , VCE (V), , 50, 100, , 40.1, 36.3, , 2.01, 3.63, , 13.97, 9.11, , Now the BJT collector current increases by about 81% due to the 100% increase in ., Notice that IB decreased, helping maintain the value of IC —or at least reducing the, overall change in IC due to the change in . The change in VCE has dropped to about, 35%. The network of Fig. 4.22 is therefore more stable than that of Fig. 4.7 for the, same change in ., , Saturation Level, The collector saturation level or maximum collector current for an emitter-bias design can be determined using the same approach applied to the fixed-bias configuration: Apply a short circuit between the collector–emitter terminals as shown in Fig., 4.23 and calculate the resulting collector current. For Fig. 4.23:, ICsat , , VCC, RC RE, , (4.25), , Figure 4.23 Determining ICsat for, the emitter-stabilized bias circuit., , The addition of the emitter resistor reduces the collector saturation level below that, obtained with a fixed-bias configuration using the same collector resistor., , 156, , Chapter 4, , DC Biasing—BJTs
Page 168 :
EXAMPLE 4.6, , Determine the saturation current for the network of Example 4.4., , Solution, , ICsat , , , VCC, RC RE, 20 V, 2 k 1 k, , , , 20 V, 3k, , 6.67 mA, which is about twice the level of ICQ for Example 4.4., , Load-Line Analysis, The load-line analysis of the emitter-bias network is only slightly different from that, encountered for the fixed-bias configuration. The level of IB as determined by Eq., (4.17) defines the level of IB on the characteristics of Fig. 4.24 (denoted IBQ)., , Figure 4.24 Load line for the, emitter-bias configuration., , The collector–emitter loop equation that defines the load line is the following:, VCE VCC IC (RC RE), Choosing IC 0 mA gives, VCE VCCIC0 mA, , (4.26), , as obtained for the fixed-bias configuration. Choosing VCE 0 V gives, IC , , VCC, RC RE, , , , VCE0 V, , (4.27), , as shown in Fig. 4.24. Different levels of IBQ will, of course, move the Q-point up or, down the load line., , 4.5 VOLTAGE-DIVIDER BIAS, In the previous bias configurations the bias current ICQ and voltage VCEQ were a function of the current gain () of the transistor. However, since is temperature sensitive, especially for silicon transistors, and the actual value of beta is usually not well, defined, it would be desirable to develop a bias circuit that is less dependent, or in, 4.5 Voltage-Divider Bias, , 157
Page 169 :
Figure 4.26 Defining the Q-point for the voltage-divider, bias configuration., , Figure 4.25 Voltage-divider bias configuration., , fact, independent of the transistor beta. The voltage-divider bias configuration of Fig., 4.25 is such a network. If analyzed on an exact basis the sensitivity to changes in beta, is quite small. If the circuit parameters are properly chosen, the resulting levels of ICQ, and VCEQ can be almost totally independent of beta. Recall from previous discussions, that a Q-point is defined by a fixed level of ICQ and VCEQ as shown in Fig. 4.26. The, level of IBQ will change with the change in beta, but the operating point on the characteristics defined by ICQ and VCEQ can remain fixed if the proper circuit parameters, are employed., As noted above, there are two methods that can be applied to analyze the voltagedivider configuration. The reason for the choice of names for this configuration will, become obvious in the analysis to follow. The first to be demonstrated is the exact, method that can be applied to any voltage-divider configuration. The second is referred to as the approximate method and can be applied only if specific conditions, are satisfied. The approximate approach permits a more direct analysis with a savings, in time and energy. It is also particularly helpful in the design mode to be described, in a later section. All in all, the approximate approach can be applied to the majority, of situations and therefore should be examined with the same interest as the exact, method., , Exact Analysis, The input side of the network of Fig. 4.25 can be redrawn as shown in Fig. 4.27 for, the dc analysis. The Thévenin equivalent network for the network to the left of the, base terminal can then be found in the following manner:, , B, R1, VCC, , R2, , RE, , Thévenin, , 158, , Chapter 4, , DC Biasing—BJTs, , Figure 4.27 Redrawing the, input side of the network of, Fig. 4.25.
Page 170 :
RTh: The voltage source is replaced by a short-circuit equivalent as shown in, Fig. 4.28., RTh R1R2, , R2, , (4.28), , ETh: The voltage source VCC is returned to the network and the open-circuit, Thévenin voltage of Fig. 4.29 determined as follows:, Applying the voltage-divider rule:, ETh VR2 , , R1, , R2VCC, R1 R2, , R Th, , Figure 4.28 Determining RTh., , (4.29), , The Thévenin network is then redrawn as shown in Fig. 4.30, and IBQ can be determined by first applying Kirchhoff’s voltage law in the clockwise direction for the, loop indicated:, , VCC, , +, , +, , R1, R2, , VR E Th, 2, , –, , –, , ETh IBRTh VBE IERE 0, Substituting IE ( 1)IB and solving for IB yields, IB , , Figure 4.29 Determining ETh., , ETh VBE, RTh ( 1)RE, , (4.30), , Although Eq. (4.30) initially appears different from those developed earlier, note, that the numerator is again a difference of two voltage levels and the denominator is, the base resistance plus the emitter resistor reflected by ( 1)—certainly very similar to Eq. (4.17)., Once IB is known, the remaining quantities of the network can be found in the, same manner as developed for the emitter-bias configuration. That is,, VCE VCC IC (RC RE), , RTh, , B, , +, IB, , VBE, , –, , ETh, , E, , RE, , (4.31), , which is exactly the same as Eq. (4.19). The remaining equations for VE, VC, and VB, are also the same as obtained for the emitter-bias configuration., , Figure 4.30 Inserting the, Thévenin equivalent circuit., , Determine the dc bias voltage VCE and the current IC for the voltage-divider configuration of Fig. 4.31., , EXAMPLE 4.7, , Figure 4.31 Beta-stabilized, circuit for Example 4.7., , 4.5 Voltage-Divider Bias, , 159
Page 171 :
Solution, Eq. (4.28):, , RTh R1R2, , , Eq. (4.29):, , ETh , , (39 k )(3.9 k ), 3.55 k, 39 k 3.9 k, R2VCC, R1 R2, , (3.9 k )(22 V), 2V, 39 k 3.9 k, ETh VBE, IB , RTh ( 1)RE, , , Eq. (4.30):, , , , 3.55 k, , 2 V 0.7 V, 1.3 V, , (141)(1.5 k ), 3.55 k 211.5 k, , 6.05 A, IC IB, (140)(6.05 A), 0.85 mA, Eq. (4.31):, , VCE VCC IC (RC RE), 22 V (0.85 mA)(10 k, , 1.5 k ), , 22 V 9.78 V, 12.22 V, , Approximate Analysis, The input section of the voltage-divider configuration can be represented by the network of Fig. 4.32. The resistance Ri is the equivalent resistance between base and, ground for the transistor with an emitter resistor RE. Recall from Section 4.4 [Eq., (4.18)] that the reflected resistance between base and emitter is defined by Ri , ( 1)RE. If Ri is much larger than the resistance R2, the current IB will be much, smaller than I2 (current always seeks the path of least resistance) and I2 will be approximately equal to I1. If we accept the approximation that IB is essentially zero amperes compared to I1 or I2, then I1 I2 and R1 and R2 can be considered series ele-, , Figure 4.32 Partial-bias circuit, for calculating the approximate, base voltage VB., , 160, , Chapter 4, , DC Biasing—BJTs
Page 172 :
ments. The voltage across R2, which is actually the base voltage, can be determined, using the voltage-divider rule (hence the name for the configuration). That is,, VB , , R2VCC, R1 R2, , (4.32), , Since Ri ( 1)RE RE the condition that will define whether the approximate approach can be applied will be the following:, , RE, , 10R2, , (4.33), , In other words, if times the value of RE is at least 10 times the value of R2, the approximate approach can be applied with a high degree of accuracy., Once VB is determined, the level of VE can be calculated from, VE VB VBE, , (4.34), , and the emitter current can be determined from, VE, RE, , (4.35), , ICQ IE, , (4.36), , IE , and, , The collector-to-emitter voltage is determined by, VCE VCC ICRC IERE, but since IE IC,, VCEQ VCC IC (RC RE), , (4.37), , Note in the sequence of calculations from Eq. (4.33) through Eq. (4.37) that , does not appear and IB was not calculated. The Q-point (as determined by ICQ and, VCEQ) is therefore independent of the value of ., , Repeat the analysis of Fig. 4.31 using the approximate technique, and compare solutions for ICQ and VCEQ., , EXAMPLE 4.8, , Solution, Testing:, , RE, (140)(1.5 k ), 210 k, Eq. (4.32):, , 10R2, 10(3.9 k ), 39 k, VB , , , (satisfied), R2VCC, R1 R2, (3.9 k )(22 V), 39 k 3.9 k, , 2V, 4.5 Voltage-Divider Bias, , 161
Page 173 :
Note that the level of VB is the same as ETh determined in Example 4.7. Essentially, therefore, the primary difference between the exact and approximate techniques, is the effect of RTh in the exact analysis that separates ETh and VB., Eq. (4.34):, , VE VB VBE, 2 V 0.7 V, 1.3 V, , ICQ IE , , VE, 1.3 V, , 0.867 mA, RE, 1.5 k, , compared to 0.85 mA with the exact analysis. Finally,, VCEQ VCC IC(RC RE), 22 V (0.867 mA)(10 kV 1.5 k ), 22 V 9.97 V, 12.03 V, versus 12.22 V obtained in Example 4.7., The results for ICQ and VCEQ are certainly close, and considering the actual variation in parameter values one can certainly be considered as accurate as the other., The larger the level of Ri compared to R2, the closer the approximate to the exact solution. Example 4.10 will compare solutions at a level well below the condition established by Eq. (4.33)., , EXAMPLE 4.9, , Repeat the exact analysis of Example 4.7 if is reduced to 70, and compare solutions for ICQ and VCEQ., , Solution, This example is not a comparison of exact versus approximate methods but a testing, of how much the Q-point will move if the level of is cut in half. RTh and ETh are, the same:, RTh 3.55 k ,, IB , , , ETh 2 V, , ETh VBE, RTh ( 1)RE, 2 V 0.7 V, 1.3 V, , 3.55 k (71)(1.5 k ), 3.55 k 106.5 k, , 11.81 A, ICQ IB, (70)(11.81 A), 0.83 mA, VCEQ VCC IC(RC RE), 22 V (0.83 mA)(10 k, 12.46 V, 162, , Chapter 4, , DC Biasing—BJTs, , 1.5 k )
Page 174 :
Tabulating the results, we have:, , , ICQ (mA), , VCEQ (V), , 140, 70, , 0.85, 0.83, , 12.22, 12.46, , The results clearly show the relative insensitivity of the circuit to the change in ., Even though is drastically cut in half, from 140 to 70, the levels of ICQ and VCEQ, are essentially the same., Determine the levels of ICQ and VCEQ for the voltage-divider configuration of Fig. 4.33, using the exact and approximate techniques and compare solutions. In this case, the, conditions of Eq. (4.33) will not be satisfied but the results will reveal the difference, in solution if the criterion of Eq. (4.33) is ignored., , EXAMPLE 4.10, , Figure 4.33 Voltage-divider, configuration for Example 4.10., , Solution, Exact Analysis, , Eq. (4.33):, , RE, , (50)(1.2 k ), 60 k, , 10R2, 10(22 k ), 220 k, , RTh R1R2 82 k 22 k, ETh , IB , , (not satisfied), , 17.35 k, , R2VCC, 22 k (18 V), , 3.81 V, R1 R2, 82 k 22 k, 3.81 V 0.7 V, 3.11 V, ETh VBE, , , 17.35, k, , (51)(1.2, k, ), RTh ( 1)RE, 78.55 k, , 39.6 A, ICQ IB (50)(39.6 A) 1.98 mA, VCEQ VCC IC(RC RE), 18 V (1.98 mA)(5.6 k, , 1.2 k ), , 4.54 V, 4.5 Voltage-Divider Bias, , 163
Page 175 :
Approximate Analysis, , VB ETh 3.81 V, VE VB VBE 3.81 V 0.7 V 3.11 V, ICQ IE , , VE, 3.11 V, , 2.59 mA, RE, 1.2 k, , VCEQ VCC IC (RC RE), 18 V (2.59 mA)(5.6 k, , 1.2 k ), , 3.88 V, Tabulating the results, we have:, , Exact, Approximate, , ICQ (mA), , VCEQ (V), , 1.98, 2.59, , 4.54, 3.88, , The results reveal the difference between exact and approximate solutions. ICQ is about, 30% greater with the approximate solution, while VCEQ is about 10% less. The results, are notably different in magnitude, but even though RE is only about three times, larger than R2, the results are still relatively close to each other. For the future, however, our analysis will be dictated by Eq. (4.33) to ensure a close similarity between, exact and approximate solutions., , Transistor Saturation, The output collector–emitter circuit for the voltage-divider configuration has the same, appearance as the emitter-biased circuit analyzed in Section 4.4. The resulting equation for the saturation current (when VCE is set to zero volts on the schematic) is therefore the same as obtained for the emitter-biased configuration. That is,, VCC, RC RE, , ICsat ICmax , , (4.38), , Load-Line Analysis, The similarities with the output circuit of the emitter-biased configuration result in, the same intersections for the load line of the voltage-divider configuration. The load, line will therefore have the same appearance as that of Fig. 4.24, with, IC , , , , VCC, RC RE VCE0 V, , VCE VCCIC0 mA, , and, , (4.39), (4.40), , The level of IB is of course determined by a different equation for the voltage-divider, bias and the emitter-bias configurations., 164, , Chapter 4, , DC Biasing—BJTs
Page 176 :
4.6 DC BIAS WITH VOLTAGE FEEDBACK, An improved level of stability can also be obtained by introducing a feedback path, from collector to base as shown in Fig. 4.34. Although the Q-point is not totally independent of beta (even under approximate conditions), the sensitivity to changes in, beta or temperature variations is normally less than encountered for the fixed-bias or, emitter-biased configurations. The analysis will again be performed by first analyzing the base–emitter loop with the results applied to the collector–emitter loop., , Base–Emitter Loop, Figure 4.35 shows the base–emitter loop for the voltage feedback configuration. Writing Kirchhoff’s voltage law around the indicated loop in the clockwise direction will, result in, VCC I CRC IBRB VBE IERE 0, VCC, , +, , RC, , –, , I C', vo, RB, , IC, , IB, , C2, , +, , vi, , RB, VCC, , RC, I C', IC, , IB, , +, , VCE, , –, , C1, , +–, , VBE, , IE, , –, +, , IE, RE, , RE, , –, Figure 4.35 Base–emitter loop for the, network of Fig. 4.34., , Figure 4.34 dc bias circuit with voltage feedback., , It is important to note that the current through RC is not IC but I C (where I C , IC IB). However, the level of IC and IC far exceeds the usual level of IB and the approximation I C IC is normally employed. Substituting I C IC IB and IE IC, will result in, VCC IBRC IBRB VBE IBRE 0, Gathering terms, we have, VCC VBE IB(RC RE) IBRB 0, and solving for IB yields, IB , , VCC VBE, RB (RC RE), , (4.41), , The result is quite interesting in that the format is very similar to equations for IB, obtained for earlier configurations. The numerator is again the difference of available, voltage levels, while the denominator is the base resistance plus the collector and emitter resistors reflected by beta. In general, therefore, the feedback path results in a reflection of the resistance RC back to the input circuit, much like the reflection of RE., In general, the equation for IB has had the following format:, IB , , V, RB R, 4.6 DC Bias with Voltage Feedback, , 165
Page 177 :
with the absence of R for the fixed-bias configuration, R RE for the emitter-bias, setup (with ( 1) ), and R RC RE for the collector-feedback arrangement., The voltage V is the difference between two voltage levels., Since IC IB,, , V, RB R, , ICQ , , In general, the larger R is compared to RB, the less the sensitivity of ICQ to variations in beta. Obviously, if R RB and RB R R , then, ICQ , , I'C, , and ICQ is independent of the value of beta. Since R is typically larger for the voltagefeedback configuration than for the emitter-bias configuration, the sensitivity to variations in beta is less. Of course, R is zero ohms for the fixed-bias configuration and, is therefore quite sensitive to variations in beta., , +, RC, , Collector–Emitter Loop, , –, IC, , +, , The collector–emitter loop for the network of Fig. 4.34 is provided in Fig. 4.36. Applying Kirchhoff’s voltage law around the indicated loop in the clockwise direction, will result in, , VCC, , IERE VCE I CRC VCC 0, , VCE, , IE, , V, V, V, , , RB R, R, R, , –, +, , Since I C IC and IE IC, we have, IC (RC RE) VCE VCC 0, , RE, , –, , VCE VCC IC (RC RE), , and, , (4.42), , which is exactly as obtained for the emitter-bias and voltage-divider bias configurations., , Figure 4.36 Collector–emitter, loop for the network of Fig. 4.34., , EXAMPLE 4.11, , Determine the quiescent levels of ICQ and VCEQ for the network of Fig. 4.37., , Solution, Eq. (4.41):, , IB , , , 10 V, , , , 4.7 kΩ, 250 kΩ, , β = 90, , vi, , 10 V 0.7 V, (90)(4.7 k 1.2 k ), , 250 k, 250 k, , 9.3 V, 531 k, , , , 9.3 V, 781 k, , 11.91 A, , vo, 10 µF, , VCC VBE, RB (RC RE), , ICQ IB (90)(11.91 A), 1.07 mA, , 10 µF, , VCEQ VCC IC (RC RE), 1.2 kΩ, , 10 V (1.07 mA)(4.7 k, 10 V 6.31 V, 3.69 V, , Figure 4.37 Network for Example 4.11., , 166, , Chapter 4, , DC Biasing—BJTs, , 1.2 k )
Page 178 :
Repeat Example 4.11 using a beta of 135 (50% more than Example 4.11)., , EXAMPLE 4.12, , Solution, It is important to note in the solution for IB in Example 4.11 that the second term in, the denominator of the equation is larger than the first. Recall in a recent discussion, that the larger this second term is compared to the first, the less the sensitivity to, changes in beta. In this example the level of beta is increased by 50%, which will increase the magnitude of this second term even more compared to the first. It is more, important to note in these examples, however, that once the second term is relatively, large compared to the first, the sensitivity to changes in beta is significantly less., Solving for IB gives, IB , , VCC VBE, , RB (RC RE), 10 V 0.7 V, (135)(4.7 k 1.2 k ), , 250 k, , , 250 k, , 9.3 V, 796.5 k, , , , 9.3 V, 1046.5 k, , 8.89 A, ICQ IB, , and, , (135)(8.89 A), 1.2 mA, and, , VCEQ VCC IC (RC RE), 10 V (1.2 mA)(4.7 k, , 1.2 k ), , 10 V 7.08 V, 2.92 V, Even though the level of increased 50%, the level of ICQ only increased 12.1%, while the level of VCEQ decreased about 20.9%. If the network were a fixed-bias design, a 50% increase in would have resulted in a 50% increase in ICQ and a dramatic change in the location of the Q-point., Determine the dc level of IB and VC for the network of Fig. 4.38., , EXAMPLE 4.13, , 18 V, , 91 kΩ, , 110 kΩ, , 3.3 kΩ, 10 µF, vo, , R1, , R2, 10 µF, , 10 µF, , β = 75, , vi, , 510 Ω, , 50 µF, , Figure 4.38 Network for, Example 4.13., , 4.6 DC Bias with Voltage Feedback, , 167
Page 179 :
Solution, In this case, the base resistance for the dc analysis is composed of two resistors with, a capacitor connected from their junction to ground. For the dc mode, the capacitor, assumes the open-circuit equivalence and RB R1 R2., Solving for IB gives, IB , , , , VCC VBE, RB (RC RE), (91 k, , 18 V 0.7 V, 110 k ) (75)(3.3 k, , 201 k, , 17.3 V, 285.75 k, , , , 0.51 k ), , 17.3 V, 486.75 k, , 35.5 A, IC IB, (75)(35.5 A), 2.66 mA, VC VCC I CRC VCC ICRC, 18 V (2.66 mA)(3.3 k ), 18 V 8.78 V, 9.22 V, , Saturation Conditions, Using the approximation I C IC , the equation for the saturation current is the same, as obtained for the voltage-divider and emitter-bias configurations. That is,, ICsat ICmax , , VCC, RC RE, , (4.43), , Load-Line Analysis, Continuing with the approximation I C IC will result in the same load line defined, for the voltage-divider and emitter-biased configurations. The level of IBQ will be defined by the chosen bias configuration., , 4.7 MISCELLANEOUS BIAS, CONFIGURATIONS, There are a number of BJT bias configurations that do not match the basic mold of, those analyzed in the previous sections. In fact, there are variations in design that, would require many more pages than is possible in a book of this type. However, the, primary purpose here is to emphasize those characteristics of the device that permit, a dc analysis of the configuration and to establish a general procedure toward the desired solution. For each configuration discussed thus far, the first step has been the, derivation of an expression for the base current. Once the base current is known, the, collector current and voltage levels of the output circuit can be determined quite di168, , Chapter 4, , DC Biasing—BJTs
Page 180 :
rectly. This is not to imply that all solutions will take this path, but it does suggest a, possible route to follow if a new configuration is encountered., The first example is simply one where the emitter resistor has been dropped from, the voltage-feedback configuration of Fig. 4.34. The analysis is quite similar but does, require dropping RE from the applied equation., , EXAMPLE 4.14, , For the network of Fig. 4.39:, (a) Determine ICQ and VCEQ., (b) Find VB, VC, VE, and VBC., , Figure 4.39 Collector feedback, with RE 0 ., , Solution, (a) The absence of RE reduces the reflection of resistive levels to simply that of RC, and the equation for IB reduces to, IB , , , VCC VBE, RB RC, 20 V 0.7 V, 19.3 V, , 680 k (120)(4.7 k ), 1.244 M, , 15.51 A, ICQ IB (120)(15.51 A), 1.86 mA, VCEQ VCC ICRC, 20 V (1.86 mA)(4.7 k ), 11.26 V, VB VBE 0.7 V, VC VCE 11.26 V, VE 0 V, VBC VB VC 0.7 V 11.26 V, 10.56 V, In the next example, the applied voltage is connected to the emitter leg and RC is, connected directly to ground. Initially, it appears somewhat unorthodox and quite different from those encountered thus far, but one application of Kirchhoff’s voltage law, to the base circuit will result in the desired base current., 4.7 Miscellaneous Bias Configurations, , 169
Page 181 :
EXAMPLE 4.15, , Determine VC and VB for the network of Fig. 4.40., , Figure 4.40 Example 4.15, , Solution, Applying Kirchhoff’s voltage law in the clockwise direction for the base–emitter loop, will result in, IBRB VBE VEE 0, IB , , and, , VEE VBE, RB, , Substitution yields, IB , , , 9 V 0.7 V, 100 k, 8.3 V, 100 k, , 83 A, IC IB, (45)(83 A), 3.735 mA, VC ICRC, (3.735 mA)(1.2 k ), 4.48 V, VB IBRB, (83 A)(100 k ), 8.3 V, The next example employs a network referred to as an emitter-follower configuration. When the same network is analyzed on an ac basis, we will find that the output and input signals are in phase (one following the other) and the output voltage is, slightly less than the applied signal. For the dc analysis the collector is grounded and, the applied voltage is in the emitter leg., 170, , Chapter 4, , DC Biasing—BJTs
Page 182 :
EXAMPLE 4.16, , Determine VCEQ and IE for the network of Fig. 4.41., , Figure 4.41 Common-collector (emitter-follower) configuration., , Solution, Applying Kirchhoff’s voltage law to the input circuit will result in, IBRB VBE IERE VEE 0, but, , IE ( 1)IB, , and, , VEE VBE ( 1)IBRE IBRB 0, VEE VBE, IB , RB ( 1)RE, , with, , Substituting values yields, IB , , , 20 V 0.7 V, 240 k (91)(2 k ), 240 k, , 19.3 V, 182 k, , , , 19.3 V, 422 k, , 45.73 A, IC IB, (90)(45.73 A), 4.12 mA, Applying Kirchhoff’s voltage law to the output circuit, we have, VEE IERE VCE 0, but, and, , IE ( 1)IB, VCEQ VEE ( 1)IBRE, 20 V (91)(45.73 A)(2 k ), 11.68 V, IE 4.16 mA, , 4.7 Miscellaneous Bias Configurations, , 171
Page 183 :
All of the examples thus far have employed a common-emitter or commoncollector configuration. In the next example we investigate the common-base configuration. In this situation the input circuit will be employed to determine IE rather than, IB. The collector current is then available to perform an analysis of the output circuit., , EXAMPLE 4.17, , Determine the voltage VCB and the current IB for the common-base configuration of, Fig. 4.42., , Figure 4.42 Common-base configuration., , Solution, Applying Kirchhoff’s voltage law to the input circuit yields, VEE IERE VBE 0, IE , , and, , VEE VBE, RE, , Substituting values, we obtain, IE , , 4 V 0.7 V, 2.75 mA, 1.2 k, , Applying Kirchhoff’s voltage law to the output circuit gives, VCB ICRC VCC 0, and, , VCB VCC ICRC with IC IE, 10 V (2.75 mA)(2.4 k ), 3.4 V, IB , , , IC, , 2.75 mA, 60, , 45.8 A, Example 4.18 employs a split supply and will require the application of Thévenin’s, theorem to determine the desired unknowns., 172, , Chapter 4, , DC Biasing—BJTs
Page 185 :
+, , R Th, , –, , VB, , IB, E Th, , β = 120, , +, , 1.73 kΩ, , VBE, , 11.53 V, , –, RE, , E, , +, , 1.8 kΩ, , –, VEE = –20 V, , Figure 4.46 Substituting the, Thévenin equivalent circuit., , Substituting IE ( 1)IB gives, VEE ETh VBE ( 1)IBRE IBRTh 0, and, , IB , , VEE ETh VBE, RTh ( 1)RE, , , , 20 V 11.53 V 0.7 V, 1.73 k (121)(1.8 k ), , , , 7.77 V, 219.53 k, , 35.39 A, IC IB, (120)(35.39 A), 4.25 mA, VC VCC ICRC, 20 V (4.25 mA)(2.7 k ), 8.53 V, VB ETh IBRTh, (11.53 V) (35.39 A)(1.73 k ), 11.59 V, , 4.8 DESIGN OPERATIONS, Discussions thus far have focused on the analysis of existing networks. All the elements are in place and it is simply a matter of solving for the current and voltage levels of the configuration. The design process is one where a current and/or voltage may, be specified and the elements required to establish the designated levels must be determined. This synthesis process requires a clear understanding of the characteristics, of the device, the basic equations for the network, and a firm understanding of the, basic laws of circuit analysis, such as Ohm’s law, Kirchhoff’s voltage law, and so on., In most situations the thinking process is challenged to a higher degree in the design, process than in the analysis sequence. The path toward a solution is less defined and, in fact may require a number of basic assumptions that do not have to be made when, simply analyzing a network., 174, , Chapter 4, , DC Biasing—BJTs
Page 186 :
The design sequence is obviously sensitive to the components that are already, specified and the elements to be determined. If the transistor and supplies are specified, the design process will simply determine the required resistors for a particular, design. Once the theoretical values of the resistors are determined, the nearest standard commercial values are normally chosen and any variations due to not using the, exact resistance values are accepted as part of the design. This is certainly a valid approximation considering the tolerances normally associated with resistive elements, and the transistor parameters., If resistive values are to be determined, one of the most powerful equations is, simply Ohm’s law in the following form:, Runk , , VR, IR, , (4.44), , In a particular design the voltage across a resistor can often be determined from specified levels. If additional specifications define the current level, Eq. (4.44) can then, be used to calculate the required resistance level. The first few examples will demonstrate how particular elements can be determined from specified levels. A complete, design procedure will then be introduced for two popular configurations., Given the device characteristics of Fig. 4.47a, determine VCC, RB, and RC for the fixedbias configuration of Fig. 4.47b., , EXAMPLE 4.19, , Figure 4.47 Example 4.19, , Solution, From the load line, , and, , with, , VCC 20 V, , , , IC , , VCC, RC, , RC , , VCC, 20 V, , 2.5 k, IC, 8 mA, , VCE 0 V, , IB , , VCC VBE, RB, , RB , , VCC VBE, IB, , , , 20 V 0.7 V, 19.3 V, , 40 A, 40 A, , 482.5 k, 4.8 Design Operations, , 175
Page 187 :
Standard resistor values:, RC 2.4 k, RB 470 k, Using standard resistor values gives, IB 41.1 A, which is well within 5% of the value specified., , EXAMPLE 4.20, , Given that ICQ 2 mA and VCEQ 10 V, determine R1 and RC for the network of, Fig. 4.48., , Figure 4.48 Example 4.20, , Solution, VE IERE ICRE, (2 mA)(1.2 k ) 2.4 V, VB VBE VE 0.7 V 2.4 V 3.1 V, VB , and, , R2VCC, 3.1 V, R1 R2, , (18 k )(18 V), 3.1 V, R1 18 k, 324 k, , 3.1R1 55.8 k, , 3.1R1 268.2 k, R1 , Eq. (4.44):, , RC , , VRC, IC, , , , 268.2 k, 3.1, , 86.52 k, , VCC VC, IC, , with, , VC VCE VE 10 V 2.4 V 12.4 V, , and, , RC , , 18 V 12.4V, 2mA, , 2.8 k, The nearest standard commercial values to R1 are 82 and 91 k . However, using, the series combination of standard values of 82 k and 4.7 k 86.7 k would result in a value very close to the design level., 176, , Chapter 4, , DC Biasing—BJTs
Page 189 :
For standard values:, RC 2.4 k, RE 1 k, RB 620 k, , The discussion to follow will introduce one technique for designing an entire circuit to operate at a specified bias point. Often the manufacturer’s specification (spec), sheets provide information on a suggested operating point (or operating region) for a, particular transistor. In addition, other system components connected to the given amplifier stage may also define the current swing, voltage swing, value of common supply voltage, and so on, for the design., In actual practice, many other factors may have to be considered that may affect, the selection of the desired operating point. For the moment we shall concentrate,, however, on determining the component values to obtain a specified operating point., The discussion will be limited to the emitter-bias and voltage-divider bias configurations, although the same procedure can be applied to a variety of other transistor circuits., , Design of a Bias Circuit with an Emitter, Feedback Resistor, Consider first the design of the dc bias components of an amplifier circuit having, emitter-resistor bias stabilization as shown in Fig. 4.50. The supply voltage and operating point were selected from the manufacturer’s information on the transistor used, in the amplifier., , Figure 4.50 Emitter-stabilized, bias circuit for design consideration., , The selection of collector and emitter resistors cannot proceed directly from, the information just specified. The equation that relates the voltages around the, collector–emitter loop has two unknown quantities present—the resistors RC and RE., At this point some engineering judgment must be made, such as the level of the emitter voltage compared to the applied supply voltage. Recall that the need for including a resistor from emitter to ground was to provide a means of dc bias stabilization, so that the change of collector current due to leakage currents in the transistor and, the transistor beta would not cause a large shift in the operating point. The emitter, resistor cannot be unreasonably large because the voltage across it limits the range of, voltage swing of the voltage from collector to emitter (to be noted when the ac re178, , Chapter 4, , DC Biasing—BJTs
Page 190 :
sponse is discussed). The examples examined in this chapter reveal that the voltage, from emitter to ground is typically around one-fourth to one-tenth of the supply voltage. Selecting the conservative case of one-tenth will permit calculating the emitter, resistor RE and the resistor RC in a manner similar to the examples just completed. In, the next example we perform a complete design of the network of Fig. 4.49 using the, criteria just introduced for the emitter voltage., Determine the resistor values for the network of Fig. 4.50 for the indicated operating, point and supply voltage., , EXAMPLE 4.22, , Solution, VE 110 VCC 110 (20 V) 2 V, RE , RC , , VE, V, 2V, E, 1 k, IE, IC, 2 mA, VRC, IC, , , , 20 V 10 V 2 V, 8V, VCC VCE VE, , , 2 mA, 2 mA, IC, , 4 k, IB , RB , , IC, 2 mA, , 13.33 A, 150, , VRB, IB, , , , 20 V 0.7 V 2 V, VCC VBE VE, , 13.33 A, IB, , 1.3 M, , Design of a Current-Gain-Stabilized, (Beta-Independent) Circuit, The circuit of Fig. 4.51 provides stabilization both for leakage and current gain (beta), changes. The four resistor values shown must be obtained for the specified operating, point. Engineering judgment in selecting a value of emitter voltage, VE, as in the previous design consideration, leads to a direct straightforward solution for all the resistor values. The design steps are all demonstrated in the next example., , Figure 4.51 Current-gainstabilized circuit for design, considerations., , 4.8 Design Operations, , 179
Page 191 :
EXAMPLE 4.23, , Determine the levels of RC, RE, R1, and R2 for the network of Fig. 4.51 for the operating point indicated., , Solution, VE 110 VCC 110 (20 V) 2 V, VE, V, 2V, E, 200 , IE, IC, 10 mA, VRC, V VCE VE, 10 V, 20 V 8 V 2 V, RC , CC, , , IC, 10 mA, IC, 10 mA, RE , , 1 k, VB VBE VE 0.7 V 2 V 2.7 V, The equations for the calculation of the base resistors R1 and R2 will require a little thought. Using the value of base voltage calculated above and the value of the supply voltage will provide one equation—but there are two unknowns, R1 and R2. An, additional equation can be obtained from an understanding of the operation of these, two resistors in providing the necessary base voltage. For the circuit to operate efficiently, it is assumed that the current through R1 and R2 should be approximately, equal and much larger than the base current (at least 101). This fact and the voltagedivider equation for the base voltage provide the two relationships necessary to determine the base resistors. That is,, , and, , RE, , R2 , , 1, 10, , VB , , R2, VCC, R1 R2, , Substitution yields, R2 , , 1, 10, , (80)(0.2 k ), , 1.6 k, VB 2.7 V , and, , 2.7R1 4.32 k, , (1.6 k )(20 V), R1 1.6 k, , 32 k, , 2.7R1 27.68 k, R1 10.25 k (use 10 k ), , 4.9 TRANSISTOR SWITCHING, NETWORKS, The application of transistors is not limited solely to the amplification of signals., Through proper design it can be used as a switch for computer and control applications. The network of Fig. 4.52a can be employed as an inverter in computer logic, circuitry. Note that the output voltage VC is opposite to that applied to the base or input terminal. In addition, note the absence of a dc supply connected to the base circuit. The only dc source is connected to the collector or output side and for computer, applications is typically equal to the magnitude of the “high” side of the applied, signal—in this case 5 V., 180, , Chapter 4, , DC Biasing—BJTs
Page 192 :
VCC = 5 V, , RC, , Vi, , 0.82 kΩ, , 5V, , VC, 5V, , VC, RB, h FE = 125, 68 kΩ, , 0V, , 0V, , t, , t, , (a), , I C (mA), 60 µA, 7, I C sat = 6.1 mA, , 50 µA, , 6, , 40 µA, , 5, 4, , 30 µA, , 3, , 20 µA, , 2, 10 µA, , 1, , I B = 0 µA, 0, , 1, ~ 0V, VCE sat =, , 2, , 3, ~ 0 mA, I CEO =, , 4, , 5, VCC = 5 V, , VCE, , (b), , Figure 4.52 Transistor inverter., , Proper design for the inversion process requires that the operating point switch, from cutoff to saturation along the load line depicted in Fig. 4.52b. For our purposes, we will assume that IC ICEO 0 mA when IB 0 A (an excellent approximation, in light of improving construction techniques), as shown in Fig. 4.52b. In addition,, we will assume that VCE VCEsat 0 V rather than the typical 0.1- to 0.3-V level., When Vi 5 V, the transistor will be “on” and the design must ensure that the, network is heavily saturated by a level of IB greater than that associated with the IB, curve appearing near the saturation level. In Fig. 4.52b, this requires that IB 50 A., The saturation level for the collector current for the circuit of Fig. 4.52a is defined by, ICsat , , VCC, RC, , (4.45), , 4.9 Transistor Switching Networks, , 181
Page 193 :
The level of IB in the active region just before saturation results can be approximated by the following equation:, ICsat, IBmax , dc, For the saturation level we must therefore ensure that the following condition is, satisfied:, IC, , IB , , sat, , (4.46), , dc, , For the network of Fig. 4.52b, when Vi 5 V, the resulting level of IB is the following:, 5 V 0.7 V, V 0.7 V, , 63 A, IB i, 68 k, RB, VCC, 5V, , RC, 0.82 k, , ICsat , , and, , 6.1 mA, , Testing Eq. (4.46) gives, IB 63 A , , ICsat, , dc, , , , 6.1 mA, 48.8 A, 125, , which is satisfied. Certainly, any level of IB greater than 60 A will pass through a, Q-point on the load line that is very close to the vertical axis., For Vi 0 V, IB 0 A, and since we are assuming that IC ICEO 0 mA, the, voltage drop across RC as determined by VRC ICRC 0 V, resulting in VC 5 V, for the response indicated in Fig. 4.52a., In addition to its contribution to computer logic, the transistor can also be employed as a switch using the same extremities of the load line. At saturation, the current IC is quite high and the voltage VCE very low. The result is a resistance level between the two terminals determined by, VCEsat, Rsat , ICsat, and depicted in Fig. 4.53., , C, , I Csat, C, , +, VCE sat, , –, , R ≅ 0Ω, , Figure 4.53 Saturation conditions and the resulting terminal, resistance., , E, , E, , Using a typical average value of VCEsat such as 0.15 V gives, Rsat , , VCEsat 0.15 V, , 24.6, ICsat, 6.1 mA, , which is a relatively low value and 0, kilohm range., 182, , Chapter 4, , DC Biasing—BJTs, , when placed in series with resistors in the
Page 194 :
Figure 4.54 Cutoff conditions, and the resulting terminal resistance., , For Vi 0 V, as shown in Fig. 4.54, the cutoff condition will result in a resistance, level of the following magnitude:, VCC, 5V, , , Rcutoff , ICEO, 0 mA, resulting in the open-circuit equivalence. For a typical value of ICEO 10 A, the, magnitude of the cutoff resistance is, 5V, VCC, , 500 k, 10, A, ICEO, which certainly approaches an open-circuit equivalence for many situations., Rcutoff , , Determine RB and RC for the transistor inverter of Fig. 4.55 if ICsat 10 mA., , EXAMPLE 4.24, , VCC = 10 V, Vi, , VC, , RC, 10 V, , 10 V, , 10 V, , VC, RB, Vi, 0V, , h FE = 250, , 0V, , 0V, t, , t, , Figure 4.55 Inverter for Example 4.24., , Solution, At saturation:, ICsat , 10 mA , , and, so that, , RC , , VCC, RC, 10 V, RC, , 10 V, 1k, 10 mA, , At saturation:, IB , , IC sat, 10 mA, , 40 A, dc, 250, , Choosing IB 60 A to ensure saturation and using, IB , , Vi 0.7 V, RB, 4.9 Transistor Switching Networks, , 183
Page 195 :
RB , , we obtain, , 10 V 0.7 V, Vi 0.7 V, , 155 k, 60 A, IB, , Choose RB 150 k , which is a standard value. Then, Vi 0.7 V, 10 V 0.7 V, , 62 A, 150 k, RB, ICsat, 40 A, IB 62 A , dc, , IB , and, , Therefore, use RB 150 k and RC 1 k., There are transistors that are referred to as switching transistors due to the speed, with which they can switch from one voltage level to the other. In Fig. 3.23c the periods of time defined as ts, td, tr, and tf are provided versus collector current. Their, impact on the speed of response of the collector output is defined by the collector, current response of Fig. 4.56. The total time required for the transistor to switch from, the “off” to the “on” state is designated as ton and defined by, ton tr td, , (4.47), , with td the delay time between the changing state of the input and the beginning of, a response at the output. The time element tr is the rise time from 10% to 90% of the, final value., , Transistor "on", , Transistor "off", , IC, 100%, 90%, , 10%, 0, , t, ts, , td, , tf, , tr, t on, , t off, , Figure 4.56 Defining the time intervals of a pulse waveform., , The total time required for a transistor to switch from the “on” to the “off” state, is referred to as toff and is defined by, toff ts tf, , (4.48), , where ts is the storage time and tf the fall time from 90% to 10% of the initial value., 184, , Chapter 4, , DC Biasing—BJTs
Page 196 :
For the general-purpose transistor of Fig. 3.23c at IC 10 mA, we find that, ts 120 ns, td 25 ns, tr 13 ns, and, , tf 12 ns, , so that, , ton tr td 13 ns 25 ns 38 ns, , and, , toff ts tf 120 ns 12 ns 132 ns, , Comparing the values above with the following parameters of a BSV52L switching, transistor reveals one of the reasons for choosing a switching transistor when the need, arises., ton 12 ns, , and, , toff 18 ns, , 4.10 TROUBLESHOOTING TECHNIQUES, The art of troubleshooting is such a broad topic that a full range of possibilities and, techniques cannot be covered in a few sections of a book. However, the practitioner, should be aware of a few basic maneuvers and measurements that can isolate the problem area and possibly identify a solution., Quite obviously, the first step in being able to troubleshoot a network is to fully, understand the behavior of the network and to have some idea of the expected voltage and current levels. For the transistor in the active region, the most important measurable dc level is the base-to-emitter voltage., For an “on” transistor, the voltage VBE should be in the neighborhood of, 0.7 V., The proper connections for measuring VBE appear in Fig. 4.57. Note that the positive (red) lead is connected to the base terminal for an npn transistor and the negative (black) lead to the emitter terminal. Any reading totally different from the expected level of about 0.7 V, such as 0, 4, or 12 V, or negative in value would be suspect, and the device or network connections should be checked. For a pnp transistor, the, same connections can be used but a negative reading should be expected., A voltage level of equal importance is the collector-to-emitter voltage. Recall from, the general characteristics of a BJT that levels of VCE in the neighborhood of 0.3 V, suggest a saturated device—a condition that should not exist unless being employed, in a switching mode. However:, For the typical transistor amplifier in the active region, VCE is usually about, 25% to 75% of VCC., For VCC 20 V, a reading of VCE of 1 to 2 V or 18 to 20 V as measured in Fig., 4.58 is certainly an uncommon result, and unless knowingly designed for this response, the design and operation should be investigated. If VCE 20 V (with VCC 20 V) at, least two possibilities exist—either the device (BJT) is damaged and has the, , Figure 4.57 Checking the dc, level of VBE., , Figure 4.58 Checking the dc, level of VCE., , 4.10 Troubleshooting Techniques, , 185
Page 197 :
characteristics of an open circuit between collector and emitter terminals or a connection in the collector–emitter or base–emitter circuit loop is open as shown in Fig., 4.59, establishing IC at 0 mA and VRC 0 V. In Fig. 4.59, the black lead of the voltmeter is connected to the common ground of the supply and the red lead to the bottom terminal of the resistor. The absence of a collector current and a resulting drop, across RC will result in a reading of 20 V. If the meter is connected to the collector, terminal of the BJT, the reading will be 0 V since VCC is blocked from the active device by the open circuit. One of the most common errors in the laboratory experience, is the use of the wrong resistance value for a given design. Imagine the impact of using a 680- resistor for RB rather than the design value of 680 k . For VCC 20 V, and a fixed-bias configuration, the resulting base current would be, IB , Figure 4.59 Effect of a poor, connection or damaged device., , 20 V 0.7 V, 28.4 mA, 680, , Figure 4.60 Checking voltage, levels with respect to ground., , rather than the desired 28.4 A—a significant difference!, A base current of 28.4 mA would certainly place the design in a saturation region, and possibly damage the device. Since actual resistor values are often different from, the nominal color-code value (recall the common tolerance levels for resistive elements), it is time well spent to measure a resistor before inserting it in the network., The result is actual values closer to theoretical levels and some insurance that the correct resistance value is being employed., There are times when frustration will develop. You have checked the device on a, curve tracer or other BJT testing instrumentation and it looks good. All resistor levels seem correct, the connections appear solid, and the proper supply voltage has been, applied—what next? Now the troubleshooter must strive to attain a higher level of, sophistication. Could it be that the internal connection between the wire and the end, connection of a lead is faulty? How often has simply touching a lead at the proper, point created a “make or break” situation between connections? Perhaps the supply, was turned on and set at the proper voltage but the current-limiting knob was left in, the zero position, preventing the proper level of current as demanded by the network, design. Obviously, the more sophisticated the system, the broader the range of possibilities. In any case, one of the most effective methods of checking the operation of, a network is to check various voltage levels with respect to ground by hooking up the, black (negative) lead of a voltmeter to ground and “touching” the important terminals with the red (positive) lead. In Fig. 4.60, if the red lead is connected directly to, VCC, it should read VCC volts since the network has one common ground for the supply and network parameters. At VC the reading should be less, as determined by the, drop across RC and VE should be less than VC by the collector–emitter voltage VCE., The failure of any of these points to register what would appear to be a reasonable, level may be sufficient in itself to define the faulty connection or element. If VRC and, VRE are reasonable values but VCE is 0 V, the possibility exists that the BJT is damaged and displays a short-circuit equivalence between collector and emitter terminals., As noted earlier, if VCE registers a level of about 0.3 V as defined by VCE VC VE, (the difference of the two levels as measured above), the network may be in saturation with a device that may or may not be defective., It should be somewhat obvious from the discussion above that the voltmeter section of the VOM or DMM is quite important in the troubleshooting process. Current, levels are usually calculated from the voltage levels across resistors rather than “breaking” the network to insert the milliammeter section of a multimeter. On large schematics, specific voltage levels are provided with respect to ground for easy checking and, identification of possible problem areas. Of course, for the networks covered in this, chapter, one must simply be aware of typical levels within the system as defined by, the applied potential and general operation of the network., , 186, , Chapter 4, , DC Biasing—BJTs
Page 198 :
All in all, the troubleshooting process is a true test of your clear understanding of, the proper behavior of a network and the ability to isolate problem areas using a few, basic measurements with the appropriate instruments. Experience is the key, and that, will come only with continued exposure to practical circuits., , Based on the readings provided in Fig. 4.61, determine whether the network is operating properly and, if not, the probable cause., , EXAMPLE 4.25, , Figure 4.61 Network for Example 4.25., , Solution, The 20 V at the collector immediately reveals that IC 0 mA, due to an open circuit, or a nonoperating transistor. The level of VRB 19.85 V also reveals that the transistor is “off ” since the difference of VCC VRB 0.15 V is less than that required to, turn “on” the transistor and provide some voltage for VE. In fact, if we assume a short, circuit condition from base to emitter, we obtain the following current through RB:, IRB , , VCC, 20 V, , 79.4 A, RB RE, 252 k, , which matches that obtained from, IRB , , VRB, 19.85 V, , 79.4 A, RB, 250 k, , If the network were operating properly, the base current should be, IB , , VCC VBE, 20 V 0.7 V, 19.3 V, , , 42.7 A, RB ( 1)RE, 250 k (101)(2 k ), 452 k, , The result, therefore, is that the transistor is in a damaged state, with a short-circuit, condition between base and emitter., , Based on the readings appearing in Fig. 4.62, determine whether the transistor is “on”, and the network is operating properly., 4.10 Troubleshooting Techniques, , EXAMPLE 4.26, , 187
Page 199 :
Solution, Based on the resistor values of R1 and R2 and the magnitude of VCC, the voltage, VB 4 V seems appropriate (and in fact it is). The 3.3 V at the emitter results in a, 0.7-V drop across the base-to-emitter junction of the transistor, suggesting an “on”, transistor. However, the 20 V at the collector reveals that IC 0 mA, although the, connection to the supply must be “solid” or the 20 V would not appear at the collector of the device. Two possibilities exist—there can be a poor connection between, RC and the collector terminal of the transistor or the transistor has an open base-tocollector junction. First, check the continuity at the collector junction using an ohmmeter, and if okay, the transistor should be checked using one of the methods described, in Chapter 3., , Figure 4.62 Network for, Example 4.26., , 4.11 PNP TRANSISTORS, The analysis thus far has been limited totally to npn transistors to ensure that the initial analysis of the basic configurations was as clear as possible and uncomplicated, by switching between types of transistors. Fortunately, the analysis of pnp transistors, follows the same pattern established for npn transistors. The level of IB is first determined, followed by the application of the appropriate transistor relationships to determine the list of unknown quantities. In fact, the only difference between the resulting equations for a network in which an npn transistor has been replaced by a pnp, transistor is the sign associated with particular quantities., As noted in Fig. 4.63, the double-subscript notation continues as normally defined. The current directions, however, have been reversed to reflect the actual conduction directions. Using the defined polarities of Fig. 4.63, both VBE and VCE will, be negative quantities., Applying Kirchhoff’s voltage law to the base–emitter loop will result in the following equation for the network of Fig. 4.63:, IERE VBE IBRB VCC 0, Substituting IE ( 1)IB and solving for IB yields, IB , , Figure 4.63 pnp transistor in an, emitter-stabilized configuration., , VCC VBE, RB 1)RE, , (4.49), , The resulting equation is the same as Eq. (4.17) except for the sign for VBE. However, in this case VBE 0.7 V and the substitution of values will result in the same, sign for each term of Eq. (4.49) as Eq. (4.17). Keep in mind that the direction of IB, is now defined opposite of that for a pnp transistor as shown in Fig. 4.63., For VCE Kirchhoff’s voltage law is applied to the collector–emitter loop, resulting in the following equation:, IERE VCE ICRC VCC 0, Substituting IE IC gives, VCE VCC IC(RC RE), , (4.50), , The resulting equation has the same format as Eq. (4.19), but the sign in front of, each term on the right of the equal sign has changed. Since VCC will be larger than, the magnitude of the succeeding term, the voltage VCE will have a negative sign, as, noted in an earlier paragraph., 188, , Chapter 4, , DC Biasing—BJTs
Page 200 :
Determine VCE for the voltage-divider bias configuration of Fig. 4.64., , EXAMPLE 4.27, , –18 V, , 47 kΩ, , 2.4 kΩ, 10 µF, vo, , C, , 10 µF, , B, , vi, , +, VCE, , β = 120, , –, E, 10 kΩ, 1.1 kΩ, , Figure 4.64 pnp transistor in a, voltage-divider bias configuration., , Solution, Testing the condition, , RE, results in, , (120)(1.1 k ), 132 k, , 10R2, 10(10 k ), 100 k, , (satisfied), , Solving for VB, we have, VB , , (10 k )(18 V), R2VCC, , 3.16 V, 47 k 10 k, R1 R2, , Note the similarity in format of the equation with the resulting negative voltage for, VB., Applying Kirchhoff’s voltage law around the base–emitter loop yields, VB VBE VE 0, VE VB VBE, , and, Substituting values, we obtain, , VE 3.16 V (0.7 V), 3.16 V 0.7 V, 2.46 V, Note in the equation above that the standard single- and double-subscript notation is, employed. For an npn transistor the equation VE VB VBE would be exactly the, same. The only difference surfaces when the values are substituted., The current, IE , , VE, 2.46 V, , 2.24 mA, RE, 1.1 k, , For the collector–emitter loop:, IERE VCE ICRC VCC 0, Substituting IE IC and gathering terms, we have, VCE VCC IC(RC RE), 4.11 PNP Transistors, , 189
Page 201 :
Substituting values gives, VCE 18 V (2.24 mA)(2.4 k, , 1.1 k ), , 18 V 7.84 V, 10.16 V, , 4.12 BIAS STABILIZATION, The stability of a system is a measure of the sensitivity of a network to variations in, its parameters. In any amplifier employing a transistor the collector current IC is sensitive to each of the following parameters:, : increases with increase in temperature, VBE: decreases about 7.5 mV per degree Celsius (°C) increase in temperature, ICO (reverse saturation current): doubles in value for every 10°C increase in, temperature, Any or all of these factors can cause the bias point to drift from the designed point, of operation. Table 4.1 reveals how the level of ICO and VBE changed with increase, in temperature for a particular transistor. At room temperature (about 25°C) ICO , 0.1 nA, while at 100°C (boiling point of water) ICO is about 200 times larger at 20, nA. For the same temperature variation, increased from 50 to 80 and VBE dropped, from 0.65 to 0.48 V. Recall that IB is quite sensitive to the level of VBE, especially for, levels beyond the threshold value., , TABLE 4.1 Variation of Silicon Transistor, Parameters with Temperature, T (°C), 65, 25, 100, 175, , ICO (nA), , , , 0.2 103, 0.1, 20, 3.3 103, , 20, 50, 80, 120, , VBE(V), 0.85, 0.65, 0.48, 0.30, , The effect of changes in leakage current (ICO) and current gain () on the dc bias, point is demonstrated by the common-emitter collector characteristics of Fig. 4.65a, and b. Figure 4.65 shows how the transistor collector characteristics change from a, temperature of 25°C to a temperature of 100°C. Note that the significant increase in, leakage current not only causes the curves to rise but also an increase in beta, as revealed by the larger spacing between curves., An operating point may be specified by drawing the circuit dc load line on the, graph of the collector characteristic and noting the intersection of the load line and, the dc base current set by the input circuit. An arbitrary point is marked in Fig. 4.65a, at IB 30 A. Since the fixed-bias circuit provides a base current whose value depends approximately on the supply voltage and base resistor, neither of which is affected by temperature or the change in leakage current or beta, the same base current, magnitude will exist at high temperatures as indicated on the graph of Fig. 4.65b. As, the figure shows, this will result in the dc bias point’s shifting to a higher collector, current and a lower collector–emitter voltage operating point. In the extreme, the transistor could be driven into saturation. In any case, the new operating point may not, 190, , Chapter 4, , DC Biasing—BJTs
Page 202 :
Figure 4.65 Shift in dc bias point (Q-point) due to change in temperature:, (a) 25°C; (b) 100°C., , be at all satisfactory, and considerable distortion may result because of the bias-point, shift. A better bias circuit is one that will stabilize or maintain the dc bias initially, set, so that the amplifier can be used in a changing-temperature environment., , Stability Factors, S(ICO), S(VBE), and S(), A stability factor, S, is defined for each of the parameters affecting bias stability as, listed below:, S(ICO) , , IC, ICO, , (4.51), , S(VBE) , , IC, VBE, , (4.52), , IC, , , (4.53), , S() , , In each case, the delta symbol () signifies change in that quantity. The numerator of, each equation is the change in collector current as established by the change in the, quantity in the denominator. For a particular configuration, if a change in ICO fails to, produce a significant change in IC, the stability factor defined by S(ICO) IC/ICO, will be quite small. In other words:, Networks that are quite stable and relatively insensitive to temperature variations have low stability factors., In some ways it would seem more appropriate to consider the quantities defined, by Eqs. (4.51–4.53) to be sensitivity factors because:, 4.12 Bias Stabilization, , 191
Page 203 :
The higher the stability factor, the more sensitive the network to variations in, that parameter., The study of stability factors requires the knowledge of differential calculus. Our, purpose here, however, is to review the results of the mathematical analysis and to, form an overall assessment of the stability factors for a few of the most popular bias, configurations. A great deal of literature is available on this subject, and if time permits, you are encouraged to read more on the subject., S(ICO): EMITTER-BIAS CONFIGURATION, For the emitter-bias configuration, an analysis of the network will result in, S(ICO) ( 1), , 1 RB/RE, ( 1) RB/RE, , (4.54), , For RB/RE ( 1), Eq. (4.54) will reduce to the following:, S(ICO) 1, , (4.55), , as shown on the graph of S(ICO) versus RB/RE in Fig. 4.66., , Figure 4.66 Variation of stability factor S(ICO) with the resistor ratio RB /RE for the emitter-bias configuration., , For RB/RE 1, Eq. (4.54) will approach the following level (as shown in Fig., 4.66):, S(ICO) ( 1), , 1, →1, ( 1), , (4.56), , revealing that the stability factor will approach its lowest level as RE becomes sufficiently large. Keep in mind, however, that good bias control normally requires that, RB be greater than RE. The result therefore is a situation where the best stability levels are associated with poor design criteria. Obviously, a trade-off must occur that, will satisfy both the stability and bias specifications. It is interesting to note in Fig., 4.66 that the lowest value of S(ICO) is 1, revealing that IC will always increase at a, rate equal to or greater than ICO., For the range where RB/RE ranges between 1 and ( 1), the stability factor will, be determined by, S(ICO) , , 192, , Chapter 4, , DC Biasing—BJTs, , RB, RE, , (4.57)
Page 204 :
as shown in Fig. 4.66. The results reveal that the emitter-bias configuration is quite, stable when the ratio RB/RE is as small as possible and the least stable when the same, ratio approaches ( 1)., Calculate the stability factor and the change in IC from 25°C to 100°C for the transistor defined by Table 4.1 for the following emitter-bias arrangements., (a) RB/RE 250 (RB 250RE), (b) RB/RE 10 (RB 10RE)., (c) RB/RE 0.01 (RE 100RB)., , EXAMPLE 4.28, , Solution, RB/RE, 1 RB/RE, 251, 1 250, 51, 51, 301, 51 250, 42.53, which begins to approach the level defined by 1 51., , (a) S(ICO) ( 1) 1 , , , , , , , , IC [S(ICO)](ICO) (42.53)(19.9 nA), 0.85 A, 1 RB/RE, (b) S(ICO) ( 1), 1 RB/RE, 11, 1 10, 51, 51, 61, 51 10, 9.2, IC [S(ICO)]( ICO) (9.2)(19.9 nA), 0.18 A, 1 RB/RE, (c) S(ICO) ( 1), 1 RB/RE, 1 0.01, 1.01, 51, 51, 51 0.01, 51.01, 1.01, , , , , , , , , , , , , , , , which is certainly very close to the level of 1 forecast if RB/RE 1., IC [S(ICO)]( ICO) 1.01(19.9 nA), 20.1 nA, Example 4.28 reveals how lower and lower levels of ICO for the modern-day BJT, transistor have improved the stability level of the basic bias configurations. Even, though the change in IC is considerably different in a circuit having ideal stability, (S 1) from one having a stability factor of 42.53, the change in IC is not that significant. For example, the amount of change in IC from a dc bias current set at, say,, 2 mA, would be from 2 to 2.085 mA in the worst case, which is obviously small, enough to be ignored for most applications. Some power transistors exhibit larger, leakage currents, but for most amplifier circuits the lower levels of ICO have had a, very positive impact on the stability question., FIXED-BIAS CONFIGURATION, For the fixed-bias configuration, if we multiply the top and bottom of Eq. (4.54), by RE and then plug in RE 0 , the following equation will result:, S(ICO) 1, , (4.58), , 4.12 Bias Stabilization, , 193
Page 205 :
Note that the resulting equation matches the maximum value for the emitter-bias, configuration. The result is a configuration with a poor stability factor and a high sensitivity to variations in ICO., , Voltage-Divider Bias Configuration, Recall from Section 4.5 the development of the Thévenin equivalent network appearing in Fig. 4.67, for the voltage-divider bias configuration. For the network of, Fig. 4.67, the equation for S(ICO) is the following:, S(ICO) ( 1), , Figure 4.67 Equivalent circuit, for the voltage-divider configuration., , 1 RTh/RE, ( 1) RTh/RE, , (4.59), , Note the similarities with Eq. (4.54), where it was determined that S(ICO) had its, lowest level and the network had its greatest stability when RE RB. For Eq. (4.59),, the corresponding condition is RE RTh or RTh/RE should be as small as possible., For the voltage-divider bias configuration, RTh can be much less than the corresponding RB of the emitter-bias configuration and still have an effective design., , Feedback-Bias Configuration (RE 5 0 ), In this case,, S(ICO) ( 1), , 1 RB/RC, ( 1) RB/RC, , (4.60), , Since the equation is similar in format to that obtained for the emitter-bias and voltage-divider bias configurations, the same conclusions regarding the ratio RB/RC can, be applied here also., , Physical Impact, Equations of the type developed above often fail to provide a physical sense for why, the networks perform as they do. We are now aware of the relative levels of stability, and how the choice of parameters can affect the sensitivity of the network, but without the equations it may be difficult for us to explain in words why one network is, more stable than another. The next few paragraphs attempt to fill this void through, the use of some of the very basic relationships associated with each configuration., For the fixed-bias configuration of Fig. 4.68a, the equation for the base current is, the following:, IB , , VCC VBE, RB, , with the collector current determined by, IC IB ( 1)ICO, , (4.61), , If IC as defined by Eq. (4.61) should increase due to an increase in ICO, there is, nothing in the equation for IB that would attempt to offset this undesirable increase, in current level (assuming VBE remains constant). In other words, the level of IC would, continue to rise with temperature, with IB maintaining a fairly constant value—a very, unstable situation., For the emitter-bias configuration of Fig. 4.68b, however, an increase in IC due, to an increase in ICO will cause the voltage VE IERE ICRE to increase. The result, is a drop in the level of IB as determined by the following equation:, 194, , Chapter 4, , DC Biasing—BJTs
Page 206 :
Figure 4.68 Review of biasing, managements and the stability, factor S(ICO)., , IB ↓ , , VCC VBE VE ↑, RB, , (4.62), , A drop in IB will have the effect of reducing the level of IC through transistor action and thereby offset the tendency of IC to increase due to an increase in temperature. In total, therefore, the configuration is such that there is a reaction to an increase, in IC that will tend to oppose the change in bias conditions., The feedback configuration of Fig. 4.68c operates in much the same way as the, emitter-bias configuration when it comes to levels of stability. If IC should increase, due to an increase in temperature, the level of VRC will increase in the following equation:, VCC VBE VRC ↑, (4.63), IB ↓ , RB, and the level of IB will decrease. The result is a stabilizing effect as described for the, emitter-bias configuration. One must be aware that the action described above does, not happen in a step-by-step sequence. Rather, it is a simultaneous action to maintain, the established bias conditions. In other words, the very instant IC begins to rise, the network will sense the change and the balancing effect described above will take, place., The most stable of the configurations is the voltage-divider bias network of Fig., 4.68d. If the condition RE 10R2 is satisfied, the voltage VB will remain fairly constant for changing levels of IC. The base-to-emitter voltage of the configuration is determined by VBE VB VE. If IC should increase, VE will increase as described, above, and for a constant VB the voltage VBE will drop. A drop in VBE will establish, a lower level of IB, which will try to offset the increased level of IC., S(VBE), The stability factor defined by, S(VBE) , , IC, VBE, , will result in the following equation for the emitter-bias configuration:, S(VBE) , Substituting RE 0, , , RB ( 1)RE, , (4.64), , as occurs for the fixed-bias configuration will result in, S(VBE) , , , RB, , (4.65), , 4.12 Bias Stabilization, , 195
Page 207 :
Equation (4.64) can be written in the following form:, S(VBE) , , /RE, RB/RE ( 1), , (4.66), , Substituting the condition ( 1) RB/RE will result in the following equation, for S(VBE):, S(VBE) , , /RE, /RE, 1, , , 1, , RE, , (4.67), , revealing that the larger the resistance RE, the lower the stability factor and the more, stable the system., , EXAMPLE 4.29, , Determine the stability factor S(VBE) and the change in IC from 25°C to 100°C for, the transistor defined by Table 4.1 for the following bias arrangements., (a) Fixed-bias with RB 240 k and 100., (b) Emitter-bias with RB 240 k , RE 1 k , and 100., (c) Emitter-bias with RB 47 k , RE 4.7 k , and 100., , Solution, , RB, 100, , 240 k, , (a) Eq. (4.65): S(VBE) , , 0.417 103, IC [S(VBE)](VBE), , and, , (0.417 103)(0.48 V 0.65 V), (0.417 103)(0.17 V), 70.9 A, (b) In this case, ( 1) 101 and RB/RE 240. The condition ( 1) RB/RE is, not satisfied, negating the use of Eq. (4.67) and requiring the use of Eq. (4.64)., Eq. (4.64):, , S(VBE) , , , , RB ( 1)RE, 240 k, , 100, (101)1 k, , , , 100, 341 k, , 0.293 103, which is about 30% less than the fixed-bias value due to the additional ( 1)RE, term in the denominator of the S(VBE) equation., IC [S(VBE)](VBE), (0.293103)(0.17 V), 50 A, (c) In this case,, ( 1) 101 , 196, , Chapter 4, , DC Biasing—BJTs, , RB, 47 k, , RE, 4.7 k, , 10 (satisfied)
Page 208 :
Eq. (4.67):, , S(VBE) , , , 1, RE, 1, 4.7 k, , 0.212 103, IC [S(VBE)](VBE), , and, , (0.212 103)(0.17 V), 36.04 A, In Example 4.29, the increase of 70.9 A will have some impact on the level of, ICQ. For a situation where ICQ 2 mA, the resulting collector current will increase to, ICQ 2 mA 70.9 A, 2.0709 mA, a 3.5% increase., For the voltage-divider configuration, the level of RB will be changed to RTh in Eq., (4.64) (as defined by Fig. 4.67). In Example 4.29, the use of RB 47 k is a questionable design. However, RTh for the voltage-divider configuration can be this level or, lower and still maintain good design characteristics. The resulting equation for S(VBE), for the feedback network will be similar to that of Eq. (4.64) with RE replaced by RC., S(), The last stability factor to be investigated is that of S(). The mathematical development is more complex than that encountered for S(ICO) and S(VBE), as suggested, by the following equation for the emitter-bias configuration:, S() , , IC1(1 RB/RE), IC, , , 1(1 2 RB/RE), , (4.68), , The notation IC1 and 1 is used to define their values under one set of network, conditions, while the notation 2 is used to define the new value of beta as established by such causes as temperature change, variation in for the same transistor,, or a change in transistors., Determine ICQ at a temperature of 100°C if ICQ 2 mA at 25°C. Use the transistor, described by Table 4.1, where 1 50 and 2 80, and a resistance ratio RB/RE of, 20., , Solution, Eq. (4.68):, , S() , , EXAMPLE 4.30, , IC1(1 RB/RE), , 1(1 2 RB/RE), (2 103)(1 20), 42 103, , , (50)(1 80 20), 5050, , 8.32 106, and, , IC [S()][], (8.32 106)(30), 0.25 mA, 4.12 Bias Stabilization, , 197
Page 209 :
In conclusion therefore the collector current changed from 2 mA at room temperature to 2.25 mA at 100°C, representing a change of 12.5%., The fixed-bias configuration is defined by S() IC1/1 and RB of Eq. (4.68) can, be replaced by RTh for the voltage-divider configuration., For the collector feedback configuration with RE 0 ,, S() , , IC1(RB RC), 1(RB RC(1 2)), , (4.69), , Summary, Now that the three stability factors of importance have been introduced, the total effect on the collector current can be determined using the following equation:, IC S(ICO)ICO S(VBE)VBE S(), , (4.70), , The equation may initially appear quite complex, but take note that each component is simply a stability factor for the configuration multiplied by the resulting change, in a parameter between the temperature limits of interest. In addition, the IC to be, determined is simply the change in IC from the level at room temperature., For instance, if we examine the fixed-bias configuration, Eq. (4.70) becomes the, following:, IC, , VBE 1 , (4.71), IC ( 1)ICO , 1, RB, after substituting the stability factors as derived in this section. Let us now use Table, 4.1 to find the change in collector current for a temperature change from 25°C (room, temperature) to 100°C (the boiling point of water). For this range the table reveals that, ICO 20 nA 0.1 nA 19.9 nA, VBE 0.48 V 0.65 V 0.17 V (note the sign), 80 50 30, , and, , Starting with a collector current of 2 mA with an RB of 240 k , the resulting, change in IC due to an increase in temperature of 75°C is the following:, IC (50 1)(19.9 nA) , , 2 mA, 50, (0.17 V) , (30), 50, 240 k, , 1.01 A 35.42 A 1200 A, 1.236 mA, which is a significant change due primarily to the change in . The collector current, has increased from 2 to 3.236 mA—but this was expected in the sense that we recognize from the content of this section that the fixed-bias configuration is the least, stable., If the more stable voltage-divider configuration were employed with a ratio, RTh/RE 2 and RE 4.7 k , then, S(ICO) 2.89,, and, , S(VBE) 0.2 103,, , IC (2.89)(19.9 nA) 0.2 103(0.17 V) 1.445 106(30), 57.51 nA 34 A 43.4 A, 0.077 mA, , 198, , S() 1.445 106, , Chapter 4, , DC Biasing—BJTs
Page 210 :
The resulting collector current is 2.077 mA, or essentially 2.1 mA, compared to, the 2.0 mA at 25°C. The network is obviously a great deal more stable than the fixedbias configuration, as mentioned in earlier discussions. In this case, S() did not override the other two factors and the effects of S(VBE) and S(ICO) were equally important. In fact, at higher temperatures, the effects of S(ICO) and S(VBE) will be greater, than S() for the device of Table 4.1. For temperatures below 25°C, IC will decrease, with increasingly negative temperature levels., The effect of S(ICO) in the design process is becoming a lesser concern because, of improved manufacturing techniques that continue to lower the level of ICO ICBO., It should also be mentioned that for a particular transistor the variation in levels of, ICBO and VBE from one transistor to another in a lot is almost negligible compared to, the variation in beta. In addition, the results of the analysis above support the fact that, for a good stabilized design:, The ratio RB/RE or RTh/RE should be as small as possible with due consideration to all aspects of the design, including the ac response., Although the analysis above may have been clouded by some of the complex, equations for some of the sensitivities, the purpose here was to develop a higher level, of awareness of the factors that go into a good design and to be more intimate with, the transistor parameters and their impact on the network’s performance. The analysis of the earlier sections was for idealized situations with nonvarying parameter values. We are now more aware of how the dc response of the design can vary with the, parameter variations of a transistor., , 4.13 PSPICE WINDOWS, Voltage-Divider Configuration, The results of Example 4.7 will now be verified using PSpice Windows. Using methods described in previous chapters, the network of Fig. 4.69 can be constructed. Recall that the transistor can be found in the EVAL.slb library, the dc source under, SOURCE.slb, and the resistor under ANALOG.slb. The capacitor will also appear, in the ANALOG.slb library. Three VIEWPOINTS appear in Fig. 4.69 as obtained, from the SPECIAL.slb library. The collector current will be sensed by the IPROBE, option, also appearing in the SPECIAL.slb library. Recall that a positive result is obtained for IPROBE if the direction of conventional current enters that side of the, symbol with the internal curve representing the scale of the meter. We will want to, set the value of beta for the transistor to match that of the example. This is accom-, , Figure 4.69 Applying, PSpice Windows to the, voltage-divider configuration of Example 4.7., , 4.13 PSpice Windows, , 199
Page 211 :
plished by clicking on the transistor symbol (to obtain the red outline) followed by, Edit-Model-Edit Instance Model (text) to obtain the Model Editor. Then Bf is, changed to 140 to match the value of Example 4.7. Click OK, and the network is set, up for the analysis., In this case, since we are only interested in the dc response, the Probe Setup under Analysis should enable Do not auto-run Probe. It will save us from having to, deal with the Probe response before viewing the output file or screen. The sequence, Analysis-Simulate will result in the dc levels appearing in Fig. 4.69, which closely, match those of Example 4.7. The collector-to-emitter voltage is 13.76 V 1.259 V, 12.5 V, versus 12.22 V of Example 4.7, and the collector current is 0.824 mA, versus 0.85 mA. Any differences are due to the fact that we are using an actual transistor with a host of parameters not considered in our analysis. Recall the difference in, beta from the specification value and the value obtained from the plot of the previous chapter., Since the voltage-divider network is one that is to have a low sensitivity to changes, in beta, let us return to the transistor and replace the beta of 140 with the default value, of 225.9 and examine the results. The analysis will result in the dc levels appearing, in Fig. 4.70, which are very close to those of Fig. 4.69., , Figure 4.70 Response obtained, after changing , from 140 to 255.9, for the network of, Figure 4.69., , The collector-to-emitter voltage is 13.69 V 1.266 V 12.42 V, which is very, close to that obtained with a much lower beta. The collector current is actually closer, to the hand-calculated level, 0.832 mA versus 0.85 mA. There is no question, therefore, that the voltage-divider configuration demonstrates a low sensitivity to changes, in beta. Recall, however, that the fixed-bias configuration was very sensitive to changes, in beta, and let us proceed with the same type of analysis for the fixed-bias configuration and compare notes., , Fixed-Bias Configuration, The fixed-bias configuration of Fig. 4.71 is from Example 4.1 to permit a comparison of results. Beta was set to 50 using the procedure described above. In this case,, we will use a VIEWPOINT to read the collector-to-emitter voltage and enable the, display of bias currents (using the icon with the large capital I). In addition, we will, inhibit the display of some bias currents using the icon with the smaller capital I and, the diode symbol. The final touch is to move some of the currents displayed to clean, up the presentation., 200, , Chapter 4, , DC Biasing—BJTs
Page 212 :
Figure 4.71 Fixed-bias configuration, with a of 50., , A PSpice analysis of the network will result in the levels appearing in Fig. 4.71., These are a close match with the hand-written solution, with the collector voltage at, 6.998 V versus 6.83 V, the collector current at 2.274 mA versus 2.35 mA, and the, base current at 47.23 A versus 47.08 A., Let us now test the sensitivity to changes in beta by changing to the default value, of 255.9. The results appear in Fig. 4.72. Note the dramatic drop in VC to 0.113 V, compared to 6.83 V and the significant rise in ID to 5.4 mA versus the solution of, 2.35 mA. The fixed-bias configuration is obviously very beta-sensitive., , Figure 4.72 Network of Figure 4.71, with a of 255.9., , 4.13, , PSpice Windows, , 201
Page 213 :
§ 4.3 Fixed-Bias Circuit, , PROBLEMS, , 1. For, (a), (b), (c), (d), (e), (f), , the fixed-bias configuration of Fig. 4.73, determine:, IBQ., ICQ., VCEQ., VC., VB., VE., , Figure 4.73 Problems 1, 4, 11,, 47, 51, 52, 53, , 2. Given the information appearing in Fig. 4.74, determine:, (a) IC., (b) RC., (c) RB., (d) VCE., , 12 V, IC, RC, RB, VC = 6 V, , +, , VCE β = 80, I B = 40 µA, , –, , 3. Given the information appearing in Fig. 4.75, determine:, (a) IC., (b) VCC., (c) ., (d) RB., , Figure 4.74 Problem 2, , Figure 4.75 Problem 3, , 4. Find the saturation current (ICsat) for the fixed-bias configuration of Fig. 4.73., * 5. Given the BJT transistor characteristics of Fig. 4.76:, (a) Draw a load line on the characteristics determined by E 21 V and RC 3 k for a fixedbias configuration., (b) Choose an operating point midway between cutoff and saturation. Determine the value of, RB to establish the resulting operating point., (c) What are the resulting values of ICQ and VCEQ?, (d) What is the value of at the operating point?, (e) What is the value of defined by the operating point?, (f) What is the saturation (ICsat) current for the design?, (g) Sketch the resulting fixed-bias configuration., (h) What is the dc power dissipated by the device at the operating point?, (i) What is the power supplied by VCC?, (j) Determine the power dissipated by the resistive elements by taking the difference between, the results of parts (h) and (i)., , 202, , Chapter 4, , DC Biasing—BJTs
Page 214 :
Figure 4.77 Problems 6, 9, 11,, 20, 24, 48, 51, 54, , Figure 4.76 Problems 5, 10, 19, 35, 36, , § 4.4 Emitter-Stabilized Bias Circuit, 6. For, (a), (b), (c), (d), (e), (f), , the emitter-stabilized bias circuit of Fig. 4.77, determine:, IBQ., ICQ., VCEQ., VC., VB., VE., , Figure 4.78 Problem 7, , 7. Given the information provided in Fig. 4.78, determine:, (a) RC., (b) RE., (c) RB., (d) VCE., (e) VB., 8. Given the information provided in Fig. 4.79, determine:, (a) ., (b) VCC., (c) RB., 9. Determine the saturation current (ICsat) for the network of Fig. 4.77., * 10. Using the characteristics of Fig. 4.76, determine the following for an emitter-bias configuration if a Q-point is defined at ICQ 4 mA and VCEQ 10 V., (a) RC if VCC 24 V and RE 1.2 k ., (b) at the operating point., (c) RB., (d) Power dissipated by the transistor., (e) Power dissipated by the resistor RC., Problems, , Figure 4.79 Problem 8, , 203
Page 215 :
* 11. (a) Determine IC and VCE for the network of Fig. 4.73., (b) Change to 135 and determine the new value of IC and VCE for the network of Fig. 4.73., (c) Determine the magnitude of the percent change in IC and VCE using the following equations:, %IC , , , , IC(part b) IC(part a), IC(part a), , 100%,, , %VCE , , , , VCE(part b) VCE(part a), 100%, VCE(part a), , , , (d) Determine IC and VCE for the network of Fig. 4.77., (e) Change to 150 and determine the new value of IC and VCE for the network of Fig. 4.77., (f) Determine the magnitude of the percent change in IC and VCE using the following equations:, %IC , , , , IC(part e) IC(part d), 100%,, IC(part d), , , , %VCE , , , , VCE(part e) VCE(part d), 100%, VCE(part d), , , , (g) In each of the above, the magnitude of was increased 50%. Compare the percent change, in IC and VCE for each configuration, and comment on which seems to be less sensitive to, changes in ., , § 4.5 Voltage-Divider Bias, 12. For, (a), (b), (c), (d), (e), (f), , the voltage-divider bias configuration of Fig. 4.80, determine:, IBQ., ICQ., VCEQ., VC., VE., VB., , 13. Given the information provided in Fig. 4.81, determine:, (a) IC., (b) VE., (c) VB., (d) R1., 14. Given the information appearing in Fig. 4.82, determine:, (a) IC., (b) VE., (c) VCC., (d) VCE., (e) VB., (f) R1., , Figure 4.80 Problems 12, 15,, 18, 20, 24, 49, 51, 52, 55, , 204, , Figure 4.81 Problem 13, , Chapter 4, , DC Biasing—BJTs, , Figure 4.82 Problem 14
Page 216 :
15. Determine the saturation current (ICsat) for the network of Fig. 4.80., * 16. Determine the following for the voltage-divider configuration of Fig. 4.83 using the approximate approach if the condition established by Eq. (4.33) is satisfied., (a) IC., (b) VCE., (c) IB., (d) VE., (e) VB., * 17. Repeat Problem 16 using the exact (Thévenin) approach and compare solutions. Based on the, results, is the approximate approach a valid analysis technique if Eq. (4.33) is satisfied?, 18. (a) Determine ICQ, VCEQ, and IBQ for the network of Problem 12 (Fig. 4.80) using the approximate approach even though the condition established by Eq. (4.33) is not satisfied., (b) Determine ICQ, VCEQ, and IBQ using the exact approach., (c) Compare solutions and comment on whether the difference is sufficiently large to require, standing by Eq. (4.33) when determining which approach to employ., * 19. (a) Using the characteristics of Fig. 4.76, determine RC and RE for a voltage-divider network, having a Q-point of ICQ 5 mA and VCEQ 8 V. Use VCC 24 V and RC 3RE., (b) Find VE., (c) Determine VB., (d) Find R2 if R1 24 k assuming that RE 10R2., (e) Calculate at the Q-point., (f) Test Eq. (4.33), and note whether the assumption of part (d) is correct., , Figure 4.83 Problems 16, 17,, 21, , * 20. (a) Determine IC and VCE for the network of Fig. 4.80., (b) Change to 120 (50% increase), and determine the new values of IC and VCE for the network of Fig. 4.80., (c) Determine the magnitude of the percent change in IC and VCE using the following equations:, %IC , , , , IC(part b) IC(part a), 100%,, IC(part a), , , , %VCE , , , , VCE(part b) VCE(part a), 100%, VCE(part a), , , , (d) Compare the solution to part (c) with the solutions obtained for parts (c) and (f ) of Problem 11. If not performed, note the solutions provided in Appendix E., (e) Based on the results of part (d), which configuration is least sensitive to variations in ?, * 21. (a) Repeat parts (a) through (e) of Problem 20 for the network of Fig. 4.83. Change to 180, in part (b)., (b) What general conclusions can be made about networks in which the condition RE 10R2, is satisfied and the quantities IC and VCE are to be determined in response to a change in ?, , § 4.6 DC Bias with Voltage Feedback, 22. For, (a), (b), (c), , the collector feedback configuration of Fig. 4.84, determine:, IB., IC., VC., , 23. For, (a), (b), (c), (d), , the voltage feedback network of Fig. 4.85, determine:, IC., VC., VE., VCE., , Figure 4.84 Problems 22, 50,, 56, , Figure 4.85 Problem 23, , Problems, , 205
Page 217 :
* 24. (a) Determine the level of IC and VCE for the network of Fig. 4.86., (b) Change to 135 (50% increase), and calculate the new levels of IC and VCE., (c) Determine the magnitude of the percent change in IC and VCE using the following equations:, %IC , , , , IC(part b) IC(part a), 100%,, IC(part a), , , , %VCE , , , , VCE(part b) VCE(part a), VCE(part a), , 100%, , (d) Compare the results of part (c) with those of Problems 11(c), 11(f ), and 20(c). How does, the collector-feedback network stack up against the other configurations in sensitivity to, changes in ?, 25. Determine the range of possible values for VC for the network of Fig. 4.87 using the 1-M, tentiometer., * 26. Given VB 4 V for the network of Fig. 4.88, determine:, (a) VE., (b) IC., (c) VC., (d) VCE., (e) IB., (f) ., , Figure 4.87 Problem 25, , Figure 4.86 Problem 24, , Figure 4.88 Problem 26, , § 4.7 Miscellaneous Bias Configurations, 27. Given VC 8 V for the network of Fig. 4.89, determine:, (a) IB., (b) IC., (c) ., (d) VCE., * 28. For, (a), (b), (c), (d), , the network of Fig. 4.90, determine:, IB., IC., VCE., VC., , Figure 4.90 Problem 28, , Figure 4.89 Problem 27, , 206, , Chapter 4, , DC Biasing—BJTs, , po-
Page 218 :
* 29. For, (a), (b), (c), (d), , the network of Fig. 4.91, determine:, IB., IC., VE., VCE., , * 30. Determine the level of VE and IE for the network of Fig. 4.92., * 31. For the network of Fig. 4.93, determine:, (a) IE., (b) VC., (c) VCE., , –, , 2.2 kΩ, , 8V, , –, , VCE, , +, , VC, , IE, 1.8 kΩ, 10 V, , Figure 4.92 Problem 30, , Figure 4.91 Problem 29, , Figure 4.93 Problem 31, , § 4.8 Design Operations, 32. Determine RC and RB for a fixed-bias configuration if VCC 12 V, 80, and ICQ 2.5 mA, with VCEQ 6 V. Use standard values., 33. Design an emitter-stabilized network at ICQ 21 ICsat and VCEQ 12 VCC. Use VCC 20 V, ICsat , 10 mA, 120, and RC 4RE. Use standard values., 34. Design a voltage-divider bias network using a supply of 24 V, a transistor with a beta of 110,, and an operating point of ICQ 4 mA and VCEQ 8 V. Choose VE 18 VCC. Use standard values., * 35. Using the characteristics of Fig. 4.76, design a voltage-divider configuration to have a saturation level of 10 mA and a Q-point one-half the distance between cutoff and saturation. The, available supply is 28 V, and VE is to be one-fifth of VCC. The condition established by Eq., (4.33) should also be met to provide a high stability factor. Use standard values., , § 4.9 Transistor Switching Networks, * 36. Using the characteristics of Fig. 4.76, determine the appearance of the output waveform for the, network of Fig. 4.94. Include the effects of VCEsat, and determine IB, IBmax, and ICsat when Vi , 10 V. Determine the collector-to-emitter resistance at saturation and cutoff., * 37. Design the transistor inverter of Fig. 4.95 to operate with a saturation current of 8 mA using a, transistor with a beta of 100. Use a level of IB equal to 120% of IBmax and standard resistor values., 10 V, 2.4 kΩ, , Vi, , 5V, RC, , Vi, , Vo, , 10 V, , 180 kΩ, , Vo, , 5V, , Vi, , RB, Vi, , 0V, t, , Figure 4.94 Problem 36, , β = 100, , 0V, t, , Figure 4.95 Problem 37, , Problems, , 207
Page 219 :
38. (a) Using the characteristics of Fig. 3.23c, determine ton and toff at a current of 2 mA. Note, the use of log scales and the possible need to refer to Section 11.2., (b) Repeat part (a) at a current of 10 mA. How have ton and toff changed with increase in collector current?, (c) For parts (a) and (b), sketch the pulse waveform of Fig. 4.56 and compare results., , § 4.10 Troubleshooting Techniques, * 39. The measurements of Fig. 4.96 all reveal that the network is not functioning correctly. List as, many reasons as you can for the measurements obtained., , Figure 4.96 Problem 39, , * 40. The measurements appearing in Fig. 4.97 reveal that the networks are not operating properly., Be specific in describing why the levels obtained reflect a problem with the expected network, behavior. In other words, the levels obtained reflect a very specific problem in each case., , 16 V, , 16 V, , 3.6 kΩ, , 91 kΩ, VB = 9.4 V, , β = 100, , 3.6 kΩ, , 91 kΩ, , β = 100, , 2.64 V, , 4V, 18 kΩ, 1.2 kΩ, , (a), , 18 kΩ, 1.2 kΩ, , (b), , Figure 4.97 Problem 40, , Figure 4.98 Problem 41, , 41. For, (a), (b), (c), (d), (e), , the circuit of Fig. 4.98:, Does VC increase or decrease if RB is increased?, Does IC increase or decrease if is reduced?, What happens to the saturation current if is increased?, Does the collector current increase or decrease if VCC is reduced?, What happens to VCE if the transistor is replaced by one with smaller ?, , 208, , Chapter 4, , DC Biasing—BJTs
Page 220 :
42. Answer the following questions about the circuit of Fig. 4.99., (a) What happens to the voltage VC if the transistor is replaced by one having a larger value, of ?, (b) What happens to the voltage VCE if the ground leg of resistor RB2 opens (does not connect, to ground)?, (c) What happens to IC if the supply voltage is low?, (d) What voltage VCE would occur if the transistor base–emitter junction fails by becoming, open?, (e) What voltage VCE would result if the transistor base–emitter junction fails by becoming a, short?, , Figure 4.99 Problem 42, , * 43. Answer the following questions about the circuit of Fig. 4.100., (a) What happens to the voltage VC if the resistor RB is open?, (b) What should happen to VCE if increases due to temperature?, (c) How will VE be affected when replacing the collector resistor with one whose resistance, is at the lower end of the tolerance range?, (d) If the transistor collector connection becomes open, what will happen to VE?, (e) What might cause VCE to become nearly 18 V?, , Figure 4.100 Problem 43, , § 4.11 PNP Transistors, 44. Determine VC, VCE, and IC for the network of Fig. 4.101., 45. Determine VC and IB for the network of Fig. 4.102., 46. Determine IE and VC for the network of Fig. 4.103., , Figure 4.101 Problem 44, , Figure 4.102 Problem 45, , Figure 4.103 Problem 46, , Problems, , 209
Page 221 :
§ 4.12 Bias Stabilization, 47. Determine the following for the network of Fig. 4.73., (a) S(ICO)., (b) S(VBE)., (c) S() using T1 as the temperature at which the parameter values are specified and (T2) as, 25% more than (T1)., (d) Determine the net change in IC if a change in operating conditions results in ICO increasing from 0.2 to 10 A, VBE drops from 0.7 to 0.5 V, and increases 25%., * 48. For, (a), (b), (c), , the network of Fig. 4.77, determine:, S(ICO)., S(VBE)., S() using T1 as the temperature at which the parameter values are specified and (T2) as, 25% more than (T1)., (d) Determine the net change in IC if a change in operating conditions results in ICO increasing from 0.2 to 10 A, VBE drops from 0.7 to 0.5 V, and increases 25%., , * 49. For, (a), (b), (c), , the network of Fig. 4.80, determine:, S(ICO)., S(VBE)., S() using T1 as the temperature at which the parameter values are specified and (T2) as, 25% more than (T1)., (d) Determine the net change in IC if a change in operating conditions results in ICO increasing from 0.2 to 10 A, VBE drops from 0.7 to 0.5 V, and increases 25%., , * 50. For, (a), (b), (c), , the network of Fig. 4.89, determine:, S(ICO)., S(VBE)., S() using T1 as the temperature at which the parameter values are specified and (T2) as, 25% more than (T1)., (d) Determine the net change in IC if a change in operating conditions results in ICO increasing from 0.2 to 10 A, VBE drops from 0.7 to 0.5 V, and increases 25%., , * 51. Compare the relative values of stability for Problems 47 through 50. The results for Exercises, 47 and 49 can be found in Appendix E. Can any general conclusions be derived from the results?, * 52. (a) Compare the levels of stability for the fixed-bias configuration of Problem 47., (b) Compare the levels of stability for the voltage-divider configuration of Problem 49., (c) Which factors of parts (a) and (b) seem to have the most influence on the stability of the, system, or is there no general pattern to the results?, , § 4.13 PSpice Windows, 53. Perform a PSpice analysis of the network of Fig. 4.73. That is, determine IC, VCE, band IB., 54. Repeat Problem 53 for the network of Fig. 4.77., 55. Repeat Problem 53 for the network of Fig. 4.80., 56. Repeat Problem 53 for the network of Fig. 4.84., *Please Note: Asterisks indicate more difficult problems., , 210, , Chapter 4, , DC Biasing—BJTs
Page 222 :
CHAPTER, , Field-Effect, Transistors, , 5, , 5.1 INTRODUCTION, The field-effect transistor (FET) is a three-terminal device used for a variety of applications that match, to a large extent, those of the BJT transistor described in Chapters 3 and 4. Although there are important differences between the two types of devices, there are also many similarities that will be pointed out in the sections to follow., The primary difference between the two types of transistors is the fact that the, BJT transistor is a current-controlled device as depicted in Fig. 5.1a, while the JFET, transistor is a voltage-controlled device as shown in Fig. 5.1b. In other words, the current IC in Fig. 5.1a is a direct function of the level of IB. For the FET the current I, will be a function of the voltage VGS applied to the input circuit as shown in Fig. 5.1b., In each case the current of the output circuit is being controlled by a parameter of the, input circuit—in one case a current level and in the other an applied voltage., , Figure 5.1 (a) Current-controlled and (b) voltage-controlled, amplifiers., , Just as there are npn and pnp bipolar transistors, there are n-channel and p-channel field-effect transistors. However, it is important to keep in mind that the BJT transistor is a bipolar device—the prefix bi- revealing that the conduction level is a function of two charge carriers, electrons and holes. The FET is a unipolar device, depending solely on either electron (n-channel) or hole (p-channel) conduction., The term field-effect in the chosen name deserves some explanation. We are all, familiar with the ability of a permanent magnet to draw metal filings to the magnet, without the need for actual contact. The magnetic field of the permanent magnet has, enveloped the filings and attracted them to the magnet through an effort on the part, of the magnetic flux lines to be as short as possible. For the FET an electric field is, established by the charges present that will control the conduction path of the output, 211
Page 223 :
Drs. Ian Munro Ross (front) and, G. C. Dacey jointly developed an, experimental procedure for measuring, the characteristics of a field-effect, transistor in 1955. (Courtesy of AT&T, Archives.), Dr. Ross Born: Southport, England, PhD Gonville and Caius, College, Cambridge, University President emeritus of AT&T Bell Labs Fellow—IEEE, Member of the, National Science Board, Chairman—National, Advisory Committee on, Semiconductors, Dr. Dacey Born: Chicago, Illinois, PhD California Institute, of Technology, Director of Solid-State, Electronics Research at, Bell Labs, Vice President, Research, at Sandia Corporation, Member IRE, Tau Beta Pi,, Eta Kappa Nu, , 212, , circuit without the need for direct contact between the controlling and controlled, quantities., There is a natural tendency when introducing a second device with a range of applications similar to one already introduced to compare some of the general characteristics of one versus the other. One of the most important characteristics of the FET, is its high input impedance. At a level of 1 to several hundred megohms it far exceeds, the typical input resistance levels of the BJT transistor configurations—a very important characteristic in the design of linear ac amplifier systems. On the other hand,, the BJT transistor has a much higher sensitivity to changes in the applied signal. In, other words, the variation in output current is typically a great deal more for BJTs, than FETs for the same change in applied voltage. For this reason, typical ac voltage, gains for BJT amplifiers are a great deal more than for FETs. In general, FETs are, more temperature stable than BJTs, and FETs are usually smaller in construction than, BJTs, making them particularly useful in integrated-circuit (IC) chips. The construction characteristics of some FETs, however, can make them more sensitive to handling than BJTs., Two types of FETs will be introduced in this chapter: the junction field-effect, transistor (JFET) and the metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET category is further broken down into depletion and enhancement, types, which are both described. The MOSFET transistor has become one of the most, important devices used in the design and construction of integrated circuits for digital computers. Its thermal stability and other general characteristics make it extremely popular in computer circuit design. However, as a discrete element in a typical top-hat container, it must be handled with care (to be discussed in a later, section)., Once the FET construction and characteristics have been introduced, the biasing, arrangements will be covered in Chapter 6. The analysis performed in Chapter 4 using BJT transistors will prove helpful in the derivation of the important equations and, understanding the results obtained for FET circuits., , 5.2 CONSTRUCTION AND, CHARACTERISTICS OF JFETs, As indicated earlier, the JFET is a three-terminal device with one terminal capable of, controlling the current between the other two. In our discussion of the BJT transistor, the npn transistor was employed through the major part of the analysis and design, sections, with a section devoted to the impact of using a pnp transistor. For the JFET, transistor the n-channel device will appear as the prominent device, with paragraphs, and sections devoted to the impact of using a p-channel JFET., The basic construction of the n-channel JFET is shown in Fig. 5.2. Note that the, major part of the structure is the n-type material that forms the channel between the, embedded layers of p-type material. The top of the n-type channel is connected through, an ohmic contact to a terminal referred to as the drain (D), while the lower end of, the same material is connected through an ohmic contact to a terminal referred to as, the source (S). The two p-type materials are connected together and to the gate (G), terminal. In essence, therefore, the drain and source are connected to the ends of the, n-type channel and the gate to the two layers of p-type material. In the absence of, any applied potentials the JFET has two p-n junctions under no-bias conditions. The, result is a depletion region at each junction as shown in Fig. 5.2 that resembles the, same region of a diode under no-bias conditions. Recall also that a depletion region, is that region void of free carriers and therefore unable to support conduction through, the region., Chapter 5, , Field-Effect Transistors
Page 224 :
Figure 5.2 Junction field-effect, transistor (JFET)., , Analogies are seldom perfect and at times can be misleading, but the water analogy of Fig. 5.3 does provide a sense for the JFET control at the gate terminal and the, appropriateness of the terminology applied to the terminals of the device. The source, of water pressure can be likened to the applied voltage from drain to source that will, establish a flow of water (electrons) from the spigot (source). The “gate,” through an, applied signal (potential), controls the flow of water (charge) to the “drain.” The drain, and source terminals are at opposite ends of the n-channel as introduced in Fig. 5.2, because the terminology is defined for electron flow., Figure 5.3 Water analogy for, the JFET control mechanism., , VGS 0 V, VDS Some Positive Value, In Fig. 5.4, a positive voltage VDS has been applied across the channel and the gate, has been connected directly to the source to establish the condition VGS 0 V. The, result is a gate and source terminal at the same potential and a depletion region in the, low end of each p-material similar to the distribution of the no-bias conditions of Fig., 5.2. The instant the voltage VDD ( VDS) is applied, the electrons will be drawn to, the drain terminal, establishing the conventional current ID with the defined direction, of Fig. 5.4. The path of charge flow clearly reveals that the drain and source currents, are equivalent (ID IS). Under the conditions appearing in Fig. 5.4, the flow of charge, is relatively uninhibited and limited solely by the resistance of the n-channel between, drain and source., ID, D, , +, , n-channel, , Depletion, region, , e, e, , G, , p, , +, , p, , n, , VDS, , VDD, , e, e, , VG S = 0 V, , –, , S, , IS, , –, Figure 5.4 JFET in the VGS , 0 V and VDS 0 V., , 5.2 Construction and Characteristics of JFETs, , 213
Page 225 :
Figure 5.5 Varying reverse-bias, potentials across the p-n junction, of an n-channel JFET., , Figure 5.6, , 214, , It is important to note that the depletion region is wider near the top of both ptype materials. The reason for the change in width of the region is best described, through the help of Fig. 5.5. Assuming a uniform resistance in the n-channel, the resistance of the channel can be broken down to the divisions appearing in Fig. 5.5. The, current ID will establish the voltage levels through the channel as indicated on the, same figure. The result is that the upper region of the p-type material will be reversebiased by about 1.5 V, with the lower region only reverse-biased by 0.5 V. Recall from, the discussion of the diode operation that the greater the applied reverse bias, the, wider the depletion region—hence the distribution of the depletion region as shown, in Fig. 5.5. The fact that the p-n junction is reverse-biased for the length of the channel results in a gate current of zero amperes as shown in the same figure. The fact, that IG 0 A is an important characteristic of the JFET., As the voltage VDS is increased from 0 to a few volts, the current will increase as, determined by Ohm’s law and the plot of ID versus VDS will appear as shown in Fig., 5.6. The relative straightness of the plot reveals that for the region of low values of, VDS, the resistance is essentially constant. As VDS increases and approaches a level, referred to as VP in Fig. 5.6, the depletion regions of Fig. 5.4 will widen, causing a, noticeable reduction in the channel width. The reduced path of conduction causes the, resistance to increase and the curve in the graph of Fig. 5.6 to occur. The more horizontal the curve, the higher the resistance, suggesting that the resistance is approaching “infinite” ohms in the horizontal region. If VDS is increased to a level where, it appears that the two depletion regions would “touch” as shown in Fig. 5.7, a condition referred to as pinch-off will result. The level of VDS that establishes this condition is referred to as the pinch-off voltage and is denoted by VP as shown in Fig., 5.6. In actuality, the term pinch-off is a misnomer in that it suggests the current ID is, pinched off and drops to 0 A. As shown in Fig. 5.6, however, this is hardly the, case — ID maintains a saturation level defined as IDSS in Fig. 5.6. In reality a very, small channel still exists, with a current of very high density. The fact that ID does, not drop off at pinch-off and maintains the saturation level indicated in Fig. 5.6 is, verified by the following fact: The absence of a drain current would remove the possibility of different potential levels through the n-channel material to establish the, varying levels of reverse bias along the p-n junction. The result would be a loss of, the depletion region distribution that caused pinch-off in the first place., , ID versus VDS for VGS 0 V., , Chapter 5, , Figure 5.7 Pinch-off (VGS 0 V, VDS VP)., , Field-Effect Transistors
Page 226 :
As VDS is increased beyond VP, the region of close encounter between the two, depletion regions will increase in length along the channel, but the level of ID remains, essentially the same. In essence, therefore, once VDS VP the JFET has the characteristics of a current source. As shown in Fig. 5.8, the current is fixed at ID IDSS,, but the voltage VDS (for levels VP) is determined by the applied load., The choice of notation IDSS is derived from the fact that it is the Drain-to-Source, current with a Short-circuit connection from gate to source. As we continue to investigate the characteristics of the device we will find that:, IDSS is the maximum drain current for a JFET and is defined by the conditions, VGS 0 V and VDS |VP|., Note in Fig. 5.6 that VGS 0 V for the entire length of the curve. The next few, paragraphs will describe how the characteristics of Fig. 5.6 are affected by changes, in the level of VGS., Figure 5.8 Current source, equivalent for VGS 0 V,, VDS VP., , VGS 0 V, The voltage from gate to source, denoted VGS, is the controlling voltage of the JFET., Just as various curves for IC versus VCE were established for different levels of IB for, the BJT transistor, curves of ID versus VDS for various levels of VGS can be developed, for the JFET. For the n-channel device the controlling voltage VGS is made more and, more negative from its VGS 0 V level. In other words, the gate terminal will be set, at lower and lower potential levels as compared to the source., In Fig. 5.9 a negative voltage of 1 V has been applied between the gate and, source terminals for a low level of VDS. The effect of the applied negative-bias VGS, is to establish depletion regions similar to those obtained with VGS 0 V but at lower, levels of VDS. Therefore, the result of applying a negative bias to the gate is to reach, the saturation level at a lower level of VDS as shown in Fig. 5.10 for VGS 1 V., The resulting saturation level for ID has been reduced and in fact will continue to decrease as VGS is made more and more negative. Note also on Fig. 5.10 how the pinchoff voltage continues to drop in a parabolic manner as VGS becomes more and more, negative. Eventually, VGS when VGS VP will be sufficiently negative to establish, a saturation level that is essentially 0 mA, and for all practical purposes the device, has been “turned off.” In summary:, , ID, D, , G, , +, , IG = 0 A, , p, , p, n, , >, , 0V, , –, , +, , VDS, , 1V, , +, VG S = –1 V, , –, , S, , IS, , –, Figure 5.9 Application of a, negative voltage to the gate of a, JFET., , 5.2 Construction and Characteristics of JFETs, , 215
Page 227 :
ID (mA), , Locus of pinch-off values, , Ohmic, Region, , Saturation Region, VGS = 0 V, , IDSS 8, 7, 6, 5, , VGS = –1 V, , 4, 3, VGS = –2 V, , 2, , VGS = –3 V, , 1, , VGS = – 4 V = VP, 0, , 10, 5, VP (for VGS = 0 V), , 15, , 20, , 25, , VDS (V), , Figure 5.10 n-Channel JFET characteristics with IDSS 8 mA and VP 4 V., , The level of VGS that results in ID 0 mA is defined by VGS VP, with VP, being a negative voltage for n-channel devices and a positive voltage for, p-channel JFETs., On most specification sheets the pinch-off voltage is specified as VGS(off) rather, than VP. A specification sheet will be reviewed later in the chapter when the primary, elements of concern have been introduced. The region to the right of the pinch-off, locus of Fig. 5.10 is the region typically employed in linear amplifiers (amplifiers, with minimum distortion of the applied signal) and is commonly referred to as the, constant-current, saturation, or linear amplification region., , Voltage-Controlled Resistor, The region to the left of the pinch-off locus of Fig. 5.10 is referred to as the ohmic, or voltage-controlled resistance region. In this region the JFET can actually be employed as a variable resistor (possibly for an automatic gain control system) whose, resistance is controlled by the applied gate-to-source voltage. Note in Fig. 5.10 that, the slope of each curve and therefore the resistance of the device between drain and, source for VDS VP is a function of the applied voltage VGS. As VGS becomes more, and more negative, the slope of each curve becomes more and more horizontal,, corresponding with an increasing resistance level. The following equation will provide a good first approximation to the resistance level in terms of the applied voltage, VGS., ro, rd , (1 VGS/VP)2, , (5.1), , where ro is the resistance with VGS 0 V and rd the resistance at a particular level, of VGS., For an n-channel JFET with ro equal to 10 k (VGS 0 V, VP 6 V), Eq. (5.1), will result in 40 k at VGS 3 V., , p-Channel Devices, The p-channel JFET is constructed in exactly the same manner as the n-channel device of Fig. 5.2, but with a reversal of the p- and n-type materials as shown in Fig. 5.11., 216, , Chapter 5, , Field-Effect Transistors
Page 228 :
ID, , D, , +, , +, +, IG = 0 A, , n, +, , n, , p, , VDS, , VDD, , –, , +, , +, , +, , +, , G, , +, , VGG, , –, VG S = + VGG, , –, , S, , IS, , –, , Figure 5.11 p-Channel JFET., , The defined current directions are reversed, as are the actual polarities for the voltages VGS and VDS. For the p-channel device, the channel will be constricted by increasing positive voltages from gate to source and the double-subscript notation for, VDS will result in negative voltages for VDS on the characteristics of Fig. 5.12, which, has an IDSS of 6 mA and a pinch-off voltage of VGS 6 V. Do not let the minus, signs for VDS confuse you. They simply indicate that the source is at a higher potential than the drain., , Figure 5.12 p-Channel JFET characteristics with IDSS 6 mA and VP 6 V., , Note at high levels of VDS that the curves suddenly rise to levels that seem unbounded. The vertical rise is an indication that breakdown has occurred and the, current through the channel (in the same direction as normally encountered) is now, limited solely by the external circuit. Although not appearing in Fig. 5.10 for the, n-channel device, they do occur for the n-channel device if sufficient voltage is applied. This region can be avoided if the level of VDSmax is noted on the specification, sheet and the design is such that the actual level of VDS is less than this value for all, values of VGS., 5.2 Construction and Characteristics of JFETs, , 217
Page 229 :
Symbols, The graphic symbols for the n-channel and p-channel JFETs are provided in Fig. 5.13., Note that the arrow is pointing in for the n-channel device of Fig. 5.13a to represent, the direction in which IG would flow if the p-n junction were forward-biased. For the, p-channel device (Fig. 5.13b) the only difference in the symbol is the direction of the, arrow., , Figure 5.13 JFET symbols: (a), n-channel; (b) p-channel., , Summary, A number of important parameters and relationships were introduced in this section., A few that will surface frequently in the analysis to follow in this chapter and the, next for n-channel JFETs include the following:, The maximum current is defined as IDSS and occurs when VGS 0 V and, VDS |VP| as shown in Fig. 5.14a., For gate-to-source voltages VGS less than (more negative than) the pinch-off, level, the drain current is 0 A (ID 0 A) as appearing in Fig. 5.14b., For all levels of VGS between 0 V and the pinch-off level, the current ID will, range between IDSS and 0 A, respectively, as reviewed by Fig. 5.14c., For p-channel JFETs a similar list can be developed., , D, , +, , G, , VDD ≥ VP, , ID = IDSS, , +, VG S, , –, , VG S = 0 V, , D, , –, , S, , VG S = – VGG, G, , – +, VG S, VG G, –, +, VG G, , ≥, , (a), , ≥, , VG G, , ≥ 0V, , D, , G, , –, VG G, , +, , S, , VP, , 0 mA ≥ ID > IDSS, ID, , +, VG S, , –, , S, , (c), , Chapter 5, , VDD, , (b), , VP, , 218, , ID = 0 A, , Field-Effect Transistors, , VDD, , Figure 5.14 (a) VGS 0 V,, ID IDSS; (b) cutoff (ID 0 A), VGS less than the pinch-off level;, (c) ID exists between 0 A and IDSS, for VGS less than or equal to 0 V, and greater than the pinch-off, level.
Page 230 :
5.3 TRANSFER CHARACTERISTICS, Derivation, For the BJT transistor the output current IC and input controlling current IB were related by beta, which was considered constant for the analysis to be performed. In, equation form,, , control variable, ↓, (5.2), IC f(IB) IB, ↑, , constant, In Eq. (5.2) a linear relationship exists between IC and IB. Double the level of IB and, IC will increase by a factor of two also., Unfortunately, this linear relationship does not exist between the output and input, quantities of a JFET. The relationship between ID and VGS is defined by Shockley’s, equation:, control variable, ↓ 2, V, (5.3), ID IDSS 1 GS, VP, ↑, ↑, constants, , , , , , The squared term of the equation will result in a nonlinear relationship between ID and, VGS, producing a curve that grows exponentially with decreasing magnitudes of VGS., For the dc analysis to be performed in Chapter 6, a graphical rather than mathematical approach will in general be more direct and easier to apply. The graphical approach, however, will require a plot of Eq. (5.3) to represent the device and a plot of, the network equation relating the same variables. The solution is defined by the point, of intersection of the two curves. It is important to keep in mind when applying the, graphical approach that the device characteristics will be unaffected by the network, in which the device is employed. The network equation may change along with the, intersection between the two curves, but the transfer curve defined by Eq. (5.3) is unaffected. In general, therefore:, The transfer characteristics defined by Shockley’s equation are unaffected by, the network in which the device is employed., , William Bradford Shockley, (1910–1989), co-inventor of the, first transistor and formulator of, the “field-effect” theory employed, in the development of the, transistor and FET. (Courtesy of, AT&T Archives.), Born: London, England, PhD Harvard, 1936, Head, Transistor Physics, Department–Bell Laboratories, President, Shockley Transistor, Corp., Poniatoff Professor of, Engineering Science at, Stanford University, Nobel Prize in physics in 1956, with Drs. Brattain and Bardeen, , The transfer curve can be obtained using Shockley’s equation or from the output, characteristics of Fig. 5.10. In Fig. 5.15 two graphs are provided, with the vertical, ID (mA), , ID (mA), 10 10, 9 9, , IDSS, , 8 8, , VGS = 0 V, , IDSS, , 7 7, 6 6, 5 5, , VGS = –1 V, , 4 4, 3 3, VGS = –2 V, VGS = –3 V, VGS = – 4 V, , 2 2, 1 1, VGS (V) – 4, , –3, , –2, , –1, , 0 0, , 5, , 10, , 15, , 20, , 25, , ID = 0 mA, VGS = VP, , 5.3, , Transfer Characteristics, , VDS, , Figure 5.15 Obtaining the, transfer curve from the drain, characteristics., , 219
Page 231 :
scaling in milliamperes for each graph. One is a plot of ID versus VDS, while the other, is ID versus VGS. Using the drain characteristics on the right of the “y” axis, a horizontal line can be drawn from the saturation region of the curve denoted VGS 0 V, to the ID axis. The resulting current level for both graphs is IDSS. The point of intersection on the ID versus VGS curve will be as shown since the vertical axis is defined, as VGS 0 V., In review:, When VGS 0 V, ID IDSS., When VGS VP 4 V, the drain current is zero milliamperes, defining another, point on the transfer curve. That is:, When VGS VP, ID 0 mA., Before continuing, it is important to realize that the drain characteristics relate, one output (or drain) quantity to another output (or drain) quantity—both axes are, defined by variables in the same region of the device characteristics. The transfer characteristics are a plot of an output (or drain) current versus an input-controlling quantity. There is therefore a direct “transfer” from input to output variables when employing the curve to the left of Fig. 5.15. If the relationship were linear, the plot of, ID versus VGS would result in a straight line between IDSS and VP. However, a parabolic curve will result because the vertical spacing between steps of VGS on the drain, characteristics of Fig. 5.15 decreases noticeably as VGS becomes more and more negative. Compare the spacing between VGS 0 V and VGS 1 V to that between, VGS 3 V and pinch-off. The change in VGS is the same, but the resulting change, in ID is quite different., If a horizontal line is drawn from the VGS 1 V curve to the ID axis and then, extended to the other axis, another point on the transfer curve can be located. Note, that VGS 1 V on the bottom axis of the transfer curve with ID 4.5 mA. Note in, the definition of ID at VGS 0 V and 1 V that the saturation levels of ID are employed and the ohmic region ignored. Continuing with VGS 2 V and 3 V, the, transfer curve can be completed. It is the transfer curve of ID versus VGS that will receive extended use in the analysis of Chapter 6 and not the drain characteristics of, Fig. 5.15. The next few paragraphs will introduce a quick, efficient method of plotting ID versus VGS given only the levels of IDSS and VP and Shockley’s equation., , Applying Shockley’s Equation, The transfer curve of Fig. 5.15 can also be obtained directly from Shockley’s equation (5.3) given simply the values of IDSS and VP. The levels of IDSS and VP define, the limits of the curve on both axes and leave only the necessity of finding a few intermediate plot points. The validity of Eq. (5.3) as a source of the transfer curve of, Fig. 5.15 is best demonstrated by examining a few specific levels of one variable and, finding the resulting level of the other as follows:, Substituting VGS 0 V gives, Eq. (5.3):, , IDSS, , Chapter 5, , 2, , P, , ID IDSS | VGS 0 V, , and, 220, , , , 0, 1 V I, , Field-Effect Transistors, , 2, , V, ID IDSS 1 GS, VP, , DSS(1, , 0)2, (5.4)
Page 232 :
Substituting VGS VP yields, , , , VP, ID IDSS 1 , VP, , , , 2, , IDSS(1 1)2 IDSS (0), ID 0 AVGS VP, , (5.5), , For the drain characteristics of Fig. 5.15, if we substitute VGS 1 V,, , , , V, ID IDSS 1 GS, VP, , , , 2, , 1 V, 8 mA 1 , 4 V, 8 mA(0.5625), 4.5 mA, , , , 2, , , , , , , , 2, , 1, 8 mA 1 , 4, , 8 mA(0.75)2, , as shown in Fig. 5.15. Note the care taken with the negative signs for VGS and VP in, the calculations above. The loss of one sign would result in a totally erroneous result., It should be obvious from the above that given IDSS and VP (as is normally provided on specification sheets) the level of ID can be found for any level of VGS. Conversely, by using basic algebra we can obtain [from Eq. (5.3)] an equation for the resulting level of VGS for a given level of ID. The derivation is quite straight forward, and will result in, , I, ID, , VGS VP 1 , , (5.6), , DSS, , Let us test Eq. (5.6) by finding the level of VGS that will result in a drain current, of 4.5 mA for the device with the characteristics of Fig. 5.15., , , 8m, , A , 4.5 mA, , VGS 4 V 1 , , 4 V(1 0, .5, 625) 4 V(1 0.75), 4 V(0.25), 1 V, as substituted in the above calculation and verified by Fig. 5.15., , Shorthand Method, Since the transfer curve must be plotted so frequently, it would be quite advantageous, to have a shorthand method for plotting the curve in the quickest, most efficient manner while maintaining an acceptable degree of accuracy. The format of Eq. (5.3) is, such that specific levels of VGS will result in levels of ID that can be memorized to, provide the plot points needed to sketch the transfer curve. If we specify VGS to be, one-half the pinch-off value VP, the resulting level of ID will be the following, as determined by Shockley’s equation:, , , , 1 V /2, V, , V, ID IDSS 1 GS, VP, IDSS, , P, , P, , 2, , 2, , , , , , 1, IDSS 1 , 2, , 2, , IDSS(0.5)2, , IDSS (0.25), 5.3 Transfer Characteristics, , 221
Page 233 :
and, , , , I SS, ID D, 4, , (5.7), , VGS VP/2, , Now it is important to realize that Eq. (5.7) is not for a particular level of VP. It, is a general equation for any level of VP as long as VGS VP/2. The result specifies, that the drain current will always be one-fourth of the saturation level IDSS as long as, the gate-to-source voltage is one-half the pinch-off value. Note the level of ID for, VGS VP/2 4 V/2 2 V in Fig. 5.15., If we choose ID IDSS/2 and substitute into Eq. (5.6), we find that, , I, ID, , VGS VP 1 , , D SS, , , I , V (1 0.5) V (0.293), , VP 1 , , IDSS/2, , P, , P, , D SS, , and, , VGS, , 0.3VP|ID IDSS /2, , (5.8), , Additional points can be determined, but the transfer curve can be sketched to a, satisfactory level of accuracy simply using the four plot points defined above and reviewed in Table 5.1. In fact, in the analysis of Chapter 6, a maximum of four plot, points are used to sketch the transfer curves. On most occasions using just the plot, point defined by VGS VP /2 and the axis intersections at IDSS and VP will provide a, curve accurate enough for most calculations., , TABLE 5.1 VGS versus ID Using, Shockley’s Equation, , EXAMPLE 5.1, , VGS, , ID, , 0, 0.3 VP, 0.5 VP, VP, , IDSS, IDSS/2, IDSS/4, 0 mA, , Sketch the transfer curve defined by IDSS 12 mA and VP 6 V., , Solution, Two plot points are defined by, IDSS 12 mA, and, , ID 0 mA, , and, and, , VGS 0 V, VGS VP, , At VGS VP /2 6 V/2 3 V the drain current will be determined by ID , IDSS /4 12 mA/4 3 mA. At ID IDSS /2 12 mA/2 6 mA the gate-to-source, voltage is determined by VGS 0.3VP 0.3(6 V) 1.8 V. All four plot points, are well defined on Fig. 5.16 with the complete transfer curve., 222, , Chapter 5, , Field-Effect Transistors
Page 234 :
Figure 5.16 Transfer curve for, Example 5.1., , For p-channel devices Shockley’s equation (5.3) can still be applied exactly as it, appears. In this case, both VP and VGS will be positive and the curve will be the mirror, image of the transfer curve obtained with an n-channel and the same limiting values., Sketch the transfer curve for a p-channel device with IDSS 4 mA and VP 3 V., , EXAMPLE 5.2, , Solution, At VGS VP /2 3 V/2 1.5 V, ID IDSS /4 4 mA/4 1 mA. At ID IDSS/2 , 4 mA/2 2 mA, VGS 0.3VP 0.3(3 V) 0.9 V. Both plot points appear in Fig., 5.17 along with the points defined by IDSS and VP., , Figure 5.17 Transfer curve for the, p-channel device of Example 5.2., , 5.4 SPECIFICATION SHEETS ( JFETs), Although the general content of specification sheets may vary from the absolute, minimum to an extensive display of graphs and charts, there are a few fundamental, parameters that will be provided by all manufacturers. A few of the most important, are discussed in the following paragraphs. The specification sheet for the 2N5457, n-channel JFET as provided by Motorola is provided as Fig. 5.18., 5.4, , Specification Sheets (JFETs), , 223
Page 235 :
Figure 5.18 2N5457 Motorola n-channel JFET., , Maximum Ratings, The maximum rating list usually appears at the beginning of the specification sheet,, with the maximum voltages between specific terminals, maximum current levels, and, the maximum power dissipation level of the device. The specified maximum levels, for VDS and VDG must not be exceeded at any point in the design operation of the device. The applied source VDD can exceed these levels, but the actual level of voltage, between these terminals must never exceed the level specified. Any good design will, 224, , Chapter 5, , Field-Effect Transistors
Page 236 :
try to avoid these levels by a good margin of safety. The term reverse in VGSR defines, the maximum voltage with the source positive with respect to the gate (as normally, biased for an n-channel device) before breakdown will occur. On some specification, sheets it is referred to as BVDSS —the Breakdown Voltage with the Drain-Source, Shorted (VDS 0 V). Although normally designed to operate with IG 0 mA, if forced, to accept a gate current it could withstand 10 mA before damage would occur. The, total device dissipation at 25°C (room temperature) is the maximum power the device can dissipate under normal operating conditions and is defined by, PD VDSID, , (5.9), , Note the similarity in format with the maximum power dissipation equation for the, BJT transistor., The derating factor is discussed in detail in Chapter 3, but for the moment recognize that the 2.82 mW/°C rating reveals that the dissipation rating decreases by, 2.82 mW for each increase in temperature of 1°C above 25°C., , Electrical Characteristics, The electrical characteristics include the level of VP in the OFF CHARACTERISTICS and IDSS in the ON CHARACTERISTICS. In this case VP VGS(off) has a range, from 0.5 to 6.0 V and IDSS from 1 to 5 mA. The fact that both will vary from, device to device with the same nameplate identification must be considered in the, design process. The other quantities are defined under conditions appearing in parentheses. The small-signal characteristics are discussed in Chapter 9., , Case Construction and Terminal Identification, This particular JFET has the appearance provided on the specification sheet of Fig., 5.18. The terminal identification is also provided directly under the figure. JFETs are, also available in top-hat containers, as shown in Fig. 5.19 with its terminal identification., , Operating Region, The specification sheet and the curve defined by the pinch-off levels at each level of, VGS define the region of operation for linear amplification on the drain characteristics as shown in Fig. 5.20. The ohmic region defines the minimum permissible values of VDS at each level of VGS, and VDSmax specifies the maximum value for this pa-, , Figure 5.19 Top-hat container, and terminal identification for a, p-channel JFET., , Figure 5.20 Normal operating, region for linear amplifier design., , 5.4, , Specification Sheets (JFETs), , 225
Page 237 :
rameter. The saturation current IDSS is the maximum drain current, and the maximum, power dissipation level defines the curve drawn in the same manner as described for, BJT transistors. The resulting shaded region is the normal operating region for amplifier design., , 5.5 INSTRUMENTATION, Recall from Chapter 3 that hand-held instruments are available to measure the level, of dc for the BJT transistor. Similar instrumentation is not available to measure the, levels of IDSS and VP. However, the curve tracer introduced for the BJT transistor can, also display the drain characteristics of the JFET transistor through a proper setting, of the various controls. The vertical scale (in milliamperes) and the horizontal scale, (in volts) have been set to provide a full display of the characteristics, as shown in, Fig. 5.21. For the JFET of Fig. 5.21, each vertical division (in centimeters) reflects a, 1-mA change in IC while each horizontal division has a value of 1 V. The step voltage is 500 mV/step (0.5 V/step), revealing that the top curve is defined by VGS 0 V, and the next curve down 0.5 V for the n-channel device. Using the same step voltage the next curve is 1 V, then 1.5 V, and finally 2 V. By drawing a line from, the top curve over to the ID axis, the level of IDSS can be estimated to be about 9 mA., The level of VP can be estimated by noting the VGS value of the bottom curve and, taking into account the shrinking distance between curves as VGS becomes more and, more negative. In this case, VP is certainly more negative than 2 V and perhaps VP, is close to 2.5 V. However, keep in mind that the VGS curves contract very quickly, as they approach the cutoff condition, and perhaps VP 3 V is a better choice. It, VGS = 0 V, , I DSS ≅ 9 mA, , Vertical, Sens., , 1 mA, per div., VGS = –0.5 V, Horizontal, Sens., , 1V, per div., VGS = –1 V, I DSS = 4.5 mA, 2, (VGS = – 0.9 V), , 500 mV, per step., VGS = –1.5 V, gm, , 2m, per div., 1 mA, div, , VGS = –2 V, VP ≅ − 3 V, , 1V, div, , Figure 5.21 Drain characteristics for a 2N4416 JFET transistor as displayed on a, curve tracer., , 226, , Chapter 5, , Field-Effect Transistors
Page 238 :
should also be noted that the step control is set for a 5-step display, limiting the displayed curves to VGS 0, 0.5, 1, 1.5, and 2 V. If the step control had been, increased to 10, the voltage per step could be reduced to 250 mV 0.25 V and the, curve for VGS 2.25 V would have been included as well as an additional curve, between each step of Fig. 5.21. The VGS 2.25 V curve would reveal how quickly, the curves are closing in on each other for the same step voltage. Fortunately, the level, of VP can be estimated to a reasonable degree of accuracy simply by applying a condition appearing in Table 5.1. That is, when ID IDSS /2, then VGS 0.3VP. For the, characteristics of Fig. 5.21, ID IDSS /2 9 mA/2 4.5 mA, and as visible from Fig., 5.21 the corresponding level of VGS is about 0.9 V. Using this information we find, that VP VGS /0.3 0.9 V/0.3 3 V, which will be our choice for this device., Using this value we find that at VGS 2 V,, V, ID IDSS 1 GS, VP, , , , 2, , , , 2 V, 9 mA 1 , 3 V, 1 mA, , , , 2, , , , as supported by Fig. 5.21., At VGS 2.5 V, Shockley’s equation will result in ID 0.25 mA, with VP , 3 V clearly revealing how quickly the curves contract near VP. The importance of, the parameter gm and how it is determined from the characteristics of Fig. 5.21 are, described in Chapter 8 when small-signal ac conditions are examined., , 5.6 IMPORTANT RELATIONSHIPS, A number of important equations and operating characteristics have been introduced in, the last few sections that are of particular importance for the analysis to follow for the dc, and ac configurations. In an effort to isolate and emphasize their importance, they are repeated below next to a corresponding equation for the BJT transistor. The JFET equations, are defined for the configuration of Fig. 5.22a, while the BJT equations relate to Fig. 5.22b., JFET, D, , BJT, C, IC, , ID, IG = 0 A, G, , (, , ID = IDSS 1 –, , +, VGS, , VGS, VP, , IB, , 2, , (, , B, , IS, , IC = β IB, , +, , VBE = 0.7 V, , –, , IE, , –, E, , S, , Figure 5.22 (a) JFET versus, (b) BJT., , (b), , (a), , JFET, , , , V, 1 GS, VP, , BJT, , , , 2, , ⇔, , IC IB, , ID IS, , ⇔, , IC, , IG, , ⇔, , VBE, , ID IDSS, , 0A, , IE, , (5.10), , 0.7 V, , 5.6 Important Relationships, , 227
Page 239 :
A clear understanding of the impact of each of the equations above is sufficient, background to approach the most complex of dc configurations. Recall that VBE , 0.7 V was often the key to initiating an analysis of a BJT configuration. Similarly,, the condition IG 0 A is often the starting point for the analysis of a JFET configuration. For the BJT configuration, IB is normally the first parameter to be determined., For the JFET, it is normally VGS. The number of similarities between the analysis of, BJT and JFET dc configurations will become quite apparent in Chapter 6., , 5.7 DEPLETION-TYPE MOSFET, As noted in the chapter introduction, there are two types of FETs: JFETs and MOSFETs. MOSFETs are further broken down into depletion type and enhancement type., The terms depletion and enhancement define their basic mode of operation, while the, label MOSFET stands for metal-oxide-semiconductor-field-effect transistor. Since, there are differences in the characteristics and operation of each type of MOSFET,, they are covered in separate sections. In this section we examine the depletion-type, MOSFET, which happens to have characteristics similar to those of a JFET between, cutoff and saturation at IDSS but then has the added feature of characteristics that extend into the region of opposite polarity for VGS., , Basic Construction, The basic construction of the n-channel depletion-type MOSFET is provided in Fig., 5.23. A slab of p-type material is formed from a silicon base and is referred to as the, substrate. It is the foundation upon which the device will be constructed. In some, cases the substrate is internally connected to the source terminal. However, many discrete devices provide an additional terminal labeled SS, resulting in a four-terminal, device, such as that appearing in Fig. 5.23. The source and drain terminals are connected through metallic contacts to n-doped regions linked by an n-channel as shown, in the figure. The gate is also connected to a metal contact surface but remains insulated from the n-channel by a very thin silicon dioxide (SiO2) layer. SiO2 is a particular type of insulator referred to as a dielectric that sets up opposing (as revealed by, , Figure 5.23 n-Channel depletion-type MOSFET., , 228, , Chapter 5, , Field-Effect Transistors
Page 240 :
the prefix di-) electric fields within the dielectric when exposed to an externally applied field. The fact that the SiO2 layer is an insulating layer reveals the following, fact:, There is no direct electrical connection between the gate terminal and the, channel of a MOSFET., In addition:, It is the insulating layer of SiO2 in the MOSFET construction that accounts, for the very desirable high input impedance of the device., In fact, the input resistance of a MOSFET is often that of the typical JFET, even, though the input impedance of most JFETs is sufficiently high for most applications., The very high input impedance continues to fully support the fact that the gate current (IG) is essentially zero amperes for dc-biased configurations., The reason for the label metal-oxide-semiconductor FET is now fairly obvious:, metal for the drain, source, and gate connections to the proper surface—in particular, the gate terminal and the control to be offered by the surface area of the contact,, the oxide for the silicon dioxide insulating layer, and the semiconductor for the basic, structure on which the n- and p-type regions are diffused. The insulating layer between the gate and channel has resulted in another name for the device: insulatedgate FET or IGFET, although this label is used less and less in current literature., , Basic Operation and Characteristics, In Fig. 5.24 the gate-to-source voltage is set to zero volts by the direct connection, from one terminal to the other, and a voltage VDS is applied across the drain-to-source, terminals. The result is an attraction for the positive potential at the drain by the free, electrons of the n-channel and a current similar to that established through the channel of the JFET. In fact, the resulting current with VGS 0 V continues to be labeled, IDSS, as shown in Fig. 5.25., , Figure 5.24 n-Channel depletion-type MOSFET with VGS 0 V and an applied, voltage VDD., , 5.7 Depletion-Type MOSFET, , 229
Page 241 :
ID (mA), , Depletion, mode, , ID, VGS = + 1 V, , 10.9, Enhancement, mode, I DSS, , 8, , VGS = 0 V, , VGS = –1 V, I DSS, 2, IDSS, 4, , 4, 2, , – 6 – 5 – 4 – 3 – 2 –1 0, VP 0.3V, VP, P, 2, , 1, , VGS, , VGS = – 2 V, VGS = VP = – 3 V, 2, –4 V, –5 V, , 0, VGS = VP = – 6 V, , VDS, , Figure 5.25 Drain and transfer characteristics for an n-channel depletion-type MOSFET., , In Fig. 5.26, VGS has been set at a negative voltage such as 1 V. The negative, potential at the gate will tend to pressure electrons toward the p-type substrate (like, charges repel) and attract holes from the p-type substrate (opposite charges attract) as, shown in Fig. 5.26. Depending on the magnitude of the negative bias established by, VGS, a level of recombination between electrons and holes will occur that will reduce, the number of free electrons in the n-channel available for conduction. The more negative the bias, the higher the rate of recombination. The resulting level of drain current is therefore reduced with increasing negative bias for VGS as shown in Fig. 5.25, for VGS 1 V, 2 V, and so on, to the pinch-off level of 6 V. The resulting levels of drain current and the plotting of the transfer curve proceeds exactly as described, for the JFET., , Figure 5.26 Reduction in free, carriers in channel due to a negative potential at the gate terminal., , For positive values of VGS , the positive gate will draw additional electrons (free, carriers) from the p-type substrate due to the reverse leakage current and establish, new carriers through the collisions resulting between accelerating particles. As the, gate-to-source voltage continues to increase in the positive direction, Fig. 5.25 reveals, that the drain current will increase at a rapid rate for the reasons listed above. The, 230, , Chapter 5, , Field-Effect Transistors
Page 242 :
vertical spacing between the VGS 0 V and VGS 1 V curves of Fig. 5.25 is a clear, indication of how much the current has increased for the 1-V change in VGS. Due, to the rapid rise, the user must be aware of the maximum drain current rating since, it could be exceeded with a positive gate voltage. That is, for the device of Fig. 5.25,, the application of a voltage VGS 4 V would result in a drain current of 22.2 mA,, which could possibly exceed the maximum rating (current or power) for the device., As revealed above, the application of a positive gate-to-source voltage has “enhanced”, the level of free carriers in the channel compared to that encountered with VGS , 0 V. For this reason the region of positive gate voltages on the drain or transfer characteristics is often referred to as the enhancement region, with the region between, cutoff and the saturation level of IDSS referred to as the depletion region., It is particularly interesting and helpful that Shockley’s equation will continue to, be applicable for the depletion-type MOSFET characteristics in both the depletion, and enhancement regions. For both regions, it is simply necessary that the proper sign, be included with VGS in the equation and the sign be carefully monitored in the mathematical operations., Sketch the transfer characteristics for an n-channel depletion-type MOSFET with, IDSS 10 mA and VP 4 V., , EXAMPLE 5.3, , Solution, At VGS 0 V,, , ID IDSS 10 mA, , VGS VP 4 V,, , ID 0 mA, , VP, 4 V, VGS , 2 V,, 2, 2, I SS, and at ID D,, 2, , I SS, 10 mA, ID D, 2.5 mA, 4, 4, , VGS 0.3VP 0.3(4 V) 1.2 V, , all of which appear in Fig. 5.27., Before plotting the positive region of VGS, keep in mind that ID increases very, rapidly with increasing positive values of VGS. In other words, be conservative with, the choice of values to be substituted into Shockley’s equation. In this case, we will, try 1 V as follows:, , , , V, ID IDSS 1 GS, VP, , , , 2, , 1 V, 10 mA 1 , 4 V, , , , , , 2, , 10 mA(1 0.25)2 10 mA(1.5625), , 15.63 mA, which is sufficiently high to finish the plot., , p-Channel Depletion-Type MOSFET, The construction of a p-channel depletion-type MOSFET is exactly the reverse of that, appearing in Fig. 5.23. That is, there is now an n-type substrate and a p-type channel, as shown in Fig. 5.28a. The terminals remain as identified, but all the voltage polarities and the current directions are reversed, as shown in the same figure. The drain, characteristics would appear exactly as in Fig. 5.25 but with VDS having negative val5.7 Depletion-Type MOSFET, , Figure 5.27 Transfer characteristics for an n-channel depletiontype MOSFET with IDSS 10 mA, and VP 4 V., , 231
Page 243 :
ID (mA), , ID (mA), , D, , VGS, , 8, , 8, , 6, , p, , +, , 9, , n, , p, p, , SS, , IDSS, , VGS = 0 V, , 6, , 5, , 5, , 4, , 4, , 3, , 3, , 2, , 2, , 1, , 1, , –1 0, , –, , VGS = –1 V, , 7, , 7, ID, , G, , 9, , 1 2 3 4 5 6, VP, , VGS, , VGS = +1 V, VGS = +2 V, VGS = +3 V, VGS = +4 V, VGS = +5 V, , 0, , VGS = VP = +6 V, , VDS, , S, (a), , (b), , (c), , Figure 5.28 p-Channel depletion-type MOSFET with IDSS 6 mA and VP 6 V., , ues, ID having positive values as indicated (since the defined direction is now reversed), and VGS having the opposite polarities as shown in Fig. 5.28c. The reversal, in VGS will result in a mirror image (about the ID axis) for the transfer characteristics, as shown in Fig. 5.28b. In other words, the drain current will increase from cutoff at, VGS VP in the positive VGS region to IDSS and then continue to increase for increasingly negative values of VGS. Shockley’s equation is still applicable and requires, simply placing the correct sign for both VGS and VP in the equation., , Symbols, Specification Sheets, and Case, Construction, The graphic symbols for an n- and p-channel depletion-type MOSFET are provided, in Fig. 5.29. Note how the symbols chosen try to reflect the actual construction of the, device. The lack of a direct connection (due to the gate insulation) between the gate, and channel is represented by a space between the gate and the other terminals of the, symbol. The vertical line representing the channel is connected between the drain and, source and is “supported” by the substrate. Two symbols are provided for each type, of channel to reflect the fact that in some cases the substrate is externally available, while in others it is not. For most of the analysis to follow in Chapter 6, the substrate, and source will be connected and the lower symbols will be employed., , Figure 5.29 Graphic symbols, for (a) n-channel depletion-type, MOSFETs and (b) p-channel, depletion-type MOSFETs., , 232, , Chapter 5, , Field-Effect Transistors
Page 244 :
The device appearing in Fig. 5.30 has three terminals, with the terminal identification appearing in the same figure. The specification sheet for a depletion-type MOSFET is similar to that of a JFET. The levels of VP and IDSS are provided along with, a list of maximum values and typical “on” and “off” characteristics. In addition, how-, , Figure 5.30 2N3797 Motorola n-channel depletion-type MOSFET., , 5.7 Depletion-Type MOSFET, , 233
Page 245 :
ever, since ID can extend beyond the IDSS level, another point is normally provided, that reflects a typical value of ID for some positive voltage (for an n-channel device)., For the unit of Fig. 5.30, ID is specified as ID(on) 9 mA dc, with VDS 10 V and, VGS 3.5 V., , 5.8 ENHANCEMENT-TYPE MOSFET, Although there are some similarities in construction and mode of operation between, depletion-type and enhancement-type MOSFETs, the characteristics of the enhancement-type MOSFET are quite different from anything obtained thus far. The transfer, curve is not defined by Shockley’s equation, and the drain current is now cut off until the gate-to-source voltage reaches a specific magnitude. In particular, current control in an n-channel device is now effected by a positive gate-to-source voltage rather, than the range of negative voltages encountered for n-channel JFETs and n-channel, depletion-type MOSFETs., , Basic Construction, The basic construction of the n-channel enhancement-type MOSFET is provided in, Fig. 5.31. A slab of p-type material is formed from a silicon base and is again referred to as the substrate. As with the depletion-type MOSFET, the substrate is sometimes internally connected to the source terminal, while in other cases a fourth lead, is made available for external control of its potential level. The source and drain terminals are again connected through metallic contacts to n-doped regions, but note in, Fig. 5.31 the absence of a channel between the two n-doped regions. This is the primary difference between the construction of depletion-type and enhancement-type, MOSFETs—the absence of a channel as a constructed component of the device. The, SiO2 layer is still present to isolate the gate metallic platform from the region between the drain and source, but now it is simply separated from a section of the, p-type material. In summary, therefore, the construction of an enhancement-type, MOSFET is quite similar to that of the depletion-type MOSFET, except for the absence of a channel between the drain and source terminals., , Figure 5.31 n-Channel enhancement-type MOSFET., , 234, , Chapter 5, , Field-Effect Transistors
Page 246 :
Basic Operation and Characteristics, If VGS is set at 0 V and a voltage applied between the drain and source of the device, of Fig. 5.31, the absence of an n-channel (with its generous number of free carriers), will result in a current of effectively zero amperes—quite different from the depletion-type MOSFET and JFET where ID IDSS. It is not sufficient to have a large accumulation of carriers (electrons) at the drain and source (due to the n-doped regions), if a path fails to exist between the two. With VDS some positive voltage, VGS at 0 V,, and terminal SS directly connected to the source, there are in fact two reverse-biased, p-n junctions between the n-doped regions and the p-substrate to oppose any significant flow between drain and source., In Fig. 5.32 both VDS and VGS have been set at some positive voltage greater than, 0 V, establishing the drain and gate at a positive potential with respect to the source., The positive potential at the gate will pressure the holes (since like charges repel) in, the p-substrate along the edge of the SiO2 layer to leave the area and enter deeper regions of the p-substrate, as shown in the figure. The result is a depletion region near, the SiO2 insulating layer void of holes. However, the electrons in the p-substrate (the, minority carriers of the material) will be attracted to the positive gate and accumulate in the region near the surface of the SiO2 layer. The SiO2 layer and its insulating qualities will prevent the negative carriers from being absorbed at the gate terminal. As VGS increases in magnitude, the concentration of electrons near the SiO2 surface, increases until eventually the induced n-type region can support a measurable flow, between drain and source. The level of VGS that results in the significant increase in, drain current is called the threshold voltage and is given the symbol VT. On specification sheets it is referred to as VGS(Th), although VT is less unwieldy and will be used, in the analysis to follow. Since the channel is nonexistent with VGS 0 V and “enhanced” by the application of a positive gate-to-source voltage, this type of MOSFET, is called an enhancement-type MOSFET. Both depletion- and enhancement-type MOSFETs have enhancement-type regions, but the label was applied to the latter since it, is its only mode of operation., , Electrons attracted to positive gate, (induced n-channel), Region depleted of p-type, carriers (holes), , ID, , n, , D, , IG = 0 A, G, , +, VGS, , –, S, , +, +, +, +, +, +, , e, e, e, e, e, e, e, e, , +, +, +, +, +, +, +, , SS, , p, , +, VDS, , –, , n, , IS = ID, Insulating layer, , Holes repelled, by positive gate, , Figure 5.32 Channel formation, in the n-channel enhancementtype MOSFET., , 5.8 Enhancement-Type MOSFET, , 235
Page 247 :
As VGS is increased beyond the threshold level, the density of free carriers in the, induced channel will increase, resulting in an increased level of drain current. However, if we hold VGS constant and increase the level of VDS, the drain current will, eventually reach a saturation level as occurred for the JFET and depletion-type MOSFET. The leveling off of ID is due to a pinching-off process depicted by the narrower, channel at the drain end of the induced channel as shown in Fig. 5.33. Applying Kirchhoff’s voltage law to the terminal voltages of the MOSFET of Fig. 5.33, we find that, VDG VDS VGS, , (5.11), , Figure 5.33 Change in channel, and depletion region with increasing level of VDS for a fixed value, of VGS., , If VGS is held fixed at some value such as 8 V and VDS is increased from 2 to 5, V, the voltage VDG [by Eq. (5.11)] will drop from 6 to 3 V and the gate will become less and less positive with respect to the drain. This reduction in gate-to-drain, voltage will in turn reduce the attractive forces for free carriers (electrons) in this region of the induced channel, causing a reduction in the effective channel width. Eventually, the channel will be reduced to the point of pinch-off and a saturation condition will be established as described earlier for the JFET and depletion-type MOSFET., In other words, any further increase in VDS at the fixed value of VGS will not affect, the saturation level of ID until breakdown conditions are encountered., The drain characteristics of Fig. 5.34 reveal that for the device of Fig. 5.33 with, VGS 8 V, saturation occurred at a level of VDS 6 V. In fact, the saturation level, for VDS is related to the level of applied VGS by, VDSsat VGS VT, , (5.12), , Obviously, therefore, for a fixed value of VT, then the higher the level of VGS, the more, the saturation level for VDS, as shown in Fig. 5.33 by the locus of saturation levels., 236, , Chapter 5, , Field-Effect Transistors
Page 248 :
ID (mA), , Locus of VDSsat, , 11, VGS = +8 V, , 10, 9, 8, , VGS = +7 V, , 7, 6, 5, , VGS = +6 V, , 4, 3, , VGS = +5 V, , 2, VGS = +4 V, VGS = +3 V, , 1, 0, , 5V, 6V, , 10 V, , 15 V, , 20 V, , 25 V, , VGS = V T = 2 V, , VDS, , Figure 5.34 Drain characteristics of an n-channel enhancement-type, MOSFET with VT 2 V and k 0.278 103 A/V2., , For the characteristics of Fig. 5.33 the level of VT is 2 V, as revealed by the fact, that the drain current has dropped to 0 mA. In general, therefore:, For values of VGS less than the threshold level, the drain current of an enhancement-type MOSFET is 0 mA., Figure 5.34 clearly reveals that as the level of VGS increased from VT to 8 V, the, resulting saturation level for ID also increased from a level of 0 to 10 mA. In addition, it is quite noticeable that the spacing between the levels of VGS increased as the, magnitude of VGS increased, resulting in ever-increasing increments in drain current., For levels of VGS VT, the drain current is related to the applied gate-to-source, voltage by the following nonlinear relationship:, ID k(VGS VT)2, , (5.13), , Again, it is the squared term that results in the nonlinear (curved) relationship between ID and VGS. The k term is a constant that is a function of the construction of, the device. The value of k can be determined from the following equation [derived, from Eq. (5.13)] where ID(on) and VGS(on) are the values for each at a particular point, on the characteristics of the device., ID(on), k 2, (VGS(on) VT), , (5.14), , Substituting ID(on) 10 mA when VGS(on) 8 V from the characteristics of Fig., 5.34 yields, 10 mA, 10 mA, 10 mA, , k 2 , (8 V 2 V), (6 V)2, 36 V2, 0.278 103 A/V2, and a general equation for ID for the characteristics of Fig. 5.34 results in:, ID 0.278, , 103(VGS 2 V)2, 5.8 Enhancement-Type MOSFET, , 237
Page 249 :
Substituting VGS 4 V, we find that, 103(4 V 2 V)2 0.278, , ID 0.278, , 103(2)2, , 103(4) 1.11 mA, , 0.278, , as verified by Fig. 5.34. At VGS VT , the squared term is 0 and ID 0 mA., For the dc analysis of enhancement-type MOSFETs to appear in Chapter 6, the, transfer characteristics will again be the characteristics to be employed in the graphical solution. In Fig. 5.35 the drain and transfer characteristics have been set side by, side to describe the transfer process from one to the other. Essentially, it proceeds as, introduced earlier for the JFET and depletion-type MOSFETs. In this case, however,, it must be remembered that the drain current is 0 mA for VGS VT. At this point a, measurable current will result for ID and will increase as defined by Eq. (5.13). Note, that in defining the points on the transfer characteristics from the drain characteristics, only the saturation levels are employed, thereby limiting the region of operation, to levels of VDS greater than the saturation levels as defined by Eq. (5.12)., , ID (mA), , ID (mA), , 10, , 10, , 9, , 9, , 8, , 8, , 7, , 7, , 6, , 6, , 5, , 5, , 4, , 4, , 3, , 3, , 2, , 2, , 1, , 1, , 0, , 1, , 2, VT, , 3, , 4, , 5, , 6, , 7, , 8, , VGS, , VGS = +8 V, , VGS = +7 V, , VGS = +6 V, , VGS = +5 V, VGS = +4 V, VGS = +3 V, , 0, , 5, , 10, , 15, , 20, , 25, , VDS, , VGS = V T = 2 V, , Figure 5.35 Sketching the transfer characteristics for an n-channel enhancementtype MOSFET from the drain characteristics., , The transfer curve of Fig. 5.35 is certainly quite different from those obtained earlier. For an n-channel (induced) device, it is now totally in the positive VGS region, and does not rise until VGS VT. The question now surfaces as to how to plot the, transfer characteristics given the levels of k and VT as included below for a particular MOSFET:, ID 0.5, , 103(VGS 4 V)2, , First, a horizontal line is drawn at ID 0 mA from VGS 0 V to VGS 4 V as, shown in Fig. 5.36a. Next, a level of VGS greater than VT such as 5 V is chosen and, substituted into Eq. (5.13) to determine the resulting level of ID as follows:, ID 0.5, 0.5, , 103(VGS 4 V)2, 103(5 V 4 V)2 0.5, , 0.5 mA, 238, , Chapter 5, , Field-Effect Transistors, , 103(1)2
Page 250 :
Figure 5.36 Plotting the transfer characteristics of an n-channel enhancementtype MOSFET with k 0.5 103 A/V2 and VT 4 V., , and a point on the plot is obtained as shown in Fig. 5.36b. Finally, additional levels, of VGS are chosen and the resulting levels of ID obtained. In particular, at VGS 6,, 7, and 8 V, the level of ID is 2, 4.5, and 8 mA, respectively, as shown on the resulting plot of Fig. 5.36c., , p-Channel Enhancement-Type MOSFETs, The construction of a p-channel enhancement-type MOSFET is exactly the reverse of, that appearing in Fig. 5.31, as shown in Fig. 5.37a. That is, there is now an n-type, substrate and p-doped regions under the drain and source connections. The terminals, remain as identified, but all the voltage polarities and the current directions are reversed. The drain characteristics will appear as shown in Fig. 5.37c, with increasing, levels of current resulting from increasingly negative values of VGS. The transfer characteristics will be the mirror image (about the ID axis) of the transfer curve of Fig., 5.35, with ID increasing with increasingly negative values of VGS beyond VT, as shown, in Fig. 5.37b. Equations (5.11) through (5.14) are equally applicable to p-channel devices., 5.8 Enhancement-Type MOSFET, , 239
Page 251 :
ID (mA), , D, ID, , p, G, , n, , –, , SS, , p, , +, , –6 –5 –4 –3 –2 –1, VT, , D, (a), , ID (mA), , 8, , 8, , 7, , 7, , 6, , 6, , 5, , 5, , 4, , 4, , 3, , 3, , 2, , 2, , 1, , 1, , 0, , VGS, , VGS = –6 V, , VGS = –5 V, , VGS = –4 V, VGS = –3 V, , 0, , VGS = VT = –2 V, , (b), , VDS, , (c), , Figure 5.37 p-Channel enhancement-type MOSFET with VT 2 V and, , k 0.5, , 103 A/V2., , Symbols, Specification Sheets, and Case, Construction, The graphic symbols for the n- and p-channel enhancement-type MOSFETs are provided as Fig. 5.38. Again note how the symbols try to reflect the actual construction, of the device. The dashed line between drain and source was chosen to reflect the fact, that a channel does not exist between the two under no-bias conditions. It is, in fact,, the only difference between the symbols for the depletion-type and enhancement-type, MOSFETs., , Figure 5.38 Symbols for (a), n-channel enhancement-type, MOSFETs and (b) p-channel, enhancement-type MOSFETs., , The specification sheet for a Motorola n-channel enhancement-type MOSFET is, provided as Fig. 5.39. The case construction and terminal identification are provided, next to the maximum ratings, which now include a maximum drain current of 30 mA, dc. The specification sheet provides the level of IDSS under “off” conditions, which is, now simply 10 nA dc (at VDS 10 V and VGS 0 V) compared to the milliampere, range for the JFET and depletion-type MOSFET. The threshold voltage is specified, 240, , Chapter 5, , Field-Effect Transistors
Page 252 :
Figure 5.39 2N4351 Motorola n-channel enhancement-type MOSFET., , as VGS(Th) and has a range of 1 to 5 V dc, depending on the unit employed. Rather, than provide a range of k in Eq. (5.13), a typical level of ID(on) (3 mA in this case) is, specified at a particular level of VGS(on) (10 V for the specified ID level). In other, words, when VGS 10 V, ID 3 mA. The given levels of VGS(Th), ID(on), and VGS(on), permit a determination of k from Eq. (5.14) and a writing of the general equation for, the transfer characteristics. The handling requirements of MOSFETs are reviewed in, Section 5.9., 5.8 Enhancement-Type MOSFET, , 241
Page 253 :
EXAMPLE 5.4, , Using the data provided on the specification sheet of Fig. 5.39 and an average threshold voltage of VGS(Th) 3 V, determine:, (a) The resulting value of k for the MOSFET., (b) The transfer characteristics., , Solution, ID(on), (a) Eq. (5.14): k , (VGS(on) VGS(Th) )2, 3 103, 3 mA, 3 mA, , , , , , A/V2, , (10 V 3 V)2, (7 V)2, 49, 0.061 103 A/V2, (b) Eq. (5.13): ID k(VGS VT)2, 0.061 103(VGS 3 V)2, For VGS 5 V,, ID 0.061, 0.061, , 103(5 V 3 V)2 0.061, , 103(2)2, , 103(4) 0.244 mA, , For VGS 8, 10, 12, and 14 V, ID will be 1.525, 3 (as defined), 4.94, and 7.38 mA,, respectively. The transfer characteristics are sketched in Fig. 5.40., , Figure 5.40 Solution to Example 5.4., , 5.9 MOSFET HANDLING, The thin SiO2 layer between the gate and channel of MOSFETs has the positive effect of providing a high-input-impedance characteristic for the device, but because of, its extremely thin layer, it introduces a concern for its handling that was not present, for the BJT or JFET transistors. There is often sufficient accumulation of static charge, (that we pick up from our surroundings) to establish a potential difference across the, thin layer that can break down the layer and establish conduction through it. It is, therefore imperative that we leave the shorting (or conduction) shipping foil (or ring), 242, , Chapter 5, , Field-Effect Transistors
Page 254 :
connecting the leads of the device together until the device is to be inserted in the, system. The shorting ring prevents the possibility of applying a potential across any, two terminals of the device. With the ring the potential difference between any two, terminals is maintained at 0 V. At the very least always touch ground to permit discharge of the accumulated static charge before handling the device, and always pick, up the transistor by the casing., There are often transients (sharp changes in voltage or current) in a network when, elements are removed or inserted if the power is on. The transient levels can often be, more than the device can handle, and therefore the power should always be off when, network changes are made., The maximum gate-to-source voltage is normally provided in the list of maximum, ratings of the device. One method of ensuring that this voltage is not exceeded (perhaps by transient effects) for either polarity is to introduce two Zener diodes, as shown, in Fig. 5.41. The Zeners are back to back to ensure protection for either polarity. If, both are 30-V Zeners and a positive transient of 40 V appears, the lower Zener will, “fire” at 30 V and the upper will turn on with a 0-V drop (ideally—for the positive, “on” region of a semiconductor diode) across the other diode. The result is a maximum of 30 V for the gate-to-source voltage. One disadvantage introduced by the Zener, protection is that the off resistance of a Zener diode is less than the input impedance, established by the SiO2 layer. The result is a reduction in input resistance, but even, so it is still high enough for most applications. So many of the discrete devices now, have the Zener protection that some of the concerns listed above are not as troublesome. However, it is still best to be somewhat cautious when handling discrete MOSFET devices., , Figure 5.41 Zener-protected, MOSFET., , 5.10 VMOS, One of the disadvantages of the typical MOSFET is the reduced power-handling levels (typically, less than 1 W) compared to BJT transistors. This shortfall for a device, with so many positive characteristics can be softened by changing the construction, mode from one of a planar nature such as shown in Fig. 5.23 to one with a vertical, structure as shown in Fig. 5.42. All the elements of the planar MOSFET are present, in the vertical metal-oxide-silicon FET (VMOS)—the metallic surface connection to, the terminals of the device—the SiO2 layer between the gate and the p-type region, between the drain and source for the growth of the induced n-channel (enhancement-, , Figure 5.42 VMOS construction., , 5.10 VMOS, , 243
Page 255 :
mode operation). The term vertical is due primarily to the fact that the channel is now, formed in the vertical direction rather than the horizontal direction for the planar device. However, the channel of Fig. 5.42 also has the appearance of a “V” cut in the, semiconductor base, which often stands out as a characteristic for mental memorization of the name of the device. The construction of Fig. 5.42 is somewhat simplistic, in nature, leaving out some of the transition levels of doping, but it does permit a description of the most important facets of its operation., The application of a positive voltage to the drain and a negative voltage to the, source with the gate at 0 V or some typical positive “on” level as shown in Fig. 5.42, will result in the induced n-channel in the narrow p-type region of the device. The, length of the channel is now defined by the vertical height of the p-region, which can, be made significantly less than that of a channel using planar construction. On a horizontal plane the length of the channel is limited to 1 to 2 m (1 m 106 m). Diffusion layers (such as the p-region of Fig. 5.42) can be controlled to small fractions, of a micrometer. Since decreasing channel lengths result in reduced resistance levels,, the power dissipation level of the device (power lost in the form of heat) at operating current levels will be reduced. In addition, the contact area between the channel, and the n region is greatly increased by the vertical mode construction, contributing to a further decrease in the resistance level and an increased area for current between the doping layers. There is also the existence of two conduction paths between, drain and source, as shown in Fig. 5.42, to further contribute to a higher current rating. The net result is a device with drain currents that can reach the ampere levels, with power levels exceeding 10 W., In general:, Compared with commercially available planar MOSFETs, VMOS FETs have, reduced channel resistance levels and higher current and power ratings., An additional important characteristic of the vertical construction is:, VMOS FETs have a positive temperature coefficient that will combat the possibility of thermal runaway., If the temperature of a device should increase due to the surrounding medium or, currents of the device, the resistance levels will increase, causing a reduction in drain, current rather than an increase as encountered for a conventional device. Negative, temperature coefficients result in decreased levels of resistance with increases in temperature that fuel the growing current levels and result in further temperature instability and thermal runaway., Another positive characteristic of the VMOS configuration is:, The reduced charge storage levels result in faster switching times for VMOS, construction compared to those for conventional planar construction., In fact, VMOS devices typically have switching times less than one-half that encountered for the typical BJT transistor., , 5.11 CMOS, A very effective logic circuit can be established by constructing a p-channel and an, n-channel MOSFET on the same substrate as shown in Fig. 5.43. Note the induced, p-channel on the left and the induced n-channel on the right for the p- and n-channel, devices, respectively. The configuration is referred to as a complementary MOSFET, arrangement (CMOS) that has extensive applications in computer logic design. The, relatively high input impedance, fast switching speeds, and lower operating power, levels of the CMOS configuration have resulted in a whole new discipline referred to, as CMOS logic design., 244, , Chapter 5, , Field-Effect Transistors
Page 256 :
Vi, Vo, VSS, , G2, S2, , G1, D2, , D1, , S1, , SiO2, n+, , p, , p+, , p+, , n, , n+, , When "on", , n+, , When "on", , p-channel MOSFET, , p+, , p, , n-channel MOSFET, n-type substrate, , Figure 5.43 CMOS with the connections indicated in Fig. 5.44., , One very effective use of the complementary arrangement is as an inverter, as, shown in Fig. 5.44. As introduced for switching transistors, an inverter is a logic element that “inverts” the applied signal. That is, if the logic levels of operation are, 0 V (0-state) and 5 V (1-state), an input level of 0 V will result in an output level of, 5 V, and vice versa. Note in Fig. 5.44 that both gates are connected to the applied signal and both drain to the output Vo. The source of the p-channel MOSFET (Q2) is, connected directly to the applied voltage VSS, while the source of the n-channel MOSFET (Q1) is connected to ground. For the logic levels defined above, the application, of 5 V at the input should result in approximately 0 V at the output. With 5 V at Vi, (with respect to ground), VGS1 Vi and Q1 is “on,” resulting in a relatively low resistance between drain and source as shown in Fig. 5.45. Since Vi and VSS are at 5 V,, VGS2 0 V, which is less than the required VT for the device, resulting in an “off”, state. The resulting resistance level between drain and source is quite high for Q2, as, shown in Fig. 5.45. A simple application of the voltage-divider rule will reveal that, Vo is very close to 0 V or the 0-state, establishing the desired inversion process. For, an applied voltage Vi of 0 V (0-state), VGS1 0 V and Q1 will be off with VSS2 , 5 V, turning on the p-channel MOSFET. The result is that Q2 will present a small, resistance level, Q1 a high resistance, and Vo VSS 5 V (the 1-state). Since the, drain current that flows for either case is limited by the “off” transistor to the leakage value, the power dissipated by the device in either state is very low. Additional, comment on the application of CMOS logic is presented in Chapter 17., , VSS, , Q2 off, , 5V, Ileakage, R2 (high), Vo =, , Q1 on, , Figure 5.44 CMOS inverter., , R1VSS, R1 + R2, , ≅ 0 V (0-state), , R1 (low), , Figure 5.45 Relative resistance, levels for Vi 5 V (1-state)., , 5.11 CMOS, , 245
Page 257 :
5.12 SUMMARY TABLE, Since the transfer curves and some important characteristics vary from one type of, FET to another, Table 5.2 was developed to clearly display the differences from one, device to the next. A clear understanding of all the curves and parameters of the table, will provide a sufficient background for the dc and ac analyses to follow in Chapters, 6 and 8. Take a moment to ensure that each curve is recognizable and its derivation, understood, and then establish a basis for comparison of the levels of the important, parameters of Ri and Ci for each device., , TABLE 5.2 Field Effect Transistors, Type, , -SymbolBasic Relationships, , Transfer Curve, , Input Resistance, and Capacitance, , JFET, (n-channel), , Ri 100 M, Ci: (1 10) pF, , MOSFET, depletion-type, (n-channel), , Ri 1010 , Ci: (1 10) pF, , MOSFET, enhancement-type, (n-channel), , Ri 1010 , Ci: (1 10) pF, , 246, , Chapter 5, , Field-Effect Transistors
Page 258 :
5.13 PSPICE WINDOWS, The characteristics of an n-channel JFET can be found in much the same manner as, employed for the bipolar transistor. The series of curves for various levels of V will, require a nested sweep under the main sweep for the drain-to-source voltage. The, configuration required appears in Fig. 5.46. Note the absence of any resistors since, the input impedance is assumed to be infinite, resulting in IG 0 A. Calling up the, device specifications through Edit-Model-Edit Instance Model (Text) will result in, a display having at the head of the listing a parameter Beta. For the junction-fieldeffect transistor Beta is defined by, IDSS, Beta , 2, Vp, , (5.15), , The parameter Vto 3 defines VGS VP 3 V as the pinch-off voltage—, something to check when we obtain our characteristics. Choosing the Setup Analysis, icon (recall that it has the horizontal blue line at the top), the DC Sweep is first enabled, and then activated to produce the DC Sweep dialog box. Select Voltage SourceLinear, and insert the Name: VDD, the Start Value of 0 V, End Value of 10 V, and, Increment of 0.01 V. Then, the Nested Sweep is chosen, and Voltage and Linear are, chosen once more. Finally, the Name: VGG is entered, the Start Value of 0 V is chosen, the End Value of 5 V is entered, and the Increment is set at 1 V. Then, be, sure to Enable Nested Sweep before clicking on OK and closing. With the Automatically run Probe after Simulation enabled, clicking on the analysis icon will result in, the OrCAD-MicroSim Probe screen. There is no need to call up the X-Axis Settings, because the horizontal axis has the correct range and the voltage VDD is actually the, drain-to-source voltage. By choosing the Trace icon, the Add Traces dialog box will, appear. ID(J1) is chosen, followed by OK. The result is the set of characteristics appearing in Fig. 5.47. The remaining labels were added using the ABC icon., Note that the pinch-off voltage is 3 V, as expected by the Vto parameter. The, value of IDSS is very close to 12 mA., , Figure 5.46 Network employed, to obtain the characteristics of the, n-channel J2N3819 JFET., , Figure 5.47 Drain characteristics for the n-channel J2N3819 JFET of Figure 5.46., , 5.13 PSpice Windows, , 247
Page 259 :
The transfer characteristics can be obtained by returning to the network configuration and choosing the Analysis-Setup icon. The DC Sweep is again enabled, and, the DC Sweep is chosen. This time, since the result will only be one curve, a nested, operation will not be performed. After choosing Voltage Source and Linear, the Name, will be VGG, the Start Value 3 V (since we now know that VP 3 V), the End, Value 0 V, and the Increment 0.01 V to get a good continuous plot. After an OK followed by a Close, the Simulation icon can be chosen. Once the Probe screen appears, choose Plot-X-Axis Settings-Axis Variable and choose V(J1:g) for the gateto-source voltage. Choose OK and we’re back to the X-Axis Settings dialog box to, choose the User Defined range of 3 V to 0 V (which already appears because of, our sweep settings). Choose OK again and the Trace ID(J1) can be chosen to result, in the transfer characteristics of Fig. 5.48., , Figure 5.48 Transfer characteristics for the n-channel J2N3819 JFET of Figure 5.46., , 248, , Chapter 5, , Field-Effect Transistors
Page 260 :
PROBLEMS, , § 5.2 Construction and Characteristics of JFETs, 1. (a) Draw the basic construction of a p-channel JFET., (b) Apply the proper biasing between drain and source and sketch the depletion region for, VGS 0 V., 2. Using the characteristics of Fig. 5.10, determine ID for the following levels of VGS (with, VDS VP)., (a) VGS 0 V., (b) VGS 1 V., (c) VGS 1.5 V., (d) VGS 1.8 V., (e) VGS 4 V., (f) VGS 6 V., 3. (a) Determine VDS for VGS 0 V and ID 6 mA using the characteristics of Fig. 5.10., (b) Using the results of part (a), calculate the resistance of the JFET for the region ID 0 to, 6 mA for VGS 0 V., (c) Determine VDS for VGS 1 V and ID 3 mA., (d) Using the results of part (c), calculate the resistance of the JFET for the region ID 0 to, 3 mA for VGS 1 V., (e) Determine VDS for VGS 2 V and ID 1.5 mA., (f) Using the results of part (e), calculate the resistance of the JFET for the region ID 0 to, 1.5 mA for VGS 2 V., (g) Defining the result of part (b) as ro, determine the resistance for VGS 1 V using Eq., (5.1) and compare with the results of part (d)., (h) Repeat part (g) for VGS 2 V using the same equation, and compare the results with part, (f)., (i) Based on the results of parts (g) and (h), does Eq. (5.1) appear to be a valid approximation?, 4. Using the characteristics of Fig. 5.10:, (a) Determine the difference in drain current (for VDS VP) between VGS 0 V and VGS , 1 V., (b) Repeat part (a) between VGS 1 and 2 V., (c) Repeat part (a) between VGS 2 and 3 V., (d) Repeat part (a) between VGS 3 and 4 V., (e) Is there a marked change in the difference in current levels as VGS becomes increasingly, negative?, (f) Is the relationship between the change in VGS and the resulting change in ID linear or nonlinear? Explain., 5. What are the major differences between the collector characteristics of a BJT transistor and the, drain characteristics of a JFET transistor? Compare the units of each axis and the controlling, variable. How does IC react to increasing levels of IB versus changes in ID to increasingly negative values of VGS? How does the spacing between steps of IB compare to the spacing between, steps of VGS? Compare VCsat to VP in defining the nonlinear region at low levels of output voltage., 6. (a) Describe in your own words why IG is effectively zero amperes for a JFET transistor., (b) Why is the input impedance to a JFET so high?, (c) Why is the terminology field effect appropriate for this important three-terminal device?, 7. Given IDSS 12 mA and VP 6 V, sketch a probable distribution of characteristic curves for, the JFET (similar to Fig. 5.10)., 8. In general, comment on the polarity of the various voltages and direction of the currents for an, n-channel JFET versus a p-channel JFET., , § 5.3 Transfer Characteristics, 9. Given the characteristics of Fig. 5.49:, (a) Sketch the transfer characteristics directly from the drain characteristics., (b) Using Fig. 5.49 to establish the values of IDSS and VP, sketch the transfer characteristics, using Shockley’s equation., (c) Compare the characteristics of parts (a) and (b). Are there any major differences?, Problems, , 249
Page 261 :
Figure 5.49 Problems 9, 17, , 10. (a) Given IDSS 12 mA and VP 4 V, sketch the transfer characteristics for the JFET transistor., (b) Sketch the drain characteristics for the device of part (a)., 11. Given IDSS 9 mA and VP 3.5 V, determine ID when:, (a) VGS 0 V., (b) VGS 2 V., (c) VGS 3.5 V., (d) VGS 5 V., 12. Given IDSS 16 mA and VP 5 V, sketch the transfer characteristics using the data points, of Table 5.1. Determine the value of ID at VGS 3 V from the curve, and compare it to the, value determined using Shockley’s equation. Repeat the above for VGS 1 V., 13. A p-channel JFET has device parameters of IDSS 7.5 mA and VP 4 V. Sketch the transfer, characteristics., 14. Given IDSS 6 mA and VP 4.5 V:, (a) Determine ID at VGS 2 and 3.6 V., (b) Determine VGS at ID 3 and 5.5 mA., 15. Given a Q-point of IDQ 3 mA and VGS 3 V, determine IDSS if VP 6 V., , § 5.4 Specification Sheets (JFETs), 16. Define the region of operation for the 2N5457 JFET of Fig. .5.18 using the range of IDSS and, VP provided. That is, sketch the transfer curve defined by the maximum IDSS and VP and the, transfer curve for the minimum IDSS and VP. Then, shade in the resulting area between the two, curves., 17. Define the region of operation for the JFET of Fig. 5.49 if VDSmax 25 V and PDmax 120 mW., , § 5.5 Instrumentation, 18. Using the characteristics of Fig. 5.21, determine ID at VGS 0.7 V and VDS 10 V., 19. Referring to Fig. 5.21, is the locus of pinch-off values defined by the region of VDS VP 3 V?, 20. Determine VP for the characteristics of Fig. 5.21 using IDSS and ID at some value of VGS. That, is, simply substitute into Shockley’s equation and solve for VP. Compare the result to the assumed value of 3 V from the characteristics., , 250, , Chapter 5, , Field-Effect Transistors
Page 262 :
21. Using IDSS 9 mA and VP 3 V for the characteristics of Fig. 5.21, calculate ID at VGS , 1 V using Shockley’s equation and compare to the level appearing in Fig. 5.21., 22. (a) Calculate the resistance associated with the JFET of Fig. 5.21 for VGS 0 V from ID , 0 to 4 mA., (b) Repeat part (a) for VGS 0.5 V from ID 0 to 3 mA., (c) Assigning the label ro to the result of part (a) and rd to that of part (b), use Eq. (5.1) to determine rd and compare to the result of part (b)., , § 5.7 Depletion-Type MOSFET, 23. (a) Sketch the basic construction of a p-channel depletion-type MOSFET., (b) Apply the proper drain-to-source voltage and sketch the flow of electrons for VGS 0 V., 24. In what ways is the construction of a depletion-type MOSFET similar to that of a JFET? In, what ways is it different?, 25. Explain in your own words why the application of a positive voltage to the gate of an n-channel depletion-type MOSFET will result in a drain current exceeding IDSS., 26. Given a depletion-type MOSFET with IDSS 6 mA and VP 3 V, determine the drain current at VGS 1, 0, 1, and 2 V. Compare the difference in current levels between 1 and 0 V, with the difference between 1 and 2 V. In the positive VGS region, does the drain current increase at a significantly higher rate than for negative values? Does the ID curve become more, and more vertical with increasing positive values of VGS? Is there a linear or a nonlinear relationship between ID and VGS? Explain., 27. Sketch the transfer and drain characteristics of an n-channel depletion-type MOSFET with, IDSS 12 mA and VP 8 V for a range of VGS VP to VGS 1 V., 28. Given ID 14 mA and VGS 1 V, determine VP if IDSS 9.5 mA for a depletion-type MOSFET., 29. Given ID 4 mA at VGS 2 V, determine IDSS if VP 5 V., 30. Using an average value of 2.9 mA for the IDSS of the 2N3797 MOSFET of Fig. 5.30, determine the level of VGS that will result in a maximum drain current of 20 mA if VP 5 V., 31. If the drain current for the 2N3797 MOSFET of Fig. 5.30 is 8 mA, what is the maximum permissible value of VDS utilizing the maximum power rating?, , § 5.8 Enhancement-Type MOSFET, 32. (a) What is the significant difference between the construction of an enhancement-type MOSFET and a depletion-type MOSFET?, (b) Sketch a p-channel enhancement-type MOSFET with the proper biasing applied (VDS , 0 V, VGS VT) and indicate the channel, the direction of electron flow, and the resulting, depletion region., (c) In your own words, briefly describe the basic operation of an enhancement-type MOSFET., 33. (a) Sketch the transfer and drain characteristics of an n-channel enhancement-type MOSFET, if VT 3.5 V and k 0.4 103 A/V2., (b) Repeat part (a) for the transfer characteristics if VT is maintained at 3.5 V but k is increased, by 100% to 0.8 103 A/V2., 34. (a) Given VGS(Th) 4 V and ID(on) 4 mA at VGS(on) 6 V, determine k and write the general expression for ID in the format of Eq. (5.13)., (b) Sketch the transfer characteristics for the device of part (a)., (c) Determine ID for the device of part (a) at VGS 2, 5, and 10 V., 35. Given the transfer characteristics of Fig. 5.50, determine VT and k and write the general equation for ID., 36. Given k 0.4 103 A/V2 and ID(on) 3 mA with VGS(on) 4 V, determine VT., 37. The maximum drain current for the 2N4351 n-channel enhancement-type MOSFET is 30 mA., Determine VGS at this current level if k 0.06 103 A/V2 and VT is the maximum value., Problems, , 251
Page 263 :
Figure 5.50 Problem 35, , 38. Does the current of an enhancement-type MOSFET increase at about the same rate as a, depletion-type MOSFET for the conduction region? Carefully review the general format of the, equations, and if your mathematics background includes differential calculus, calculate dID /dVGS, and compare its magnitude., 39. Sketch the transfer characteristics of a p-channel enhancement-type MOSFET if VT 5 V, and k 0.45 103 A/V2., 40. Sketch the curve of ID 0.5 103(V 2GS) and ID 0.5 103(VGS 4)2 for VGS from 0 to, 10 V. Does VT 4 V have a significant impact on the level of ID for this region?, , § 5.10 VMOS, 41. (a) Describe in your own words why the VMOS FET can withstand a higher current and power, rating than the standard construction technique., (b) Why do VMOS FETs have reduced channel resistance levels?, (c) Why is a positive temperature coefficient desirable?, , § 5.11 CMOS, * 42. (a) Describe in your own words the operation of the network of Fig. 5.44 with Vi 0 V., (b) If the “on” MOSFET of Fig. 5.44 (with Vi 0 V) has a drain current of 4 mA with, VDS 0.1 V, what is the approximate resistance level of the device? If ID 0.5 A for the, “off” transistor, what is the approximate resistance of the device? Do the resulting resistance levels suggest that the desired output voltage level will result?, 43. Research CMOS logic at your local or college library, and describe the range of applications, and basic advantages of the approach., *Please Note: Asterisks indicate more difficult problems., , 252, , Chapter 5, , Field-Effect Transistors
Page 264 :
CHAPTER, , FET Biasing, , 6, , 6.1 INTRODUCTION, In Chapter 5 we found that the biasing levels for a silicon transistor configuration can, be obtained using the characteristic equations VBE 0.7 V, IC IB, and IC ≅ IE. The, linkage between input and output variables is provided by , which is assumed to be, fixed in magnitude for the analysis to be performed. The fact that beta is a constant, establishes a linear relationship between IC and IB. Doubling the value of IB will double the level of IC, and so on., For the field-effect transistor, the relationship between input and output quantities, is nonlinear due to the squared term in Shockley’s equation. Linear relationships result in straight lines when plotted on a graph of one variable versus the other, while, nonlinear functions result in curves as obtained for the transfer characteristics of a, JFET. The nonlinear relationship between ID and VGS can complicate the mathematical approach to the dc analysis of FET configurations. A graphical approach may, limit solutions to tenths-place accuracy, but it is a quicker method for most FET amplifiers. Since the graphical approach is in general the most popular, the analysis of, this chapter will have a graphical orientation rather than direct mathematical techniques., Another distinct difference between the analysis of BJT and FET transistors is, that the input controlling variable for a BJT transistor is a current level, while for the, FET a voltage is the controlling variable. In both cases, however, the controlled variable on the output side is a current level that also defines the important voltage levels of the output circuit., The general relationships that can be applied to the dc analysis of all FET amplifiers are, IG ≅ 0 A, , (6.1), , ID IS, , (6.2), , and, , For JFETS and depletion-type MOSFETs, Shockley’s equation is applied to relate the input and output quantities:, 1 VGS, ID IDSS , VP, , , , , , 2, , (6.3), , 253
Page 265 :
For enhancement-type MOSFETs, the following equation is applicable:, ID k(VGS VT)2, , (6.4), , It is particularly important to realize that all of the equations above are for the device only! They do not change with each network configuration so long as the device, is in the active region. The network simply defines the level of current and voltage, associated with the operating point through its own set of equations. In reality, the dc, solution of BJT and FET networks is the solution of simultaneous equations established by the device and network. The solution can be determined using a mathematical or graphical approach—a fact to be demonstrated by the first few networks, to be analyzed. However, as noted earlier, the graphical approach is the most popular for FET networks and is employed in this book., The first few sections of this chapter are limited to JFETs and the graphical approach to analysis. The depletion-type MOSFET will then be examined with its increased range of operating points, followed by the enhancement-type MOSFET., Finally, problems of a design nature are investigated to fully test the concepts and, procedures introduced in the chapter., , 6.2 FIXED-BIAS CONFIGURATION, The simplest of biasing arrangements for the n-channel JFET appears in Fig. 6.1. Referred to as the fixed-bias configuration, it is one of the few FET configurations that, can be solved just as directly using either a mathematical or graphical approach. Both, methods are included in this section to demonstrate the difference between the two, philosophies and also to establish the fact that the same solution can be obtained using either method., The configuration of Fig. 6.1 includes the ac levels Vi and Vo and the coupling, capacitors (C1 and C2). Recall that the coupling capacitors are “open circuits” for the, dc analysis and low impedances (essentially short circuits) for the ac analysis. The, resistor RG is present to ensure that Vi appears at the input to the FET amplifier for, the ac analysis (Chapter 9). For the dc analysis,, IG ≅ 0 A, VRG IGRG (0 A)RG 0 V, , and, , The zero-volt drop across RG permits replacing RG by a short-circuit equivalent, as, appearing in the network of Fig. 6.2 specifically redrawn for the dc analysis., , Figure 6.1 Fixed-bias configuration., , 254, , Chapter 6, , FET Biasing, , Figure 6.2, , Network for dc analysis.
Page 266 :
The fact that the negative terminal of the battery is connected directly to the defined positive potential of VGS clearly reveals that the polarity of VGS is directly opposite to that of VGG. Applying Kirchhoff’s voltage law in the clockwise direction of, the indicated loop of Fig. 6.2 will result in, VGG VGS 0, VGS VGG, , and, , (6.5), , Since VGG is a fixed dc supply, the voltage VGS is fixed in magnitude, resulting in the, notation “fixed-bias configuration.”, The resulting level of drain current ID is now controlled by Shockley’s equation:, , , , V, ID IDSS 1 GS, VP, , , , 2, , Since VGS is a fixed quantity for this configuration, its magnitude and sign can, simply be substituted into Shockley’s equation and the resulting level of ID calculated., This is one of the few instances in which a mathematical solution to a FET configuration is quite direct., A graphical analysis would require a plot of Shockley’s equation as shown in Fig., 6.3. Recall that choosing VGS VP/2 will result in a drain current of IDSS/4 when plotting the equation. For the analysis of this chapter, the three points defined by IDSS,, VP, and the intersection just described will be sufficient for plotting the curve., ID (mA), IDSS, , IDSS, 4, , VP, , VP, 2, , 0, , VGS, , Figure 6.3, equation., , Plotting Shockley’s, , In Fig. 6.4, the fixed level of VGS has been superimposed as a vertical line at, VGS VGG. At any point on the vertical line, the level of VGS is VGG —the level, of ID must simply be determined on this vertical line. The point where the two curves, ID (mA), Device, , IDSS, , Network, Q-point, (solution), , VP, , VGSQ = –VGG, , ID, , 0, , Q, , VGS, , Figure 6.4 Finding the solution, for the fixed-bias configuration., , 6.2, , Fixed-Bias Configuration, , 255
Page 267 :
intersect is the common solution to the configuration—commonly referred to as the, quiescent or operating point. The subscript Q will be applied to drain current and, gate-to-source voltage to identify their levels at the Q-point. Note in Fig. 6.4 that the, quiescent level of ID is determined by drawing a horizontal line from the Q-point to, the vertical ID axis as shown in Fig. 6.4. It is important to realize that once the network of Fig. 6.1 is constructed and operating, the dc levels of ID and VGS that will be, measured by the meters of Fig. 6.5 are the quiescent values defined by Fig. 6.4., , Figure 6.5 Measuring the quiescent values of ID and VGS., , The drain-to-source voltage of the output section can be determined by applying, Kirchhoff’s voltage law as follows:, VDS ID RD VDD 0, VDS VDD IDRD, , and, , (6.6), , Recall that single-subscript voltages refer to the voltage at a point with respect to, ground. For the configuration of Fig. 6.2,, VS 0 V, , (6.7), , Using double-subscript notation:, VDS VD VS, VD VDS VS VDS 0 V, , or, , VD VDS, , and, In addition,, , (6.8), , VGS VG VS, VG VGS VS VGS 0 V, , or, , VG VGS, , and, , (6.9), , The fact that VD VDS and VG VGS is fairly obvious from the fact that VS , 0 V, but the derivations above were included to emphasize the relationship that exists, between double-subscript and single-subscript notation. Since the configuration requires two dc supplies, its use is limited and will not be included in the forthcoming, list of the most common FET configurations., 256, , Chapter 6, , FET Biasing
Page 268 :
EXAMPLE 6.1, , Determine the following for the network of Fig. 6.6., (a) VGSQ., 16 V, (b) IDQ., (c) VDS., (d) VD., 2 kΩ, (e) VG., (f) VS., D, G, , I DSS = 10 mA, VP = –8 V, , +, 1 MΩ, , –, , VGS, , –, , S, , 2V, , +, Figure 6.6 Example 6.1., , Solution, Mathematical Approach:, , (a) VGSQ VGG 2 V, V 2, 2 V 2, (b) IDQ IDSS 1 GS 10 mA 1 , VP, 8 V, 2, 10 mA(1 0.25) 10 mA(0.75)2 10 mA(0.5625), 5.625 mA, (c) VDS VDD IDRD 16 V (5.625 mA)(2 k), 16 V 11.25 V 4.75 V, (d) VD VDS 4.75 V, (e) VG VGS 2 V, (f) VS 0 V, , , , , , , , , , Graphical Approach:, , The resulting Shockley curve and the vertical line at VGS 2 V are provided in Fig., 6.7. It is certainly difficult to read beyond the second place without significantly inID (mA), IDSS = 10 mA, 9, 8, 7, Q-point, , 6, 5, , I D = 5.6 mA, Q, , 4, 3, 2, , IDSS = 2.5 mA, 4, , 1, –8 –7 – 6 – 5 – 4 – 3 –2 –1, 0, VGS, VP = –8 V VP, V, =, –V, =, –2, V, GSQ, GG, = –4 V, 2, , Figure 6.7 Graphical solution, for the network of Fig. 6.6., , 6.2, , Fixed-Bias Configuration, , 257
Page 269 :
creasing the size of the figure, but a solution of 5.6 mA from the graph of Fig. 6.7 is, quite acceptable. Therefore, for part (a),, VGSQ VGG 2 V, (b) IDQ 5.6 mA, (c) VDS VDD IDRD 16 V (5.6 mA)(2 k), 16 V 11.2 V 4.8 V, (d) VD VDS 4.8 V, (e) VG VGS 2 V, (f) VS 0 V, The results clearly confirm the fact that the mathematical and graphical approaches, generate solutions that are quite close., , 6.3 SELF-BIAS CONFIGURATION, The self-bias configuration eliminates the need for two dc supplies. The controlling, gate-to-source voltage is now determined by the voltage across a resistor RS introduced in the source leg of the configuration as shown in Fig. 6.8., , Figure 6.8, figuration., , JFET self-bias con-, , For the dc analysis, the capacitors can again be replaced by “open circuits” and, the resistor RG replaced by a short-circuit equivalent since IG 0 A. The result is the, network of Fig. 6.9 for the important dc analysis., The current through RS is the source current IS, but IS ID and, VRS IDRS, For the indicated closed loop of Fig. 6.9, we find that, VGS VRS 0, and, , VGS VRS, , or, , VGS IDRS, , (6.10), , Figure 6.9 DC analysis of the, self-bias configuration., , Note in this case that VGS is a function of the output current ID and not fixed in magnitude as occurred for the fixed-bias configuration., , 258, , Chapter 6, , FET Biasing
Page 270 :
Equation (6.10) is defined by the network configuration, and Shockley’s equation, relates the input and output quantities of the device. Both equations relate the same, two variables, permitting either a mathematical or graphical solution., A mathematical solution could be obtained simply by substituting Eq. (6.10) into, Shockley’s equation as shown below:, , , , V, ID IDSS 1 GS, VP, , , , 2, , I RS, IDSS 1 D, VP, , , , or, , , , , , 2, , , , IDRS, ID IDSS 1 , , VP, , 2, , By performing the squaring process indicated and rearranging terms, an equation of, the following form can be obtained:, ID2 K1ID K2 0, The quadratic equation can then be solved for the appropriate solution for ID., The sequence above defines the mathematical approach. The graphical approach, requires that we first establish the device transfer characteristics as shown in Fig. 6.10., Since Eq. (6.10) defines a straight line on the same graph, let us now identify two, points on the graph that are on the line and simply draw a straight line between the, two points. The most obvious condition to apply is ID 0 A since it results in, VGS IDRS (0 A)RS 0 V. For Eq. (6.10), therefore, one point on the straight, line is defined by ID 0 A and VGS 0 V, as appearing on Fig. 6.10., , Figure 6.10 Defining a point, on the self-bias line., , The second point for Eq. (6.10) requires that a level of VGS or ID be chosen and, the corresponding level of the other quantity be determined using Eq. (6.10). The resulting levels of ID and VGS will then define another point on the straight line and permit an actual drawing of the straight line. Suppose, for example, that we choose a, level of ID equal to one-half the saturation level. That is,, I SS, ID D, 2, then, , IDSSRS, VGS IDRS , , 2, , The result is a second point for the straight-line plot as shown in Fig. 6.11. The straight, line as defined by Eq. (6.10) is then drawn and the quiescent point obtained at the in6.3, , Self-Bias Configuration, , 259
Page 272 :
Solution, (a) The gate-to-source voltage is determined by, VGS IDRS, Choosing ID 4 mA, we obtain, VGS (4 mA)(1 k) 4 V, The result is the plot of Fig. 6.13 as defined by the network., ID = 8 mA, VGS = –8 V, , ID (mA), 8, 7, , ID = 4 mA, VGS = – 4V, Network, , 6, 5, 4, 3, 2, 1 V = 0 V, I = 0 mA, GS, D, , – 8 –7 – 6 – 5 – 4 – 3 –2 – 1, , 0, , VGS (V), , Figure 6.13 Sketching the selfbias line for the network of Fig., 6.12., , If we happen to choose ID 8 mA, the resulting value of VGS would be 8 V, as, shown on the same graph. In either case, the same straight line will result, clearly, demonstrating that any appropriate value of ID can be chosen as long as the corresponding value of VGS as determined by Eq. (6.10) is employed. In addition, keep in, mind that the value of VGS could be chosen and the value of ID calculated with the, same resulting plot., For Shockley’s equation, if we choose VGS VP/2 3 V, we find that ID , IDSS/4 8 mA/4 2 mA, and the plot of Fig. 6.14 will result, representing the characteristics of the device. The solution is obtained by superimposing the network characteristics defined by Fig. 6.13 on the device characteristics of Fig. 6.14 and finding, the point of intersection of the two as indicated on Fig. 6.15. The resulting operating, point results in a quiescent value of gate-to-source voltage of, VGSQ 2.6 V, ID (mA), 8, 7, 6, 5, 4, 3, Q-point, 2, , I D = 2.6 mA, Q, , 1, – 6 – 5 – 4 – 3 –2 –1, , 0, , VGS (V), , VGSQ = – 2.6 V, , Figure 6.14 Sketching the device characteristics for the JFET of Fig. 6.12., , Figure 6.15 Determining the Q-point for the, network of Fig. 6.12., , 6.3, , Self-Bias Configuration, , 261
Page 273 :
(b) At the quiescent point:, IDQ 2.6 mA, (c) Eq. (6.11): VDS VDD ID(RS RD), 20 V (2.6 mA)(1 k 3.3 k), 20 V 11.18 V, 8.82 V, (d) Eq. (6.12): VS IDRS, (2.6 mA)(1 k), 2.6 V, (e) Eq. (6.13): VG 0 V, (f) Eq. (6.14): VD VDS VS 8.82 V 2.6 V 11.42 V, or, VD VDD IDRD 20 V (2.6 mA)(3.3 k) 11.42 V, , EXAMPLE 6.3, , Find the quiescent point for the network of Fig. 6.12 if:, (a) RS 100 ., (b) RS 10 k., , Solution, Note Fig. 6.16., ID (mA), 8, RS = 100 Ω, I D = 4 mA, VGS = – 0.4 V, , 7, Q-point, , 6, , I D ≅ 6.4 mA, Q, , 5, 4, , RS = 10 kΩ, VGS = –4 V, ID = 0.4 mA, , 3, 2, , Q-point, , 1, , – 6 – 5 – 4 – 3 –2 –1, , 0, , VGS (V), , VGSQ ≅ – 4.6 V, , Figure 6.16 Example 6.3., , (a) With the ID scale,, IDQ ≅ 6.4 mA, From Eq. (6.10),, VGSQ ≅ 0.64 V, (b) With the VGS scale,, VGSQ ≅ 4.6 V, From Eq. (6.10),, IDQ ≅ 0.46 mA, In particular, note how lower levels of RS bring the load line of the network closer, to the ID axis while increasing levels of RS bring the load line closer to the VGS axis., 262, , Chapter 6, , FET Biasing
Page 274 :
Determine the following for the common-gate configuration of Fig. 6.17., (a) VGSQ., (b) IDQ., (c) VD., (d) VG., (e) VS., (f) VDS., , EXAMPLE 6.4, , Figure 6.17 Example 6.4., , Solution, The grounded gate terminal and the location of the input establish strong similarities, with the common-base BJT amplifier. Although different in appearance from the basic structure of Fig. 6.8, the resulting dc network of Fig. 6.18 has the same basic structure as Fig. 6.9. The dc analysis can therefore proceed in the same manner as recent, examples., (a) The transfer characteristics and load line appear in Fig. 6.19. In this case, the second point for the sketch of the load line was determined by choosing (arbitrarily), ID 6 mA and solving for VGS. That is,, VGS IDRS (6 mA)(680 ) 4.08 V, as shown in Fig. 6.19. The device transfer curve was sketched using, I SS, 12 mA, 3 mA, ID D, 4, 4, ID (mA), , Figure 6.18 Sketching the dc, equivalent of the network of Fig., 6.17., , 12 I DSS, 11, 10, 9, 8, 7, 6, 5, 4, , Q-point, , 3, , I D ≅ 3.8 mA, Q, , 2, 1, –6, VP, , –5, , –4, , –3, , –2, –1, VGSQ ≅ –2.6 V, , 0, , Figure 6.19 Determining the, Q-point for the network of Fig., 6.17., , 6.3, , Self-Bias Configuration, , 263
Page 275 :
and the associated value of VGS:, VP, 6V, VGS , 3 V, 2, 2, as shown on Fig. 6.19. Using the resulting quiescent point of Fig. 6.19 results in, VGSQ ≅ 2.6 V, (b) From Fig. 6.19,, IDQ ≅ 3.8 mA, (c) VD VDD IDRD, 12 V (3.8 mA)(1.5 k) 12 V 5.7 V, 6.3 V, (d) VG 0 V, (e) VS IDRS (3.8 mA)(680 ), 2.58 V, (f) VDS VD VS, 6.3 V 2.58 V, 3.72 V, , 6.4 VOLTAGE-DIVIDER BIASING, The voltage-divider bias arrangement applied to BJT transistor amplifiers is also applied to FET amplifiers as demonstrated by Fig. 6.20. The basic construction is exactly the same, but the dc analysis of each is quite different. IG 0 A for FET amplifiers, but the magnitude of IB for common-emitter BJT amplifiers can affect the dc, levels of current and voltage in both the input and output circuits. Recall that IB provided the link between input and output circuits for the BJT voltage-divider configuration while VGS will do the same for the FET configuration., The network of Fig. 6.20 is redrawn as shown in Fig. 6.21 for the dc analysis., Note that all the capacitors, including the bypass capacitor CS, have been replaced by, an “open-circuit” equivalent. In addition, the source VDD was separated into two equivVDD, , R1, , VDD, , VDD, , RD, , R1, , ID, IG ≅ 0 A, VG, , +, , +, R2, , –, , +, R2, , VG, , –, , VGS, , –, +, VRS, , IS, , RS, , –, Figure 6.21 Redrawn network of Fig. 6.20 for dc analysis., , Figure 6.20 Voltage-divider bias arrangement., , 264, , Chapter 6, , FET Biasing
Page 276 :
alent sources to permit a further separation of the input and output regions of the network. Since IG 0 A, Kirchhoff’s current law requires that IR1 IR2 and the series, equivalent circuit appearing to the left of the figure can be used to find the level of, VG. The voltage VG, equal to the voltage across R2, can be found using the voltagedivider rule as follows:, R2VDD, , VG , R1 R2, , (6.15), , Applying Kirchhoff’s voltage law in the clockwise direction to the indicated loop, of Fig. 6.21 will result in, VG VGS VRS 0, and, , VGS VG VRS, , Substituting VRS ISRS ID RS, we have, VGS VG IDRS, , (6.16), , The result is an equation that continues to include the same two variables appearing in Shockley’s equation: VGS and ID. The quantities VG and RS are fixed by, the network construction. Equation (6.16) is still the equation for a straight line, but, the origin is no longer a point in the plotting of the line. The procedure for plotting, Eq. (6.16) is not a difficult one and will proceed as follows. Since any straight line, requires two points to be defined, let us first use the fact that anywhere on the horizontal axis of Fig. 6.22 the current ID 0 mA. If we therefore select ID to be 0 mA,, we are in essence stating that we are somewhere on the horizontal axis. The exact location can be determined simply by substituting ID 0 mA into Eq. (6.16) and finding the resulting value of VGS as follows:, VGS VG IDRS, VG (0 mA)RS, and, , VGS VGID0 mA, , (6.17), , The result specifies that whenever we plot Eq. (6.16), if we choose ID 0 mA, the, value of VGS for the plot will be VG volts. The point just determined appears in Fig., 6.22., , Figure 6.22 Sketching the network equation for the voltage-divider configuration., , 6.4, , Voltage-Divider Biasing, , 265
Page 277 :
For the other point, let us now employ the fact that at any point on the vertical, axis VGS 0 V and solve for the resulting value of ID:, VGS VG IDRS, 0 V VG IDRS, VG, ID , RS, , and, , , , VGS 0 V, , (6.18), , The result specifies that whenever we plot Eq. (6.16), if VGS 0 V, the level of ID is, determined by Eq. (6.18). This intersection also appears on Fig. 6.22., The two points defined above permit the drawing of a straight line to represent, Eq. (6.16). The intersection of the straight line with the transfer curve in the region, to the left of the vertical axis will define the operating point and the corresponding, levels of ID and VGS., Since the intersection on the vertical axis is determined by ID VG/RS and VG is, fixed by the input network, increasing values of RS will reduce the level of the ID intersection as shown in Fig. 6.23. It is fairly obvious from Fig. 6.23 that:, Increasing values of RS result in lower quiescent values of ID and more negative values of VGS., , Figure 6.23 Effect of RS on the resulting Q-point., , Once the quiescent values of IDQ and VGSQ are determined, the remaining network, analysis can be performed in the usual manner. That is,, , 266, , Chapter 6, , FET Biasing, , VDS VDD ID(RD RS), , (6.19), , VD VDD IDRD, , (6.20), , VS IDRS, , (6.21), , V, , IR1 IR2 DD, R1 R2, , (6.22)
Page 278 :
Determine the following for the network of Fig. 6.24., (a) IDQ and VGSQ., (b) VD., (c) VS., (d) VDS., (e) VDG., , EXAMPLE 6.5, , Figure 6.24 Example 6.5., , Solution, (a) For the transfer characteristics, if ID IDSS/4 8 mA/4 2 mA, then VGS , VP/2 4 V/2 2 V. The resulting curve representing Shockley’s equation appears in Fig. 6.25. The network equation is defined by, R2VDD, VG , , R1 R2, (270 k)(16 V), , 2.1 M 0.27 M, 1.82 V, VGS VG IDRS, , and, , 1.82 V ID(1.5 k), When ID 0 mA:, VGS 1.82 V, ID (mA), 8 (IDSS ), 7, 6, 5, 4, 3, Q-point, , 2, 1, , –4, , (VP), , –3, , –2, –1, 0, VGSQ = –1.8 V, , I D = 2.4 mA, Q, , I D =1.21 mA ( VGS = 0 V), 1, , 2, 3, VG = 1.82 V, ( I D = 0 mA ), , Figure 6.25 Determining the, Q-point for the network of Fig., 6.24., , 6.4, , Voltage-Divider Biasing, , 267
Page 279 :
When VGS 0 V:, 1.82 V, ID 1.21 mA, 1.5 k, The resulting bias line appears on Fig. 6.25 with quiescent values of, IDQ 2.4 mA, VGSQ 1.8 V, , and, (b) VD VDD IDRD, 16 V (2.4 mA)(2.4 k), 10.24 V, (c) VS IDRS (2.4 mA)(1.5 k), 3.6 V, , (d) VDS VDD ID(RD RS), 16 V (2.4 mA)(2.4 k 1.5 k), 6.64 V, or VDS VD VS 10.24 V 3.6 V, 6.64 V, (e) Although seldom requested, the voltage VDG can easily be determined using, VDG VD VG, 10.24 V 1.82 V, 8.42 V, , Although the basic construction of the network in the next example is quite different from the voltage-divider bias arrangement, the resulting equations require a solution very similar to that just described. Note that the network employs a supply at, the drain and source., , EXAMPLE 6.6, , Determine the following for the network of Fig. 6.26., (a) IDQ and VGSQ., (b) VDS., VDD = 20 V, (c) VD., ID, (d) VS., R D = 1.8 k Ω, , I DSS = 9 mA, VP = –3 V, , RS = 1.5 kΩ, , VSS = –10 V, , 268, , Chapter 6, , FET Biasing, , Figure 6.26 Example 6.6.
Page 280 :
Solution, (a) An equation for VGS in terms of ID is obtained by applying Kirchhoff’s voltage, law to the input section of the network as redrawn in Fig. 6.27., VGS ISRS VSS 0, or, , VGS VSS ISRS, , but, , IS ID, , and, , VGS VSS IDRS, , (6.23), , The result is an equation very similar in format to Eq. (6.16) that can be superimposed on the transfer characteristics using the procedure described for Eq. (6.16)., That is, for this example,, Figure 6.27 Determining the, network equation for the configuration of Fig. 6.26., , VGS 10 V ID(1.5 k), For ID 0 mA,, VGS VSS 10 V, For VGS 0 V,, 0 10 V ID(1.5 k), and, , 10 V, ID 6.67 mA, 1.5 k, , The resulting plot points are identified on Fig. 6.28., , Figure 6.28 Determining the, Q-point for the network of Fig., 6.26., , The transfer characteristics are sketched using the plot point established by VGS , VP/2 3 V/2 1.5 V and ID IDSS/4 9 mA/4 2.25 mA, as also appearing, on Fig. 6.28. The resulting operating point establishes the following quiescent levels:, IDQ 6.9 mA, VGSQ 0.35 V, (b) Applying Kirchhoff’s voltage law to the output side of Fig. 6.26 will result in, VSS ISRS VDS IDRD VDD 0, 6.4, , Voltage-Divider Biasing, , 269
Page 281 :
Substituting IS ID and rearranging gives, VDS VDD VSS ID(RD RS), , (6.24), , which for this example results in, VDS 20 V 10 V (6.9 mA)(1.8 k 1.5 k), 30 V 22.77 V, 7.23 V, (c) VD VDD IDRD, 20 V (6.9 mA)(1.8 k) 20 V 12.42 V, 7.58 V, (d) VDS VD VS, or VS VD VDS, 7.58 V 7.23 V, 0.35 V, , 6.5 DEPLETION-TYPE MOSFETs, The similarities in appearance between the transfer curves of JFETs and depletiontype MOSFETs permit a similar analysis of each in the dc domain. The primary difference between the two is the fact that depletion-type MOSFETs permit operating, points with positive values of VGS and levels of ID that exceed IDSS. In fact, for all, the configurations discussed thus far, the analysis is the same if the JFET is replaced, by a depletion-type MOSFET., The only undefined part of the analysis is how to plot Shockley’s equation for, positive values of VGS. How far into the region of positive values of VGS and values, of ID greater than IDSS does the transfer curve have to extend? For most situations,, this required range will be fairly well defined by the MOSFET parameters and the, resulting bias line of the network. A few examples will reveal the impact of the change, in device on the resulting analysis., , EXAMPLE 6.7, , For the n-channel depletion-type MOSFET of Fig. 6.29, determine:, (a) IDQ and VGSQ., (b) VDS., , Figure 6.29 Example 6.7., , 270
Page 282 :
Solution, (a) For the transfer characteristics, a plot point is defined by ID IDSS/4 6 mA/4 , 1.5 mA and VGS VP/2 3 V/2 1.5 V. Considering the level of VP and, the fact that Shockley’s equation defines a curve that rises more rapidly as VGS, becomes more positive, a plot point will be defined at VGS 1 V. Substituting, into Shockley’s equation yields, , , , V, ID IDSS 1 GS, VP, , , , 2, , 1 V, 6 mA 1 , 3 V, , , , , , 2, , , , , , 1, 6 mA 1 , 3, , 2, , 6 mA(1.778), , 10.67 mA, The resulting transfer curve appears in Fig. 6.30. Proceeding as described for JFETs,, we have:, Eq. (6.15):, , 10 M(18 V), VG 1.5 V, 10 M 110 M, , Eq. (6.16):, , VGS VG IDRS 1.5 V ID(750 ), , Figure 6.30 Determining the, Q-point for the network of Fig., 6.29., , Setting ID 0 mA results in, VGS VG 1.5 V, Setting VGS 0 V yields, VG, 1.5 V, ID , 2 mA, RS, 750 , The plot points and resulting bias line appear in Fig. 6.30. The resulting operating, point:, IDQ 3.1 mA, VGSQ 0.8 V, 6.5, , Depletion-Type MOSFETs, , 271
Page 283 :
(b) Eq. (6.19): VDS VDD ID(RD RS), 18 V (3.1 mA)(1.8 k 750 ), ≅ 10.1 V, , EXAMPLE 6.8, , Repeat Example 6.7 with RS 150 ., , Solution, (a) The plot points are the same for the transfer curve as shown in Fig. 6.31. For the, bias line,, VGS VG IDRS 1.5 V ID(150 ), , Figure 6.31 Example 6.8., , Setting ID 0 mA results in, VGS 1.5 V, Setting VGS 0 V yields, VG, 1.5 V, ID , 10 mA, RS, 150 , The bias line is included on Fig. 6.31. Note in this case that the quiescent point results in a drain current that exceeds IDSS, with a positive value for VGS. The result:, IDQ 7.6 mA, VGSQ 0.35 V, (b) Eq. (6.19): VDS VDD ID(RD RS), 18 V (7.6 mA)(1.8 k 150 ), 3.18 V, 272, , Chapter 6, , FET Biasing
Page 284 :
EXAMPLE 6.9, , Determine the following for the network of Fig. 6.32., (a) IDQ and VGSQ., (b) VD., , 20 V, , 6.2 kΩ, , Vo, I DSS = 8 mA, VP = – 8 V, , Vi, , 1 MΩ, , 2.4 kΩ, , Figure 6.32 Example 6.9., , Solution, (a) The self-bias configuration results in, VGS IDRS, as obtained for the JFET configuration, establishing the fact that VGS must be less, than zero volts. There is therefore no requirement to plot the transfer curve for positive values of VGS, although it was done on this occasion to complete the transfer, characteristics. A plot point for the transfer characteristics for VGS 0 V is, I SS, 8 mA, ID D, 2 mA, 4, 4, VP, 8 V, 4 V, VGS , 2, 2, , and, and for VGS, , 0 V, since VP 8 V, we will choose, VGS 2 V, , and, , , , V, ID IDSS 1 GS, VP, , , , 2, , 2 V, 8 mA 1 , 8 V, , , , , , 2, , 12.5 mA, The resulting transfer curve appears in Fig. 6.33. For the network bias line, at VGS , 0 V, ID 0 mA. Choosing VGS 6 V gives, V, 6 V, ID GS 2.5 mA, RS, 2.4 k, The resulting Q-point:, IDQ 1.7 mA, VGSQ 4.3 V, (b) VD VDD IDRD, 20 V (1.7 mA)(6.2 k), 9.46 V, 6.5, , Depletion-Type MOSFETs, , 273
Page 285 :
Figure 6.33 Determining the Qpoint for the network of Fig., 6.32., , The example to follow employs a design that can also be applied to JFET transistors. At first impression it appears rather simplistic, but in fact it often causes some, confusion when first analyzed due to the special point of operation., , EXAMPLE 6.10, , Determine VDS for the network of Fig. 6.34., , Solution, The direct connection between the gate and source terminals requires that, VGS 0 V, Since VGS is fixed at 0 V, the drain current must be IDSS (by definition). In other, words,, VGSQ 0 V, IDQ 10 mA, , and, , There is therefore no need to draw the transfer curve and, VD VDD IDRD 20 V (10 mA)(1.5 k), 20 V 15 V, 5V, Figure 6.34 Example 6.10., , 6.6 ENHANCEMENT-TYPE MOSFETs, The transfer characteristics of the enhancement-type MOSFET are quite different from, those encountered for the JFET and depletion-type MOSFETs, resulting in a graphical solution quite different from the preceding sections. First and foremost, recall that, for the n-channel enhancement-type MOSFET, the drain current is zero for levels of, gate-to-source voltage less than the threshold level VGS(Th), as shown in Fig. 6.35. For, levels of VGS greater than VGS(Th), the drain current is defined by, 274, , Chapter 6, , FET Biasing
Page 286 :
ID (mA), ID2, , ID = k (VGS – VGS(Th) )2, , ID (on), , ID1, , VGS(Th), , VGS1, , ID = 0 mA, , VGS(on), , VGS2, , VGS, , Figure 6.35 Transfer characteristics of an n-channel enhancementtype MOSFET., , ID k(VGS VGS(Th))2, , (6.25), , Since specification sheets typically provide the threshold voltage and a level of drain, current (ID(on)) and its corresponding level of VGS(on), two points are defined immediately as shown in Fig. 6.35. To complete the curve, the constant k of Eq. (6.25) must, be determined from the specification sheet data by substituting into Eq. (6.25) and, solving for k as follows:, ID k(VGS VGS(Th))2, ID(on) k(VGS(on) VGS(Th))2, and, , ID(on), k , (VGS(on) VGS(Th))2, , (6.26), , Once k is defined, other levels of ID can be determined for chosen values of VGS. Typically, a point between VGS(Th) and VGS(on) and one just greater than VGS(on) will provide a sufficient number of points to plot Eq. (6.25) (note ID1 and ID2 on Fig., 6.35)., , Feedback Biasing Arrangement, A popular biasing arrangement for enhancement-type MOSFETs is provided in Fig., 6.36. The resistor RG brings a suitably large voltage to the gate to drive the MOSFET, “on.” Since IG 0 mA and VRG 0 V, the dc equivalent network appears as shown, in Fig. 6.37., A direct connection now exists between drain and gate, resulting in, VD VG, and, , VDS VGS, , (6.27), , 6.6, , Enhancement-Type MOSFETs, , 275
Page 287 :
Figure 6.37 DC equivalent of, the network of Fig. 6.36., , Figure 6.36 Feedback biasing arrangement., , For the output circuit,, VDS VDD IDRD, which becomes the following after substituting Eq. (6.27):, VGS VDD IDRD, , (6.28), , The result is an equation that relates the same two variables as Eq. (6.25), permitting, the plot of each on the same set of axes., Since Eq. (6.28) is that of a straight line, the same procedure described earlier can, be employed to determine the two points that will define the plot on the graph. Substituting ID 0 mA into Eq. (6.28) gives, VGS VDDID 0 mA, , (6.29), , Substituting VGS 0 V into Eq. (6.28), we have, V D, ID D, RD, , , , VGS 0 V, , (6.30), , The plots defined by Eqs. (6.25) and (6.28) appear in Fig. 6.38 with the resulting operating point., , Figure 6.38 Determining the Qpoint for the network of Fig., 6.36., , 276, , Chapter 6, , FET Biasing
Page 288 :
Determine IDQ and VDSQ for the enhancement-type MOSFET of Fig. 6.39., , EXAMPLE 6.11, , Figure 6.39 Example 6.11., , Solution, Plotting the Transfer Curve:, , Two points are defined immediately as shown in Fig. 6.40. Solving for k:, Eq. (6.26):, , ID(on), k , (VGS(on) VGS(Th))2, 6 mA, 6 103, 2 A/v2, (8 V 3 V), 25, 0.24 103 A/V2, , For VGS 6 V (between 3 and 8 V):, ID 0.24, , 103(6 V 3 V)2 0.24, , 103(9), , 2.16 mA, , Figure 6.40 Plotting the transfer curve for the MOSFET of Fig., 6.39., , 6.6, , Enhancement-Type MOSFETs, , 277
Page 289 :
as shown on Fig. 6.40. For VGS 10 V (slightly greater than VGS(Th)):, 103(10 V 3 V)2 0.24, , ID 0.24, , 103(49), , 11.76 mA, as also appearing on Fig. 6.40. The four points are sufficient to plot the full curve for, the range of interest as shown in Fig. 6.40., For the Network Bias Line:, , VGS VDD IDRD, 12 V ID(2 k), Eq. (6.29):, , VGS VDD 12 VID 0 mA, , Eq. (6.30):, , V D, 12 V, ID D, 6 mAVGS 0 V, RD, 2 k, , The resulting bias line appears in Fig. 6.41., At the operating point:, IDQ 2.75 mA, and, , VGSQ 6.4 V, , with, , VDSQ VGSQ 6.4 V, ID = mA, , 12, 11, 10, 9, 8, 7, VDD, 6, RD, 5, 4, I D = 2.75 mA, Q, , 3, , Q-point, , 2, 1, 0, , 1, , 2, , 3, , 4, , 5, , 6, , 7, , 9 10 11 12, (VDD), VGSQ = 6.4 V, 8, , VGS, , Figure 6.41 Determining the Q-point for the network of Fig. 6.39., , Voltage-Divider Biasing Arrangement, A second popular biasing arrangement for the enhancement-type MOSFET appears, in Fig. 6.42. The fact that IG 0 mA results in the following equation for VGG as derived from an application of the voltage-divider rule:, R2VDD, , VG , R1 R2, , Figure 6.42 Voltage-divider, biasing arrangement for an nchannel enhancement MOSFET., , 278, , Chapter 6, , FET Biasing, , (6.31)
Page 290 :
Applying Kirchhoff’s voltage law around the indicated loop of Fig. 6.42 will result in, VG VGS VRS 0, and, , VGS VG VRS, , or, , VGS VG IDRS, , (6.32), , For the output section:, VRS VDS VRD VDD 0, VDS VDD VRS VRD, , and, , VDS VDD ID(RS RD), , or, , (6.33), , Since the characteristics are a plot of ID versus VGS and Eq. (6.32) relates the same, two variables, the two curves can be plotted on the same graph and a solution determined at their intersection. Once IDQ and VGSQ are known, all the remaining quantities of the network such as VDS, VD, and VS can be determined., Determine IDQ, VGSQ, and VDS for the network of Fig. 6.43., , EXAMPLE 6.12, , Figure 6.43 Example 6.12., , Solution, Network:, , Eq. (6.31):, , R2VDD, (18 M)(40 V), VG , 18 V, R1 R2, 22 M 18 M, , Eq. (6.32):, , VGS VG IDRS 18 V ID(0.82 k), , When ID 0 mA,, VGS 18 V (0 mA)(0.82 k) 18 V, as appearing on Fig. 6.44. When VGS 0 V,, VGS 18 V ID(0.82 k), 0 18 V ID(0.82 k), 18 V, ID 21.95 mA, 0.82 k, as appearing on Fig. 6.44., 6.6, , Enhancement-Type MOSFETs, , 279
Page 291 :
ID (mA), , 30, VG, = 21.95, RS, 20, , 10, I D ≅ 6.7 mA, , Q-point, , Q, , 0, , 5, VGS (Th), , 10, 15, 20, VGSQ = 12.5 V VG = 18 V, , 25, , VGS, , Figure 6.44 Determining the Q-point for the network of Example 6.12., , Device:, , VGS(Th) 5 V,, Eq. (6.26):, , ID(on) 3 mA with VGS(on) 10 V, , ID(on), k , (VGS(on) VGS(Th))2, 3 mA, , 0.12, (10 V 5 V)2, , 103 A/V2, , ID k(VGS VGS(Th))2, , and, , 0.12, , 103(VGS 5)2, , which is plotted on the same graph (Fig. 6.44). From Fig. 6.44,, IDQ ≅ 6.7 mA, VGSQ 12.5 V, Eq. (6.33):, , VDS VDD ID(RS RD), 40 V (6.7 mA)(0.82 k 3.0 k), 40 V 25.6 V, 14.4 V, , 6.7 SUMMARY TABLE, Now that the most popular biasing arrangements for the various FETs have been introduced, Table 6.1 reviews the basic results and demonstrates the similarity in approach for a number of configurations. It also reveals that the general analysis of dc, configurations for FETs is not overly complex. Once the transfer characteristics are, established, the network self-bias line can be drawn and the Q-point determined at, the intersection of the device transfer characteristic and the network bias curve. The, remaining analysis is simply an application of the basic laws of circuit analysis., 280, , Chapter 6, , FET Biasing
Page 293 :
6.8 COMBINATION NETWORKS, Now that the dc analysis of a variety of BJT and FET configurations is established,, the opportunity to analyze networks with both types of devices presents itself. Fundamentally, the analysis simply requires that we first approach the device that will, provide a terminal voltage or current level. The door is then usually open to calculate other quantities and concentrate on the remaining unknowns. These are usually, particularly interesting problems due to the challenge of finding the opening and then, using the results of the past few sections and Chapter 5 to find the important quantities for each device. The equations and relationships used are simply those we have, now employed on more than one occasion—no need to develop any new methods of, analysis., , EXAMPLE 6.13, , Determine the levels of VD and VC for the network of Fig. 6.45., , Figure 6.45 Example 6.13., , Solution, From past experience we now realize that VGS is typically an important quantity to, determine or write an equation for when analyzing JFET networks. Since VGS is a, level for which an immediate solution is not obvious, let us turn our attention to the, transistor configuration. The voltage-divider configuration is one where the approximate technique can be applied (RE (180 1.6 k) 288 k 10R2 240 k),, permitting a determination of VB using the voltage-divider rule on the input circuit., For VB:, 24 k(16 V), VB 3.62 V, 82 k 24 k, Using the fact that VBE 0.7 V results in, VE VB VBE 3.62 V 0.7 V, 2.92 V, 282, , Chapter 6, , FET Biasing
Page 294 :
and, , V E, VE, 2.92 V, IE R, , 1.825 mA, RE, RE, 1.6 k, , with, , IC ≅ IE 1.825 mA, , Continuing, we find for this configuration that, ID IS IC, VD 16 V ID(2.7 k), , and, , 16 V (1.825 mA)(2.7 k) 16 V 4.93 V, 11.07 V, The question of how to determine VC is not as obvious. Both VCE and VDS are unknown quantities preventing us from establishing a link between VD and VC or from, VE to VD. A more careful examination of Fig. 6.45 reveals that VC is linked to VB by, VGS (assuming that VRG 0 V). Since we know VB if we can find VGS, VC can be, determined from, VC VB VGS, The question then arises as to how to find the level of VGSQ from the quiescent, value of ID. The two are related by Shockley’s equation:, , , , , , V S, IDQ IDSS 1 G, VP, Q, , 2, , and VGSQ could be found mathematically by solving for VGSQ and substituting numerical values. However, let us turn to the graphical approach and simply work in the, reverse order employed in the preceding sections. The JFET transfer characteristics, are first sketched as shown in Fig. 6.46. The level of IDQ is then established by a horizontal line as shown in the same figure. VGSQ is then determined by dropping a line, down from the operating point to the horizontal axis, resulting in, VGSQ 3.7 V, The level of VC:, VC VB VGSQ 3.62 V (3.7 V), 7.32 V, , ID (mA), 12 I DSS, 10, 8, 6, 4, 2, , Q-point, , I D = 1.825 mA, Q, , – 6 –5, VP, , –4, , –3, , –2, , –1, , VGS ≅ – 3.7 V, Q, , 0, , Figure 6.46 Determining the, Q-point for the network of Fig., 6.45., , 6.8, , Combination Networks, , 283
Page 295 :
EXAMPLE 6.14, , Determine VD for the network of Fig. 6.47., , Figure 6.47 Example 6.14., , Solution, In this case, there is no obvious path to determine a voltage or current level for the, transistor configuration. However, turning to the self-biased JFET, an equation for, VGS can be derived and the resulting quiescent point determined using graphical, techniques. That is,, VGS IDRS ID(2.4 k), resulting in the self-bias line appearing in Fig. 6.48 that establishes a quiescent, point at, VGSQ 2.6 V, IDQ 1 mA, ID (mA), 8 IDSS, , For the transistor,, IE ≅ IC ID 1 mA, , 7, 6, 4, , VB 16 V IB(470 k), , 3, 2, 1, , 16 V (12.5 A)(470 k) 16 V 5.875 V, , 1.67 mA, I D = 1 mA, , 10.125 V, , Q, , 0, –4 –3 –2 –1, VP, VGS = –2.6 V, , and, , VE VD VB VBE, 10.125 V 0.7 V, , Q, , Figure 6.48 Determining the, Q-point for the network of Fig., 6.47., , 284, , I, 1 mA, IB C 12.5 A, , 80, , and, , 5, , 9.425 V, , Chapter 6, , FET Biasing
Page 296 :
6.9 DESIGN, The design process is one that is not limited solely to dc conditions. The area of application, level of amplification desired, signal strength, and operating conditions are, just a few of the conditions that enter into the total design process. However, we will, first concentrate on establishing the chosen dc conditions., For example, if the levels of VD and ID are specified for the network of Fig. 6.49,, the level of VGSQ can be determined from a plot of the transfer curve and RS can then, be determined from VGS IDRS. If VDD is specified, the level of RD can then be, calculated from RD (VDD VD)/ID. Of course, the value of RS and RD may not be, standard commercial values, requiring that the nearest commercial value be employed., However, with the tolerance (range of values) normally specified for the parameters, of a network, the slight variation due to the choice of standard values will seldom, cause a real concern in the design process., The above is only one possibility for the design phase involving the network of, Fig. 6.49. It is possible that only VDD and RD are specified together with the level of, VDS. The device to be employed may have to be specified along with the level of RS., It appears logical that the device chosen should have a maximum VDS greater than, the specified value by a safe margin., In general, it is good design practice for linear amplifiers to choose operating, points that do not crowd the saturation level (IDSS) or cutoff (VP) regions. Levels of, VGSQ close to VP/2 or IDQ near IDSS/2 are certainly reasonable starting points in the, design. Of course, in every design procedure the maximum levels of ID and VDS as, appearing on the specification sheet must not be considered as exceeded., The examples to follow have a design or synthesis orientation in that specific levels are provided and network parameters such as RD, RS, VDD, and so on, must be determined. In any case, the approach is in many ways the opposite of that described, in previous sections. In some cases, it is just a matter of applying Ohm’s law in its, appropriate form. In particular, if resistive levels are requested, the result is often obtained simply by applying Ohm’s law in the following form:, VR, Runknown , IR, , Figure 6.49 Self-bias configuration to be designed., , (6.34), , where VR and IR are often parameters that can be found directly from the specified, voltage and current levels., For the network of Fig. 6.50, the levels of VDQ and IDQ are specified. Determine the, required values of RD and RS. What are the closest standard commercial values?, , EXAMPLE 6.15, , 20 V, I D = 2.5 mA, Q, , RD, VD = 12 V, I DSS = 6 mA, VP = – 3 V, , RS, , Figure 6.50 Example 6.15., , 6.9, , Design, , 285
Page 297 :
Solution, As defined by Eq. (6.34),, VDD VDQ, VRD, RD , , IDQ, IDQ, 20 V 12 V, 8V, 3.2 k, 2.5 mA, 2.5 mA, , and, , Plotting the transfer curve in Fig. 6.51 and drawing a horizontal line at IDQ , 2.5 mA will result in VGSQ 1 V, and applying VGS IDRS will establish the, level of RS:, (VGSQ ), (1 V), RS , 0.4 k, IDQ, 2.5 mA, ID (mA), 6 IDSS, 5, 4, 3, I = 2.5 mA, 2 DQ, 1, –3 –2, VP, , –1, , 0, , VGS = – 1 V, Q, , VGS, , Figure 6.51 Determining VGSQ, for the network of Fig. 6.50., , The nearest standard commercial values are, RD 3.2 k ⇒ 3.3 k, RS 0.4 k ⇒ 0.39 k, , EXAMPLE 6.16, , For the voltage-divider bias configuration of Fig. 6.52, if VD 12 V and VGSQ , 2 V, determine the value of RS., , Solution, The level of VG is determined as follows:, 47 k(16 V), VG 5.44 V, 47 k 91 k, VDD VD, , ID , RD, , with, , 16 V 12 V, 2.22 mA, 1.8 k, The equation for VGS is then written and the known values substituted:, VGS VG IDRS, 2 V 5.44 V (2.22 mA)RS, , Figure 6.52 Example 6.16., , 7.44 V (2.22 mA)RS, 7.44 V, RS 3.35 k, 2.22 mA, , and, , The nearest standard commercial value is 3.3 k., 286, , Chapter 6, , FET Biasing
Page 298 :
The levels of VDS and ID are specified as VDS 12VDD and ID ID(on) for the network, of Fig. 6.53. Determine the level of VDD and RD., , EXAMPLE 6.17, , VDD, RD, , 10 MΩ, , VGS(on) = 6 V, I D(on) = 4 mA, VGS(Th) = 3 V, , Figure 6.53 Example 6.17., , Solution, Given ID ID(on) 4 mA and VGS VGS(on) 6 V, for this configuration,, VDS VGS 12VDD, and, , 6 V 12VDD, , so that, , VDD 12 V, , Applying Eq. (6.34) yields, , 12V, DD, VDD 21VDD, , VRD, VDD VDS , RD , , I, D(on), I, D(on), ID, ID(on), , and, , 6V, RD 1.5 k, 4 mA, , which is a standard commercial value., , 6.10 TROUBLESHOOTING, How often has a network been carefully constructed only to find that when the power, is applied, the response is totally unexpected and fails to match the theoretical calculations. What is the next step? Is it a bad connection? A misreading of the color, code for a resistive element? An error in the construction process? The range of possibilities seems vast and often frustrating. The troubleshooting process first described, in the analysis of BJT transistor configurations should narrow down the list of possibilities and isolate the problem area following a definite plan of attack. In general,, the process begins with a rechecking of the network construction and the terminal, connections. This is usually followed by the checking of voltage levels between specific terminals and ground or between terminals of the network. Seldom are current, levels measured since such maneuvers require disturbing the network structure to insert the meter. Of course, once the voltage levels are obtained, current levels can be, calculated using Ohm’s law. In any case, some idea of the expected voltage or current level must be known for the measurement to have any importance. In total, therefore, the troubleshooting process can begin with some hope of success only if the basic operation of the network is understood along with some expected levels of voltage, 6.10, , Troubleshooting, , 287
Page 299 :
Figure 6.54 Checking the dc, operation of the JFET self-bias, configuration., , or current. For the n-channel JFET amplifier, it is clearly understood that the quiescent value of VGSQ is limited to 0 V or a negative voltage. For the network of Fig., 6.54, VGSQ is limited to negative values in the range 0 V to VP. If a meter is hooked, up as shown in Fig. 6.54, with the positive lead (normally red) to the gate and the, negative lead (usually black) to the source, the resulting reading should have a negative sign and a magnitude of a few volts. Any other response should be considered, suspicious and needs to be investigated., The level of VDS is typically between 25% and 75% of VDD. A reading of 0 V for, VDS clearly indicates that either the output circuit has an “open” or the JFET is internally short-circuited between drain and source. If VD is VDD volts, there is obviously no drop across RD due to the lack of current through RD and the connections, should be checked for continuity., If the level of VDS seems inappropriate, the continuity of the output circuit can, easily be checked by grounding the negative lead of the voltmeter and measuring the, voltage levels from VDD to ground using the positive lead. If VD VDD, the current, through RD may be zero, but there is continuity between VD and VDD. If VS VDD,, the device is not open between drain and source, but it is also not “on.” The continuity through to VS is confirmed, however. In this case, it is possible that there is a, poor ground connection between RS and ground that may not be obvious. The internal connection between the wire of your lead and the terminal connector may have, separated. Other possibilities also exist, such as a shorted device from drain to source,, but the troubleshooter will simply have to narrow down the possible causes for the, malfunction., The continuity of a network can also be checked simply by measuring the voltage across any resistor of the network (except for RG in the JFET configuration). An, indication of 0 V immediately reveals the lack of current through the element due to, an open circuit in the network., The most sensitive element in the BJT and JFET configurations is the amplifier, itself. The application of excessive voltage during the construction or testing phase, or the use of incorrect resistor values resulting in high current levels can destroy the, device. If you question the condition of the amplifier, the best test for the FET is the, curve tracer since it not only reveals whether the device is operable but also its range, of current and voltage levels. Some testers may reveal that the device is still fundamentally sound but do not reveal whether its range of operation has been severely reduced., The development of good troubleshooting techniques comes primarily from experience and a level of confidence in what to expect and why. There are, of course,, times when the reasons for a strange response seem to disappear mysteriously when, you check a network. In such cases, it is best not to breathe a sigh of relief and, continue with the construction. The cause for such a sensitive “make or break”, situation should be found and corrected, or it may reoccur at the most inopportune, moment., , 6.11 P-CHANNEL FETS, The analysis thus far has been limited solely to n-channel FETs. For p-channel FETs,, a mirror image of the transfer curves is employed, and the defined current directions, are reversed as shown in Fig. 6.55 for the various types of FETs., Note for each configuration of Fig. 6.55 that each supply voltage is now a negative voltage drawing current in the indicated direction. In particular, note that the, double-subscript notation for voltages continues as defined for the n-channel device:, VGS, VDS, and so on. In this case, however, VGS is positive (positive or negative for, the depletion-type MOSFET) and VDS negative., 288, , Chapter 6, , FET Biasing
Page 300 :
Figure 6.55 p-channel configurations., , Due to the similarities between the analysis of n-channel and p-channel devices,, one can actually assume an n-channel device and reverse the supply voltage and perform the entire analysis. When the results are obtained, the magnitude of each quantity will be correct, although the current direction and voltage polarities will have to, be reversed. However, the next example will demonstrate that with the experience, gained through the analysis of n-channel devices, the analysis of p-channel devices, is quite straightforward., 6.11 P-Channel FETs, , 289
Page 301 :
EXAMPLE 6.18, , Determine IDQ, VGSQ, and VDS for the p-channel JFET of Fig. 6.56., , Figure 6.56 Example 6.18., , Solution, 20 k(20 V), VG 4.55 V, 20 k 68 k, Applying Kirchhoff’s voltage law gives, VG VGS IDRS 0, VGS VG IDRS, , and, Choosing ID 0 mA yields, , VGS VG 4.55 V, as appearing in Fig. 6.57., Choosing VGS 0 V, we obtain, VG, 4.55 V, ID , 2.53 mA, RS, 1.8 k, as also appearing in Fig. 6.57., The resulting quiescent point from Fig. 6.57:, IDQ 3.4 mA, VGSQ 1.4 V, ID (mA), 8, 7, 6, 5, I D = 3.4 mA, , 4, Q- point, , Q, , 2, 1, – 5 – 4 –3 – 2 – 1, , 0 1, , 2, VGS, , 4, VP, = 1.4 V, , Q, , 290, , Chapter 6, , FET Biasing, , 3, , VGS, , Figure 6.57 Determining the, Q-point for the JFET configuration of Fig. 6.56.
Page 302 :
For VDS, Kirchhoff’s voltage law will result in, IDRS VDS IDRD VDD 0, VDS VDD ID(RD RS), , and, , 20 V (3.4 mA)(2.7 k 1.8 k), 20 V 15.3 V, 4.7 V, , 6.12 UNIVERSAL JFET BIAS CURVE, Since the dc solution of a FET configuration requires drawing the transfer curve for, each analysis, a universal curve was developed that can be used for any level of IDSS, and VP. The universal curve for an n-channel JFET or depletion-type MOSFET (for, negative values of VGSQ) is provided in Fig. 6.58. Note that the horizontal axis is not, that of VGS but of a normalized level defined by VGS /VP, the VP indicating that, only the magnitude of VP is to be employed, not its sign. For the vertical axis, the, scale is also a normalized level of ID /IDSS. The result is that when ID IDSS, the, ratio is 1, and when VGS VP, the ratio VGS /VPis 1. Note also that the scale, for ID/IDSS is on the left rather than on the right as encountered for ID in past exercises. The additional two scales on the right need an introduction. The vertical scale, labeled m can in itself be used to find the solution to fixed-bias configurations., The other scale, labeled M, is employed along with the m scale to find the solution, m=, , VP, RS IDSS, , M= m, , +, , ID, I DSS, 1.0, , 5, , 1.0, , 0.8, , 4, , 0.8, , 0.6, , 3, , 0.6, , 0.4, , 2, , 0.4, , 0.2, , 1, , 0.2, , Normalized curve, V, of ID = I DSS 1 – GS, VP, , 0, , –1, , – 0.8, , VG G, VP, , 2, , – 0.6, , – 0.4, , – 0.2, , 6.12, , 0, , VGS, VP, , Figure 6.58 Universal JFET bias, curve., , Universal JFET Bias Curve, , 291
Page 303 :
to voltage-divider configurations. The scaling for m and M come from a mathematical development involving the network equations and normalized scaling just introduced. The description to follow will not concentrate on why the m scale extends from, 0 to 5 at VGS /VP 0.2 and the M scale from 0 to 1 at VGS /VP 0 but rather, on how to use the resulting scales to obtain a solution for the configurations. The, equations for m and M are the following, with VG as defind by Eq. (6.15)., VP, m , IDSSRS, , Mm, , (6.35), , VG, , VP, , (6.36), , R2VDD, VG , , R1 R2, , with, , Keep in mind that the beauty of this approach is the elimination of the need to sketch, the transfer curve for each analysis, that the superposition of the bias line is a great, deal easier, and that the calculations are fewer. The use of the m and M axes is best, described by examples employing the scales. Once the procedure is clearly understood, the analysis can be quite rapid, with a good measure of accuracy., , EXAMPLE 6.19, , Determine the quiescent values of ID and VGS for the network of Fig. 6.59., , Figure 6.59 Example 6.19., , Solution, Calculating the value of m, we obtain, VP, 3 V, m , 0.31, IDSSRS, (6 mA)(1.6 k), The self-bias line defined by RS is plotted by drawing a straight line from the origin, through a point defined by m 0.31, as shown in Fig. 6.60., The resulting Q-point:, VGS, I, D 0.18, 0.575, and, VP, IDSS, 292, , Chapter 6, , FET Biasing
Page 304 :
Figure 6.60 Universal curve for Examples 6.19 and 6.20., , The quiescent values of ID and VGS can then be determined as follows:, IDQ 0.18IDSS 0.18(6 mA) 1.08 mA, and, , VGSQ 0.575VP 0.575(3 V) 1.73 V, , Determine the quiescent values of ID and VGS for the network of Fig. 6.61., , Figure 6.61 Example 6.20., , EXAMPLE 6.20, , 293
Page 305 :
Solution, Calculating m gives, VP, 6 V, m , 0.625, IDSSRS, (8 mA)(1.2 k), Determining VG yields, R2VDD, (220 k)(18 V), VG , 3.5 V, R1 R2, 910 k 220 k, Finding M, we have, Mm, , VG, 3.5 V, 0.625 0.365, VP, 6V, , , , , , Now that m and M are known, the bias line can be drawn on Fig. 6.60. In particular,, note that even though the levels of IDSS and VP are different for the two networks, the, same universal curve can be employed. First find M on the M axis as shown in Fig., 6.60. Then draw a horizontal line over to the m axis and, at the point of intersection,, add the magnitude of m as shown in the figure. Using the resulting point on the m, axis and the M intersection, draw the straight line to intersect with the transfer curve, and define the Q-point:, VGS, I, D 0.53, 0.26, and, That is,, VP, IDSS, and, , IDQ 0.53IDSS 0.53(8 mA) 4.24 mA, , with, , VGSQ 0.26VP 0.26(6 V) 1.56 V, , 6.13 PSPICE WINDOWS, JFET Voltage-Divider Configuration, The results of Example 6.20 will now be verified using PSpice Windows. The network of Fig. 6.62 is constructed using computer methods described in the previous, chapters. The J2N3819 JFET is obtained from the EVAL.slb library and, through, Edit-Model-Edit Instance Model (Text), Vto is set to 6V and Beta, as defined by, Beta IDSS/VP2 is set to 0.222 mA/V2. After an OK followed by clicking the, Simulation icon (the yellow background with the two waveforms) and clearing the, Message Viewer, PSpiceAD screens will result in Fig. 6.62. The resulting drain cur-, , Figure 6.62 JFET voltage-divider configuration with PSpice Windows results, for the dc levels., , 294, , Chapter 6, , FET Biasing
Page 306 :
rent is 4.231 mA compared to the calculated level of 4.24 mA, and VGS is 3.504 V , 5.077 V 1.573 V versus the calculated value of 1.56 V—both excellent comparisons., , Combination Network, Next, the results of Example 6.13 with both a transistor and JFET will be verified., For the transistor, the Model must be altered to have a Bf(beta) of 180 to match the, example, and for the JFET, Vto must be set to 6V and Beta to 0.333 mA/V2. The, results appearing in Fig. 6.63 are again an excellent comparison with the handwritten solution. VD is 11.44 V compared to 11.07 V, VC is 7.138 V compared to 7.32 V,, and VGS is 3.758 V compared to 3.7 V., , Figure 6.63 Verifying, the hand-calculated solution of Example 6.13 using PSpice Windows., , Enhancement MOSFET, Next, the analysis procedure of Section 6.6 will be verified using the IRF150, enhancement-type n-channel MOSFET found in the EVAL.slb library. First, the device characteristics will be obtained by constructing the network of Fig. 6.64., , Figure 6.64 Network employed to obtain the characteristics of the IRF150 enhancement-type n-channel, MOSFET., , Clicking on the Setup Analysis icon (with the blue bar at the top in the left-hand, corner of the screen), DC Sweep is chosen to obtain the DC Sweep dialog box., Voltage Source is chosen as the Swept Var. Type, and Linear is chosen for the Sweep, Type. Since only one curve will be obtained, there is no need for a Nested Sweep., The voltage-drain voltage VDD will remain fixed at a value of 9 V (about three times, the threshold value (Vto) of 2.831 V), while the gate-to-source voltage VGS, which in, 6.13, , PSpice Windows, , 295
Page 307 :
this case is VGG, will be swept from 0 to 10 V. The Name therefore is VGG and the, Start Value 0V, the End Value 10V, and the Increment 0.01V. After an OK followed, by a Close of the Analysis Setup, the analysis can be performed through the Analysis icon. If Automatically run Probe after simulation is chosen under the Probe, Setup Options of Analysis, the OrCAD-MicroSim Probe screen will result, with, the horizontal axis appearing with VGG as the variable and range from 0 to 10 V., Next, the Add Traces dialog box can be obtained by clicking the Traces icon (red, pointed pattern on an axis) and the ID(M1) chosen to obtain the drain current versus, the gate-to-source voltage. Click OK, and the characteristics will appear on the screen., To expand the scale of the resulting plot to 20 V, simply choose Plot followed by XAxis Settings and set the User Defined range to 0 to 20 V. After another OK, and, the plot of Fig. 6.65 will result, revealing a rather high-current device. The labels ID, and VGS were added using the Text Label icon with the letters A, B, and C. The, hand-drawn load line will be described in the paragraph to follow., , Figure 6.65 Characteristics of the IRF500 MOSFET of Figure 6.64 with a load line defined by the, network of Figure 6.66., , The network of Fig. 6.66 was then established to provide a load line extending, from ID equal to 20 V/0.4 Ω 50 A down to VGS VGG 20 V as shown in Fig., 6.65. A simulation resulted in the levels shown, which match the solution of Fig. 6.65., , Figure 6.66 Feedback-biasing arrangement employing an IRF150 enhancement-type MOSFET., , 296, , Chapter 6, , FET Biasing
Page 308 :
§ 6.2 Fixed-Bias Configuration, , PROBLEMS, , 1. For the fixed-bias configuration of Fig. 6.67:, (a) Sketch the transfer characteristics of the device., (b) Superimpose the network equation on the same graph., (c) Determine IDQ and VDSQ., (d) Using Shockley’s equation, solve for IDQ and then find VDSQ. Compare with the solutions, of part (c)., , Figure 6.67 Problems 1, 35, , 2. For the fixed-bias configuration of Fig. 6.68, determine:, (a) IDQ and VGSQ using a purely mathematical approach., (b) Repeat part (a) using a graphical approach and compare results., (c) Find VDS, VD, VG, and VS using the results of part (a)., , Figure 6.68 Problem 2, , 3. Given the measured value of VD in Fig. 6.69, determine:, (a) ID., (b) VDS., (c) VGG., , Figure 6.69 Problem 3, , 297
Page 309 :
4. Determine VD for the fixed-bias configuration of Fig. 6.70., 5. Determine VD for the fixed-bias configuration of Fig. 6.71., , Figure 6.70 Problem 4, , Figure 6.71 Problem 5, , § 6.3 Self-Bias Configuration, 6., , For the self-bias configuration of Fig. 6.72:, (a) Sketch the transfer curve for the device., (b) Superimpose the network equation on the same graph., (c) Determine IDQ and VGSQ., (d) Calculate VDS, VD, VG, and VS., , Figure 6.72 Problems 6, 7, 36, , * 7. Determine IDQ for the network of Fig. 6.72 using a purely mathematical approach. That is, establish a quadratic equation for ID and choose the solution compatible with the network characteristics. Compare to the solution obtained in Problem 6., , 298, , 8., , For the network of Fig. 6.73, determine:, (a) VGSQ and IDQ., (b) VDS, VD, VG, and VS., , 9., , Given the measurement VS 1.7 V for the network of Fig. 6.74, determine:, (a) IDQ., (b) VGSQ., (c) IDSS., (d) VD., (e) VDS., , Chapter 6, , FET Biasing
Page 310 :
* 10. For the network of Fig. 6.75, determine:, (a) ID., (b) VDS., (c) VD., (d) VS., , Figure 6.73 Problem 8, , Figure 6.74 Problem 9, , Figure 6.75 Problem 10, , * 11. Find VS for the network of Fig. 6.76., , Figure 6.76 Problem 11, , § 6.4 Voltage-Divider Biasing, 12. For the network of Fig. 6.77, determine:, (a) VG., (b) IDQ and VGSQ., (c) VD and VS., (d) VDSQ., , Figure 6.77 Problems 12, 13, , 13. (a) Repeat Problem 12 with RS 0.51 k (about 50% of the value of 12). What is the effect, of a smaller RS on IDQ and VGSQ?, (b) What is the minimum possible value of RS for the network of Fig. 6.77?, Problems, , 299
Page 311 :
14., , For the network of Fig. 6.78, VD 9 V. Determine:, (a) ID., (b) VS and VDS., (c) VG and VGS., (d) VP., , * 15. For the network of Fig. 6.79, determine:, (a) IDQ and VGSQ., (b) VDS and VS., , 18 V, ID, 2 kΩ, 750 kΩ, , VG, , +, VGS, , –, , VS, , +, , VD = 9 V, , VDS, , IDSS = 8 mA, , –, , 91 kΩ, 0.68 kΩ, , Figure 6.79 Problems 15, 37, , Figure 6.78 Problem 14, , * 16. Given VDS 4 V for the network of Fig. 6.80, determine:, (a) ID., (b) VD and VS., (c) VGS., , § 6.5 Depletion-Type MOSFETs, 17., , For the self-bias configuration of Fig. 6.81, determine:, (a) IDQ and VGSQ., (b) VDS and VD., , * 18. For the network of Fig. 6.82, determine:, (a) IDQ and VGSQ., (b) VDS and VS., , Figure 6.80 Problem 16, , Figure 6.82 Problem 18, , Figure 6.81 Problem 17, , 300, , Chapter 6, , FET Biasing
Page 312 :
§ 6.6 Enhancement-Type MOSFETs, 19., , For the network of Fig. 6.83, determine:, (a) IDQ., (b) VGSQ and VDSQ., (c) VD and VS., (d) VDS., , 20., , For the voltage-divider configuration of Fig. 6.84, determine:, (a) IDQ and VGSQ., (b) VD and VS., , 24 V, , 2.2 kΩ, 10 MΩ, , ID, , Q, , +, , VGS(Th) = 3 V, I D(on) = 5 mA, VGS(on) = 6 V, VGS, , Q, , –, , 6.8 MΩ, 0.75 kΩ, , Figure 6.83 Problem 19, , Figure 6.84 Problem 20, , § 6.8 Combination Networks, *, , 21. For the network of Fig. 6.85, determine:, (a) VG., (b) VGSQ and IDQ., (c) IE., (d) IB., (e) VD., (f) VC., , Figure 6.85 Problem 21, , Problems, , 301
Page 313 :
* 22. For the combination network of Fig. 6.86, determine:, (a) VB and VG., (b) VE., (c) IE, IC, and ID., (d) IB., (e) VC, VS, and VD., (f) VCE., (g) VDS., , Figure 6.86 Problem 22, , § 6.9 Design, * 23. Design a self-bias network using a JFET transistor with IDSS 8 mA and VP 6 V to have a, Q-point at IDQ 4 mA using a supply of 14 V. Assume that RD 3RS and use standard values., * 24. Design a voltage-divider bias network using a depletion-type MOSFET with IDSS 10 mA and, VP 4 V to have a Q-point at IDQ 2.5 mA using a supply of 24 V. In addition, set VG 4, V and use RD 2.5RS with R1 22 M. Use standard values., 25. Design a network such as appears in Fig. 6.39 using an enhancement-type MOSFET with, VGS(Th) 4 V, k 0.5 103A/V2 to have a Q-point of IDQ 6 mA. Use a supply of 16 V, and standard values., , § 6.10 Troubleshooting, * 26. What do the readings for each configuration of Fig. 6.87 suggest about the operation of the, network?, , Figure 6.87 Problem 26, , 302, , Chapter 6, , FET Biasing
Page 314 :
*, , 27. Although the readings of Fig. 6.88 initially suggest that the network is behaving properly, determine a possible cause for the undesirable state of the network., , *, , 28. The network of Fig. 6.89 is not operating properly. What is the specific cause for its failure?, , Figure 6.88 Problem 27, , Figure 6.89 Problem 28, , § 6.11 p-Channel FETs, 29. For the network of Fig. 6.90, determine:, (a) IDQ and VGSQ., (b) VDS., (c) VD., 30. For the network of Fig. 6.91, determine:, (a) IDQ and VGSQ., (b) VDS., (c) VD., , Figure 6.90 Problem 29, , Figure 6.91 Problem 30, , § 6.12 Universal JFET Bias Curve, 31. Repeat Problem 1 using the universal JFET bias curve., 32. Repeat Problem 6 using the universal JFET bias curve., 33. Repeat Problem 12 using the universal JFET bias curve., 34. Repeat Problem 15 using the universal JFET bias curve., Problems, , 303
Page 315 :
§ 6.13 PSpice Windows, 35. Perform a PSpice Windows analysis of the network of Problem 1., 36. Perform a PSpice Windows analysis of the network of Problem 6., 37. Perform a PSpice Windows analysis of the network of Problem 15., *Please Note: Asterisks indicate more difficult problems., , 304, , Chapter 6, , FET Biasing
Page 316 :
re, CHAPTER, , BJT Transistor, Modeling, , 7, , 7.1 INTRODUCTION, The basic construction, appearance, and characteristics of the transistor were introduced in Chapter 3. The dc biasing of the device was then examined in detail in Chapter 4. We now begin to examine the small-signal ac response of the BJT amplifier by, reviewing the models most frequently used to represent the transistor in the sinusoidal, ac domain., One of our first concerns in the sinusoidal ac analysis of transistor networks, is the magnitude of the input signal. It will determine whether small-signal or largesignal techniques should be applied. There is no set dividing line between the two,, but the application––and the magnitude of the variables of interest relative to the, scales of the device characteristics––will usually make it quite clear which method is, appropriate. The small-signal technique is introduced in this chapter, and large-signal, applications are examined in Chapter 16., There are two models commonly used in the small-signal ac analysis of transistor networks: the re model and the hybrid equivalent model. This chapter not only introduces both models but defines the role of each and the relationship between the, two., , 7.2 AMPLIFICATION IN THE AC DOMAIN, It was demonstrated in Chapter 3 that the transistor can be employed as an amplifying device. That is, the output sinusoidal signal is greater than the input signal or,, stated another way, the output ac power is greater than the input ac power. The question then arises as to how the ac power output can be greater than the input ac power?, Conservation of energy dictates that over time the total power output, Po, of a system, cannot be greater than its power input, Pi, and that the efficiency defined by Po /Pi, cannot be greater than 1. The factor missing from the discussion above that permits, an ac power output greater than the input ac power is the applied dc power. It is a, contributor to the total output power even though part of it is dissipated by the device and resistive elements. In other words, there is an “exchange” of dc power to the, ac domain that permits establishing a higher output ac power. In fact, a conversion, efficiency is defined by Po(ac)/Pi(dc), where Po(ac) is the ac power to the load and, Pi(dc) is the dc power supplied., Perhaps the role of the dc supply can best be described by first considering the, simple dc network of Fig. 7.1. The resulting direction of flow is indicated in the figure with a plot of the current i versus time. Let us now insert a control mechanism, , Figure 7.1 Steady current, established by a dc supply., , 305
Page 317 :
re, such as that shown in Fig. 7.2. The control mechanism is such that the application of, a relatively small signal to the control mechanism can result in a much larger oscillation in the output circuit. For the system of Fig. 7.2, the peak value of the oscillation is controlled by the established dc level. Any attempt to exceed the limit set by, the dc level will result in a “clipping” (flattening) of the peak region of the output, signal. In total, therefore, proper amplifier design requires that the dc and ac components be sensitive to each other’s requirements and limitations., However, it is indeed fortunate that transistor small-signal amplifiers can be, considered linear for most applications, permitting the use of the superposition theorem to isolate the dc analysis from the ac analysis., , 7.3 BJT TRANSISTOR MODELING, Figure 7.2 Effect of a control, element on the steady-state flow, of the electrical system of Fig. 7.1., , The key to transistor small-signal analysis is the use of equivalent circuits (models), to be introduced in this chapter., A model is the combination of circuit elements, properly chosen, that best approximates the actual behavior of a semiconductor device under specific operating conditions., Once the ac equivalent circuit has been determined, the graphical symbol of the, device can be replaced in the schematic by this circuit and the basic methods of ac, circuit analysis (mesh analysis, nodal analysis, and Thévenin’s theorem) can be applied to determine the response of the circuit., There are two schools of thought in prominence today regarding the equivalent, circuit to be substituted for the transistor. For many years the industrial and educational institutions relied heavily on the hybrid parameters (to be introduced shortly)., The hybrid-parameter equivalent circuit continues to be very popular, although it must, now share the spotlight with an equivalent circuit derived directly from the operating, conditions of the transistor—the re model. Manufacturers continue to specify the hybrid parameters for a particular operating region on their specification sheets. The parameters (or components) of the re model can be derived directly from the hybrid parameters in this region. However, the hybrid equivalent circuit suffers from being, limited to a particular set of operating conditions if it is to be considered accurate., The parameters of the other equivalent circuit can be determined for any region of, operation within the active region and are not limited by the single set of parameters, provided by the specification sheet. In turn, however, the re model fails to account for, the output impedance level of the device and the feedback effect from output to, input., Since both models are used extensively today, they are both examined in detail in, this text. In some analysis and examples the hybrid model will be employed, while, in others the re model will be used exclusively. The text will make every effort, however, to show how closely related the two models are and how a proficiency with one, leads to a natural proficiency with the other., In an effort to demonstrate the effect that the ac equivalent circuit will have on, the analysis to follow, consider the circuit of Fig. 7.3. Let us assume for the moment, that the small-signal ac equivalent circuit for the transistor has already been determined. Since we are interested only in the ac response of the circuit, all the dc supplies can be replaced by a zero-potential equivalent (short circuit) since they determine only the dc (quiescent level) of the output voltage and not the magnitude of the, swing of the ac output. This is clearly demonstrated by Fig. 7.4. The dc levels were, simply important for determining the proper Q-point of operation. Once determined,, the dc levels can be ignored in the ac analysis of the network. In addition, the coupling capacitors C1 and C2 and bypass capacitor C3 were chosen to have a very small, , 306, , Chapter 7, , BJT Transistor Modeling
Page 318 :
re, , Figure 7.3 Transistor circuit, under examination in this introductory discussion., , Figure 7.4 The network of, Fig. 7.3 following removal of the, dc supply and insertion of the, short-circuit equivalent for the capacitors., , reactance at the frequency of application. Therefore, they too may for all practical, purposes be replaced by a low-resistance path or a short circuit. Note that this will, result in the “shorting out” of the dc biasing resistor RE. Recall that capacitors assume an “open-circuit” equivalent under dc steady-state conditions, permitting an isolation between stages for the dc levels and quiescent conditions., If we establish a common ground and rearrange the elements of Fig. 7.4, R1 and, R2 will be in parallel and RC will appear from collector to emitter as shown in Fig., 7.5. Since the components of the transistor equivalent circuit appearing in Fig. 7.5, employ familiar components such as resistors and independent controlled sources,, , Figure 7.5 Circuit of Fig. 7.4 redrawn for small-signal ac analysis., , 7.3 BJT Transistor Modeling, , 307
Page 319 :
re, analysis techniques such as superposition, Thévenin’s theorem, and so on, can be applied to determine the desired quantities., Let us further examine Fig. 7.5 and identify the important quantities to be determined for the system. Since we know that the transistor is an amplifying device, we, would expect some indication of how the output voltage Vo is related to the input, voltage Vi —the voltage gain. Note in Fig. 7.5 for this configuration that Ii Ib and, Io Ic, which define the current gain Ai Io/Ii. The input impedance Zi and output, impedance Zo will prove particularly important in the analysis to follow. A great deal, more will be offered about these parameters in the sections to follow., In summary, therefore, the ac equivalent of a network is obtained by:, 1. Setting all dc sources to zero and replacing them by a short-circuit equivalent, 2. Replacing all capacitors by a short-circuit equivalent, 3. Removing all elements bypassed by the short-circuit equivalents introduced, by steps 1 and 2, 4. Redrawing the network in a more convenient and logical form, In the sections to follow, the re and hybrid equivalent circuits will be introduced, to complete the ac analysis of the network of Fig. 7.5., , 7.4 THE IMPORTANT PARAMETERS:, Zi, Zo, Av, Ai, Before investigating the equivalent circuits for BJTs in some detail, let us concentrate, on those parameters of a two-port system that are of paramount importance from an, analysis and design viewpoint. For the two-port (two pairs of terminals) system of, Fig. 7.6, the input side (the side to which the signal is normally applied) is to the left, and the output side (where the load is connected) is to the right. In fact, for most electrical and electronic systems, the general flow is usually from the left to the right. For, both sets of terminals, the impedance between each pair of terminals under normal, operating conditions is quite important., , Figure 7.6, , Two-port system., , Input Impedance, Zi, For the input side, the input impedance Zi is defined by Ohm’s law as the following:, V, Zi i, Ii, , (7.1), , If the input signal Vi is changed, the current Ii can be computed using the same, level of input impedance. In other words:, 308, , Chapter 7, , BJT Transistor Modeling
Page 320 :
re, For small-signal analysis, once the input impedance has been determined the, same numerical value can be used for changing levels of applied signal., In fact, we will find in the sections to follow that the input impedance of a transistor can be approximately determined by the dc biasing conditions—conditions that, do not change simply because the magnitude of the applied ac signal has changed., It is particularly noteworthy that for frequencies in the low to mid-range (typically 100 kHz):, The input impedance of a BJT transistor amplifier is purely resistive in nature, and, depending on the manner in which the transistor is employed, can vary, from a few ohms to megohms., In addition:, An ohmmeter cannot be used to measure the small-signal ac input impedance, since the ohmmeter operates in the dc mode., Equation (7.1) is particularly useful in that it provides a method for measuring, the input resistance in the ac domain. For instance, in Fig. 7.7 a sensing resistor has, been added to the input side to permit a determination of Ii using Ohm’s law. An oscilloscope or sensitive digital multimeter (DMM) can be used to measure the voltage, Vs and Vi. Both voltages can be the peak-to-peak, peak, or rms values, as long as both, levels use the same standard. The input impedance is then determined in the following manner:, Vs Vi, , Ii , Rsense, , (7.2), , V, Zi i, Ii, , (7.3), , and, , +, , Ii, , +, , Rsense, Zi, , Vs, , Vi, , Two-port, System, , –, –, Figure 7.7, , Determining Zi., , The importance of the input impedance of a system can best be demonstrated by, the network of Fig. 7.8. The signal source has an internal resistance of 600 , and, the system (possibly a transistor amplifier) has an input resistance of 1.2 k. If the, source were ideal (Rs 0 ), the full 10 mV would be applied to the system, but, , Rsource, , +, Vs, , 600 Ω, 10 mV, , –, , +, Zi = 1.2 kΩ, Vi, , –, , Amplifier, , Figure 7.8 Demonstrating the, impact of Zi on an amplifier’s response., , 7.4 The Important Parameters: Zi, Zo, Av, Ai, , 309
Page 321 :
re, with a source impedance, the input voltage must be determined using the voltagedivider rule as follows:, Z Vs, (1.2 k)(10 mV), 6.67 mV, Vi i , Zi Rsource, 1.2 k 0.6 k, Thus, only 66.7% of the full-input signal is available at the input. If Zi were only, 600 , then Vi 12(10 mV) 5 mV or 50% of the available signal. Of course, if, Zi 8.2 k, Vi will be 93.2% of the applied signal. The level of input impedance,, therefore, can have a significant impact on the level of signal that reaches the system, (or amplifier). In the sections and chapters to follow, it will be demonstrated that the, ac input resistance is dependent on whether the transistor is in the common-base,, common-emitter, or common-collector configuration and on the placement of the resistive elements., , EXAMPLE 7.1, , For the system of Fig. 7.9, determine the level of input impedance., , Rsense, 1 kΩ, , +, Vs, , 2 mV, , Zi, , +, , Vi = 1.2 mV, , –, , Two-port, System, , –, Figure 7.9, , Example 7.1, , Solution, Vs Vi, 2 mV 1.2 mV, 0.8 mV, Ii , 0.8 A, Rsense, 1 k, 1 k, and, , V, 1.2 mV, Zi i 1.5 k, Ii, 0.8 A, , Output Impedance, Zo, The output impedance is naturally defined at the output set of terminals, but the manner in which it is defined is quite different from that of the input impedance. That is:, The output impedance is determined at the output terminals looking back into, the system with the applied signal set to zero., In Fig. 7.10, for example, the applied signal has been set to zero volts. To determine Zo, a signal, Vs, is applied to the output terminals and the level of Vo is measured with an oscilloscope or sensitive DMM. The output impedance is then, determined in the following manner:, , and, , 310, , Chapter 7, , BJT Transistor Modeling, , VV, Io o, Rsense, , (7.4), , Vo, Zo , Io, , (7.5)
Page 322 :
re, Rsource, , Rsense, , +, Io, , Two-port, System, , Vs = 0 V, , Vo, , +, V, , Zo, , –, , –, , Figure 7.10 Determining Zo., , In particular, for frequencies in the low to mid-range (typically 100 kHz):, The output impedance of a BJT transistor amplifier is resistive in nature and,, depending on the configuration and the placement of the resistive elements,, Zo, can vary from a few ohms to a level that can exceed 2 M., In addition:, An ohmmeter cannot be used to measure the small-signal ac output impedance since the ohmmeter operates in the dc mode., For amplifier configurations where significant gain in current is desired, the level, of Zo should be as large as possible. As demonstrated by Fig. 7.11, if Zo RL, the, majority of the amplifier output current will pass on to the load. It will be demonstrated in the sections and chapters to follow that Zo is frequently so large compared, to RL that it can be replaced by an open-circuit equivalent., , Figure 7.11 Effect of Zo Ro, on the load or output current IL., , EXAMPLE 7.2, , For the system of Fig. 7.12, determine the level of output impedance., Rsense, Two-port, System, Vs = 0 V, , +, , 20 kΩ, , Zo, Vo = 680 mV, , –, , +, V= 1 V, , –, Figure 7.12 Example 7.2., , Solution, VV, 1 V 680 mV, 320 mV, Io o 16 A, Rsense, 20 k, 20 k, and, , Vo, 680 mV, Zo , 42.5 k, Io, 16 A, , Voltage Gain, Av, One of the most important characteristics of an amplifier is the small-signal ac voltage gain as determined by, Vo, Av , Vi, , (7.6), , 7.4 The Important Parameters: Zi, Zo, Av, Ai, , 311
Page 323 :
re, For the system of Fig. 7.13, a load has not been connected to the output terminals, and the level of gain determined by Eq. (7.6) is referred to as the no-load voltage, gain. That is,, , , , Vo, AvNL , Vi, , (7.7), , RL (open circuit), , Rsource, , +, , +, Zi, , Vs, , –, , +, , AυNL, , Vi, , –, , Vo, , –, , Figure 7.13 Determining the no-load voltage gain., , In Chapter 9 it will be demonstrated that:, For transistor amplifiers, the no-load voltage gain is greater than the loaded, voltage gain., For the system of Fig. 7.13 having a source resistance Rs, the level of Vi would, first have to be determined using the voltage-divider rule before the gain Vo/Vs could, be calculated. That is,, Z Vs, Vi i , Zi Rs, with, , V, Zi, i , Vs, Zi Rs, , and, , V Vo, Vo, Avs , i , Vs Vi, Vs, , so that, , Vo, Zi, Avs , A, Vs, Zi Rs vNL, , (7.8), , Experimentally, the voltage gain Avs or AvNL can be determined simply by measuring the appropriate voltage levels with an oscilloscope or sensitive DMM and substituting into the appropriate equation., Depending on the configuration, the magnitude of the voltage gain for a, loaded single-stage transistor amplifier typically ranges from just less than 1, to a few hundred. A multistage (multiunit) system, however, can have a voltage gain in the thousands., , EXAMPLE 7.3, , 312, , For the BJT amplifier of Fig. 7.14, determine:, (a) Vi., (b) Ii., (c) Zi., (d) Avs., Chapter 7, , BJT Transistor Modeling
Page 324 :
re, , Figure 7.14 Example 7.3., , Solution, Vo, Vo, 7.68 V, (a) AvNL , and Vi , 24 mV, AvNL, Vi, 320, Vs Vi, 40 mV 24 mV, 13.33 A, (b) Ii , Rs, 1.2 k, V, 24 mV, (c) Zi i 1.8 k, Ii, 13.33 A, Zi, A, (d) Avs , Zi Rs vNL, 1.8 k, (320), 1.8 k 1.2 k, 192, , Current Gain, Ai, The last numerical characteristic to be discussed is the current gain defined by, I, Ai o, Ii, , (7.9), , Although typically the recipient of less attention than the voltage gain, it is, however,, an important quantity that can have significant impact on the overall effectiveness of, a design. In general:, For BJT amplifiers, the current gain typically ranges from a level just less, than 1 to a level that may exceed 100., For the loaded situation of Fig. 7.15,, V, and, Ii i, Zi, , Vo, Io , RL, , Figure 7.15 Determining the, loaded current gain., , 7.4 The Important Parameters: Zi, Zo, Av, Ai, , 313
Page 325 :
re, with, , I, Vo /RL, V Z, Ai o , oi, Ii, Vi /Zi, Vi RL, , and, , Z, Ai Avi, RL, , (7.10), , Eq. (7.10) allows the determination of the current gain from the voltage gain and the, impedance levels., , Phase Relationship, The phase relationship between input and output sinusoidal signals is important for, a variety of practical reasons. Fortunately, however:, For the typical transistor amplifier at frequencies that permit ignoring the effects of the reactive elements, the input and output signals are either 180° out, of phase or in phase., The reason for the either–or situation will become quite clear in the chapters to, follow., , Summary, The parameters of primary importance for an amplifier have now been introduced:, the input impedance Zi, the output impedance Zo, the voltage gain Av, the current gain, Ai, and the resulting phase relationship. Other factors, such as the applied frequency, at the low and high ends of the frequency spectrum, will affect some of these parameters, but this will be discussed in Chapter 11. In the sections and chapters to follow, all the parameters will be determined for a variety of transistor networks to permit a comparison of the strengths and weaknesses for each configuration., , 7.5 THE re TRANSISTOR MODEL, The re model employs a diode and controlled current source to duplicate the behavior of a transistor in the region of interest. Recall that a current-controlled current, source is one where the parameters of the current source are controlled by a current, elsewhere in the network. In fact, in general:, BJT transistor amplifiers are referred to as current-controlled devices., , Common Base Configuration, In Fig. 7.16a, a common-base pnp transistor has been inserted within the two-port, structure employed in our discussion of the last few sections. In Fig. 7.16b, the re, model for the transistor has been placed between the same four terminals. As noted, in Section 7.3, the model (equivalent circuit) is chosen in such a way as to approximate the behavior of the device it is replacing in the operating region of interest. In, other words, the results obtained with the model in place should be relatively close, to those obtained with the actual transistor. You will recall from Chapter 3 that one, junction of an operating transistor is forward-biased while the other is reverse-biased., The forward-biased junction will behave much like a diode (ignoring the effects of, changing levels of VCE) as verified by the curves of Fig. 3.7. For the base-to-emitter, junction of the transistor of Fig. 7.16a, the diode equivalence of Fig. 7.16b between, the same two terminals seems to be quite appropriate. For the output side, recall that, the horizontal curves of Fig. 3.8 revealed that Ic Ie (as derived from Ic Ie) for, the range of values of VCE. The current source of Fig. 7.16b establishes the fact that, 314, , Chapter 7, , BJT Transistor Modeling
Page 326 :
re, , Figure 7.16 (a) Common-base BJT transistor; (b) re model for the configuration, of Fig. 7.16a., , Ic Ie, with the controlling current Ie appearing in the input side of the equivalent, circuit as dictated by Fig. 7.16a. We have therefore established an equivalence at the, input and output terminals with the current-controlled source, providing a link between the two—an initial review would suggest that the model of Fig. 7.16b is a valid, model of the actual device., Recall from Chapter 1 that the ac resistance of a diode can be determined by the, equation rac 26 mV/ID, where ID is the dc current through the diode at the Q (quiescent) point. This same equation can be used to find the ac resistance of the diode, of Fig. 7.16b if we simply substitute the emitter current as follows:, 26 mV, re , IE, , (7.11), , The subscript e of re was chosen to emphasize that it is the dc level of emitter, current that determines the ac level of the resistance of the diode of Fig. 7.16b. Substituting the resulting value of re in Fig. 7.16b will result in the very useful model of, Fig. 7.17., , Figure 7.17 Common-base re, equivalent circuit., , Due to the isolation that exists between input and output circuits of Fig. 7.17, it, should be fairly obvious that the input impedance Zi for the common-base configuration of a transistor is simply re. That is,, Zi re, , (7.12), CB, , For the common-base configuration, typical values of Zi range from a few, ohms to a maximum of about 50 ., For the output impedance, if we set the signal to zero, then Ie 0 A and Ic , Ie (0 A) 0 A, resulting in an open-circuit equivalence at the output terminals., The result is that for the model of Fig. 7.17,, Zo , , (7.13), CB, , 7.5 The re Transistor Model, , 315
Page 327 :
re, In actuality:, For the common-base configuration, typical values of Zo are in the megohm, range., The output resistance of the common-base configuration is determined by the slope, of the characteristic lines of the output characteristics as shown in Fig. 7.18. Assuming the lines to be perfectly horizontal (an excellent approximation) would result in, the conclusion of Eq. (7.13). If care were taken to measure Zo graphically or experimentally, levels typically in the range 1- to 2-M would be obtained., , IC (mA), , Slope =, , 1, ro, , IE = 4 mA, , 4, IE = 3 mA, 3, IE = 2 mA, 2, IE = 1 mA, 1, IE = 0 mA, 0, , VCB, , Figure 7.18 Defining Zo., , In general, for the common-base configuration the input impedance is relatively small and the output impedance quite high., The voltage gain will now be determined for the network of Fig. 7.19., Vo Io RL (Ic)RL IeRL, Vi IeZi Iere, , and, , Vo, I RL, Av , e, Vi, Iere, , so that, , RL, RL, Av , , re, re, , and, , (7.14), CB, , For the current gain,, I, I, I, Ai o c e, Ii, Ie, Ie, and, , Ai 1, , (7.15), CB, , Figure 7.19 Defining Av , Vo /Vi for the common-base configuration., , 316, , Chapter 7, , BJT Transistor Modeling
Page 328 :
re, The fact that the polarity of the voltage Vo as determined by the current Ic is the, same as defined by Fig. 7.19 (i.e., the negative side is at ground potential) reveals that, Vo and Vi are in phase for the common-base configuration. For an npn transistor in, the common-base configuration, the equivalence would appear as shown in Fig. 7.20., , Figure 7.20 Approximate model for a common-base npn transistor configuration., , For a common-base configuration of Fig. 7.17 with IE 4 mA, 0.98, and an ac, signal of 2 mV applied between the base and emitter terminals:, (a) Determine the input impedance., (b) Calculate the voltage gain if a load of 0.56 k is connected to the output terminals., (c) Find the output impedance and current gain., , EXAMPLE 7.4, , Solution, 26 mV, 26 mV, (a) re 6.5 , IE, 4 mA, V, 2 mV, (b) Ii Ie i 307.69 A, Zi, 6.5 , Vo Ic RL IeRL (0.98)(307.69 A)(0.56 k), 168.86 mV, Vo, 168.86 mV, 84.43, and Av , Vi, 2 mV, or from Eq. (7.14),, RL, (0.98)(0.56 k), 84.43, Av , re, 6.5 , (c) Zo , I, Ai o 0.98, Ii, , as defined by Eq. (7.15), , Common Emitter Configuration, For the common-emitter configuration of Fig. 7.21a, the input terminals are the base, and emitter terminals, but the output set is now the collector and emitter terminals., In addition, the emitter terminal is now common between the input and output ports, of the amplifier. Substituting the re equivalent circuit for the npn transistor will result, in the configuration of Fig. 7.21b. Note that the controlled-current source is still connected between the collector and base terminals and the diode between the base and, 7.5 The re Transistor Model, , 317
Page 329 :
re, , Figure 7.21 (a) Common-emitter BJT transistor; (b) approximate model for the, configuration of Fig. 7.21a., , emitter terminals. In this configuration, the base current is the input current while the, output current is still Ic. Recall from Chapter 3 that the base and collector currents, are related by the following equation:, Ic Ib, , (7.16), , The current through the diode is therefore determined by, Ie Ic Ib Ib Ib, Ie ( 1)Ib, , and, , (7.17), , However, since the ac beta is typically much greater than 1, we will use the following approximation for the current analysis:, Ie Ib, , (7.18), , The input impedance is determined by the following ratio:, V, V, Zi i be, Ii, Ib, The voltage Vbe is across the diode resistance as shown in Fig. 7.22. The level of re, is still determined by the dc current IE. Using Ohm’s law gives, Vi Vbe Iere Ibre, , Figure 7.22 Determining Zi using the approximate model., , 318, , Chapter 7, , BJT Transistor Modeling
Page 330 :
re, Substituting yields, V, Ir, Zi be be, Ib, Ib, Zi re, , and, , (7.19), CE, , In essence, Eq. (7.19) states that the input impedance for a situation such as shown, in Fig. 7.23 is beta times the value of re. In other words, a resistive element in the, emitter leg is reflected into the input circuit by a multiplying factor . For instance,, if re 6.5 as in Example 7.4 and 160 (quite typical), the input impedance has, increased to a level of, Zi re (160)(6.5 ) 1.04 k, For the common-emitter configuration, typical values of Zi defined by re, range from a few hundred ohms to the kilohm range, with maximums of, about 6–7 k., , Figure 7.23 Impact of re on, input impedance., , For the output impedance, the characteristics of interest are the output set of Fig., 7.24. Note that the slope of the curves increases with increase in collector current., The steeper the slope, the less the level of output impedance (Zo). The re model of, Fig. 7.21 does not include an output impedance, but if available from a graphical, analysis or from data sheets, it can be included as shown in Fig. 7.25., IC (mA), Slope =, 10, , 50 µA, , 1, ro, 1, , 40 µA, , 8, , 30 µA, ro2 > ro1, 20 µA, , 6, , 10 µA, , 4, , I B = 0 µA, , 2, Slope =, 0, , Figure 7.25 Including ro in the, transistor equivalent circuit., , 10, , 1, ro, 2, , 20, , VCE, , Figure 7.24 Defining ro for the, common-emitter configuration., , For the common-emitter configuration, typical values of Zo are in the range of, 40 to 50 k., For the model of Fig. 7.25, if the applied signal is set to zero, the current Ic is, 0 A and the output impedance is, Zo ro, , (7.20), CE, , Of course, if the contribution due to ro is ignored as in the re model, the output impedance is defined by Zo ., The voltage gain for the common-emitter configuration will now be determined, for the configuration of Fig. 7.26 using the assumption that Zo . The effect of, including ro will be considered in Chapter 8. For the defined direction of Io and polarity of Vo,, Vo IoRL, 7.5 The re Transistor Model, , 319
Page 331 :
re, , Figure 7.26 Determining the, voltage and current gain for the, common-emitter transistor amplifier., , The minus sign simply reflects the fact that the direction of Io in Fig. 7.26 would establish a voltage Vo with the opposite polarity. Continuing gives, Vo IoRL IcRL IbRL, Vi IiZi Ib re, , and, so that, and, , Vo, I RL, Av , b, Vi, Ib re, RL, Av , re, , (7.21), CE,ro , , The resulting minus sign for the voltage gain reveals that the output and input voltages are 180° out of phase., The current gain for the configuration of Fig. 7.26:, I, Ib, I, Ai o c , Ib, Ib, Ii, and, , Ai , , CE,ro , , (7.22), , Using the facts that the input impedance is re, the collector current is Ib, and the, output impedance is ro, the equivalent model of Fig. 7.27 can be an effective tool in, the analysis to follow. For typical parameter values, the common-emitter configuration can be considered one that has a moderate level of input impedance, a high voltage and current gain, and an output impedance that may have to be included in the, network analysis., , Figure 7.27 re model for the, common-emitter transistor configuration., , EXAMPLE 7.5, , 320, , Given 120 and IE 3.2 mA for a common-emitter configuration with ro ,, determine:, (a) Zi., (b) Av if a load of 2 k is applied., (c) Ai with the 2 k load., Chapter 7, , BJT Transistor Modeling
Page 332 :
re, Solution, 26 mV, 26 mV, (a) re 8.125 , IE, 3.2 mA, and Zi re (120)(8.125 ) 975 , RL, 2 k, (b) Eq. (7.21): Av , 246.15, re, 8.125 , I, (c) Ai o , Ii, , 120, , Common Collector Configuration, For the common-collector configuration, the model defined for the common-emitter, configuration of Fig. 7.21 is normally applied rather than defining a model for the, common-collector configuration. In subsequent chapters, a number of commoncollector configurations will be investigated and the impact of using the same model, will become quite apparent., , 7.6 THE HYBRID EQUIVALENT MODEL, It was pointed out in Section 7.5 that the re model for a transistor is sensitive to the, dc level of operation of the amplifier. The result is an input resistance that will vary, with the dc operating point. For the hybrid equivalent model to be described in this, section, the parameters are defined at an operating point that may or may not reflect, the actual operating conditions of the amplifier. This is due to the fact that specification sheets cannot provide parameters for an equivalent circuit at every possible operating point. They must choose operating conditions that they believe reflect the general characteristics of the device. The hybrid parameters as shown in Fig. 7.28 are, drawn from the specification sheet for the 2N4400 transistor described in Chapter 3., The values are provided at a dc collector current of 1 mA and a collector-to-emitter, voltage of 10 V. In addition, a range of values is provided for each parameter for guidance in the initial design or analysis of a system. One obvious advantage of the specification sheet listing is the immediate knowledge of typical levels for the parameters, of the device as compared to other transistors., The quantities hie, hre, hfe, and hoe of Fig. 7.28 are called the hybrid parameters, and are the components of a small-signal equivalent circuit to be described shortly., For years, the hybrid model with all its parameters was the chosen model for the educational and industrial communities. Presently, however, the re model is applied more, frequently, but often with the hoe parameter of the hybrid equivalent model to provide, , Min., , Max., , hie, , 0.5, , 7.5, , k, , Voltage feedback ratio, (IC = 1 mA dc, VCE = 10 V dc, f = 1 kHz), , hre, , 0.1, , 8.0, , 104, , Small-signal current gain, (IC = 1 mA dc, VCE = 10 V dc, f = 1 kHz) 2N4400, , hfe, , 20, , 250, , —, , Output admittance, (IC = 1 mA dc, VCE = 10 V dc, f = 1 kHz), , hoe, , 1.0, , 30, , 1 S, , Input impedance, (IC = 1 mA dc, VCE = 10 V dc, f = 1 kHz) 2N4400, , Figure 7.28 Hybrid parameters for the 2N4400 transistor., , 7.6 The Hybrid Equivalent Model, , 321
Page 333 :
re, some measure for the output impedance. Since specification sheets do provide the hybrid parameters and the hybrid model continues to receive a good measure of attention, it is quite important that the hybrid model be covered in some detail in this book., Once developed, the similarities between the re and hybrid models will be quite apparent. In fact, once the components of one are defined for a particular operating point,, the parameters of the other model are immediately available., Our description of the hybrid equivalent model will begin with the general twoport system of Fig. 7.29. The following set of equations (7.23) is only one of a number of ways in which the four variables of Fig. 7.29 can be related. It is the most frequently employed in transistor circuit analysis, however, and therefore is discussed in, detail in this chapter., , Figure 7.29 Two-port system., , Vi h11Ii h12Vo, , (7.23a), , Io h21Ii h22Vo, , (7.23b), , The parameters relating the four variables are called h-parameters from the word, “hybrid.” The term hybrid was chosen because the mixture of variables (V and I ) in, each equation results in a “hybrid” set of units of measurement for the h-parameters., A clearer understanding of what the various h-parameters represent and how we can, determine their magnitude can be developed by isolating each and examining the resulting relationship., If we arbitrarily set Vo 0 (short circuit the output terminals) and solve for h11, in Eq. (7.23a), the following will result:, V, h11 i, Ii, , , , Vo 0, , ohms, , (7.24), , The ratio indicates that the parameter h11 is an impedance parameter with the units, of ohms. Since it is the ratio of the input voltage to the input current with the output, terminals shorted, it is called the short-circuit input-impedance parameter. The subscript 11 of h11 defines the fact that the parameter is determined by a ratio of quantities measured at the input terminals., If Ii is set equal to zero by opening the input leads, the following will result for, h12:, , , , V, h12 i, Vo, , Ii 0, , unitless, , (7.25), , The parameter h12, therefore, is the ratio of the input voltage to the output voltage, with the input current equal to zero. It has no units since it is a ratio of voltage levels and is called the open-circuit reverse transfer voltage ratio parameter. The subscript 12 of h12 reveals that the parameter is a transfer quantity determined by a ratio of input to output measurements. The first integer of the subscript defines the, 322, , Chapter 7, , BJT Transistor Modeling
Page 334 :
re, measured quantity to appear in the numerator; the second integer defines the source, of the quantity to appear in the denominator. The term reverse is included because, the ratio is an input voltage over an output voltage rather than the reverse ratio typically of interest., If in Eq. (7.23b) Vo is equal to zero by again shorting the output terminals, the, following will result for h21:, , , , I, h21 o, Ii, , Vo0, , unitless, , (7.26), , Note that we now have the ratio of an output quantity to an input quantity. The term, forward will now be used rather than reverse as indicated for h12. The parameter h21, is the ratio of the output current to the input current with the output terminals shorted., This parameter, like h12, has no units since it is the ratio of current levels. It is formally called the short-circuit forward transfer current ratio parameter. The subscript, 21 again indicates that it is a transfer parameter with the output quantity in the numerator and the input quantity in the denominator., The last parameter, h22, can be found by again opening the input leads to set, I1 0 and solving for h22 in Eq. (7.23b):, , , , I, h22 o, Vo, , Ii0, , siemens, , (7.27), , Since it is the ratio of the output current to the output voltage, it is the output conductance parameter and is measured in siemens (S). It is called the open-circuit output admittance parameter. The subscript 22 reveals that it is determined by a ratio of, output quantities., Since each term of Eq. (7.23a) has the unit volt, let us apply Kirchhoff’s voltage, law “in reverse” to find a circuit that “fits” the equation. Performing this operation, will result in the circuit of Fig. 7.30. Since the parameter h11 has the unit ohm, it is, represented by a resistor in Fig. 7.30. The quantity h12 is dimensionless and therefore, simply appears as a multiplying factor of the “feedback” term in the input circuit., Since each term of Eq. (7.23b) has the units of current, let us now apply Kirchhoff’s current law “in reverse” to obtain the circuit of Fig. 7.31. Since h22 has the, units of admittance, which for the transistor model is conductance, it is represented, by the resistor symbol. Keep in mind, however, that the resistance in ohms of this resistor is equal to the reciprocal of conductance (1/h22)., The complete “ac” equivalent circuit for the basic three-terminal linear device is, indicated in Fig. 7.32 with a new set of subscripts for the h-parameters. The notation, of Fig. 7.32 is of a more practical nature since it relates the h-parameters to the resulting ratio obtained in the last few paragraphs. The choice of letters is obvious from, the following listing:, , Figure 7.30 Hybrid input, equivalent circuit., , h11 → input resistance → hi, h12 → reverse transfer voltage ratio → hr, , Figure 7.31 Hybrid output, equivalent circuit., , Figure 7.32 Complete hybrid, equivalent circuit., , 7.6 The Hybrid Equivalent Model, , 323
Page 335 :
re, h21 → forward transfer current ratio → hf, h22 → output conductance → ho, The circuit of Fig. 7.32 is applicable to any linear three-terminal electronic device or, system with no internal independent sources. For the transistor, therefore, even though, it has three basic configurations, they are all three-terminal configurations, so that the, resulting equivalent circuit will have the same format as shown in Fig. 7.32. In each, case, the bottom of the input and output sections of the network of Fig. 7.32 can be, connected as shown in Fig. 7.33 since the potential level is the same. Essentially,, therefore, the transistor model is a three-terminal two-port system. The h-parameters,, however, will change with each configuration. To distinguish which parameter has, been used or which is available, a second subscript has been added to the h-parameter notation. For the common-base configuration, the lowercase letter b was added,, while for the common-emitter and common-collector configurations, the letters e and, c were added, respectively. The hybrid equivalent network for the common-emitter, configuration appears with the standard notation in Fig. 7.33. Note that Ii Ib, Io , Ic, and through an application of Kirchhoff’s current law, Ie Ib Ic. The input voltage is now Vbe, with the output voltage Vce. For the common-base configuration of, Fig. 7.34, Ii Ie, Io Ic with Veb Vi and Vcb Vo. The networks of Figs. 7.33 and, 7.34 are applicable for pnp or npn transistors., The fact that both a Thévenin and Norton circuit appear in the circuit of Fig. 7.32, was further impetus for calling the resultant circuit a hybrid equivalent circuit. Two, additional transistor equivalent circuits, not to be discussed in this text, called the, , Figure 7.33 Common-emitter configuration: (a) graphical symbol; (b) hybrid, equivalent circuit., , Figure 7.34 Common-base configuration: (a) graphical symbol; (b) hybrid, equivalent circuit., , 324, , Chapter 7, , BJT Transistor Modeling
Page 336 :
re, z-parameter and y-parameter equivalent circuits, use either the voltage source or the, current source, but not both, in the same equivalent circuit. In Section 7.7, the magnitudes of the various parameters will be found from the transistor characteristics in, the region of operation resulting in the desired small-signal equivalent network for, the transistor., For the common-emitter and common-base configurations, the magnitude of hr, and ho is often such that the results obtained for the important parameters such as Zi,, Zo, Av, and Ai are only slightly affected if they (hr and ho) are not included in the, model., Since hr is normally a relatively small quantity, its removal is approximated by, hr 0 and hrVo 0, resulting in a short-circuit equivalent for the feedback element, as shown in Fig. 7.35. The resistance determined by 1/ho is often large enough to be, ignored in comparison to a parallel load, permitting its replacement by an opencircuit equivalent for the CE and CB models, as shown in Fig. 7.35., The resulting equivalent of Fig. 7.36 is quite similar to the general structure of, the common-base and common-emitter equivalent circuits obtained with the re model., In fact, the hybrid equivalent and the re models for each configuration have been repeated in Fig. 7.37 for comparison. It should be reasonably clear from Fig. 7.37a that, , Ii, , Io, , +, , +, , hi, , Vi, , Vo, , h f Ii, , –, , –, Figure 7.36 Approximate hybrid equivalent model., , Figure 7.35 Effect of removing hre and hoe from the, hybrid equivalent circuit., , Ib, , Ic, , Ib, c, , b, , h ie, , Ic, c, , b, , β re, , h fe Ib, , e, , e, , β Ib, , e, , e, , (a), Ic, , Ie, e, , c, , hib, , b, , Ic, , Ie, e, , c, , re, , h f b Ib, , b, , b, , α Ie, , e, , (b), , Figure 7.37 Hybrid versus re model: (a) common-emitter configuration;, (b) common-base configuration., , 7.6 The Hybrid Equivalent Model, , 325
Page 337 :
re, , and, , hie re, , (7.28), , hfe , , (7.29), , ac, , From Fig. 7.37b,, , and, , hib re, , (7.30), , hfb 1, , (7.31), , In particular, note that the minus sign in Eq. (7.31) accounts for the fact that the current source of the standard hybrid equivalent circuit is pointing down rather than in, the actual direction as shown in the re model of Fig. 7.37b., , EXAMPLE 7.6, , Given IE 2.5 mA, hfe 140, hoe 20 S ( mho), and hob 0.5, (a) The common-emitter hybrid equivalent circuit., (b) The common-base re model., , S, determine:, , Solution, 26 mV, 26 mV, (a) re 10.4 , 2.5 mA, IE, hie re (140)(10.4 ) 1.456 k, 1, 1, ro 50 k, hoe, 20 S, Note Fig. 7.38., , c, , b, Ib, h ie, , Figure 7.38 Common-emitter, hybrid equivalent circuit for the, parameters of example 7.6., , 1.456 kΩ, , 140 Ib, , e, , e, , (b) re 10.4 , 1, 1, ro 2 M, hob, 0.5 S, , 1,, Note Fig. 7.39., , Figure 7.39 Common-base re, model for the parameters of example 7.6., , 326, , 1, = 50 kΩ, h oe, , Chapter 7, , BJT Transistor Modeling
Page 338 :
re, A series of equations relating the parameters of each configuration for the hybrid, equivalent circuit is provided in Appendix A. In Section 7.8, we demonstrate that the, hybrid parameter hfe ( ac) is the least sensitive of the hybrid parameters to a change, in collector current. Assuming, therefore, that hfe is a constant for the range of, interest, is a fairly good approximation. It is hie re that will vary significantly with, IC and should be determined at operating levels, since it can have a real impact on, the gain levels of a transistor amplifier., , 7.7 GRAPHICAL DETERMINATION OF, THE h-PARAMETERS, Using partial derivatives (calculus), it can be shown that the magnitude of the hparameters for the small-signal transistor equivalent circuit in the region of operation, for the common-emitter configuration can be found using the following equations:*, v, vbe, vbe, , hie i , ii, ib, ib, , , , v, vbe, vbe, hre i , , vo, vce, vce, i, i, i, hfe o c c, ib, ib, ii, , VCE constant, , , , IB constant, , , , VCE constant, , io, ic, ic, hoe , , , vo, vce, vce, , , , IB constant, , (ohms), , (7.32), , (unitless), , (7.33), , (unitless), , (siemens), , (7.34), , (7.35), , In each case, the symbol refers to a small change in that quantity around the, quiescent point of operation. In other words, the h-parameters are determined in the, region of operation for the applied signal so that the equivalent circuit will be the, most accurate available. The constant values of VCE and IB in each case refer to a condition that must be met when the various parameters are determined from the characteristics of the transistor. For the common-base and common-collector configurations, the proper equation can be obtained by simply substituting the proper values, of vi, vo, ii, and io., The parameters hie and hre are determined from the input or base characteristics,, while the parameters hfe and hoe are obtained from the output or collector characteristics. Since hfe is usually the parameter of greatest interest, we shall discuss the operations involved with equations, such as Eqs. (7.32) through (7.35), for this parameter first. The first step in determining any of the four hybrid parameters is to find, the quiescent point of operation as indicated in Fig. 7.40. In Eq. (7.34) the condition, VCE constant requires that the changes in base current and collector current be taken, along a vertical straight line drawn through the Q-point representing a fixed collector-to-emitter voltage. Equation (7.34) then requires that a small change in collector, current be divided by the corresponding change in base current. For the greatest accuracy, these changes should be made as small as possible., , *The partial derivative vi/ii provides a measure of the instantaneous change in vi due to an instantaneous, change in ii., , 7.7 Graphical Determination of the h-Parameters, , 327
Page 339 :
re, , Figure 7.40 hfe determination., , In Fig. 7.40, the change in ib was chosen to extend from IB1 to IB2 along the perpendicular straight line at VCE. The corresponding change in ic is then found by drawing the horizontal lines from the intersections of IB1 and IB2 with VCE constant to, the vertical axis. All that remains is to substitute the resultant changes of ib and ic into, Eq. (7.34). That is,, i, hfe c, ib, , (2.7 1.7) mA, , (20 10) A, VCE constant, , , , , , VCE 8.4 V, , 103, , 100, 10 106, In Fig. 7.41, a straight line is drawn tangent to the curve IB through the Q-point, to establish a line IB constant as required by Eq. (7.35) for hoe. A change in vCE, was then chosen and the corresponding change in iC determined by drawing the horizontal lines to the vertical axis at the intersections on the IB constant line. Substituting into Eq. (7.35), we get, , Figure 7.41 hoe determination., , 328, , Chapter 7, , BJT Transistor Modeling
Page 340 :
re, (2.2 2.1) mA, ic, hoe , , (10 7) V IB 15, vce IB constant, , , , , , A, , 3, , 0.1 10, 33 A/V 33 106 S 33 S, 3, To determine the parameters hie and hre the Q-point must first be found on the input or base characteristics as indicated in Fig. 7.42. For hie, a line is drawn tangent, to the curve VCE 8.4 V through the Q-point to establish a line VCE constant as, required by Eq. (7.32). A small change in vbe was then chosen, resulting in a corresponding change in ib. Substituting into Eq. (7.32), we get, vbe, hie , ib, , , , VCE constant, , (733 718) mV, , (20 10) A, , , , VCE 8.4 V, , 15 103, , 1.5 k, 10 106, , Figure 7.42 hie determination., , The last parameter, hre, can be found by first drawing a horizontal line through, the Q-point at IB 15 A. The natural choice then is to pick a change in vCE and, find the resulting change in vBE as shown in Fig. 7.43., Substituting into Eq. (7.33), we get, vbe, (733 725) mV, 8 103, 4 104, hre , vce IB constant, (20 0) V, 20, , , , For the transistor whose characteristics have appeared in Figs. 7.40 through 7.43,, the resulting hybrid small-signal equivalent circuit is shown in Fig. 7.44., 7.7 Graphical Determination of the h-Parameters, , 329
Page 341 :
re, , Figure 7.43 hre determination., , Figure 7.44 Complete hybrid, equivalent circuit for a transistor, having the characteristics that, appear in Figs. 7.40 through 7.43., , As mentioned earlier, the hybrid parameters for the common-base and commoncollector configurations can be found using the same basic equations with the proper, variables and characteristics., Table 7.1 lists typical parameter values in each of the three configurations for the, broad range of transistors available today. The minus sign indicates that in Eq. (7.34), as one quantity increased in magnitude, within the change chosen, the other decreased, in magnitude., , TABLE 7.1 Typical Parameter Values for the CE, CC, and CB, Transistor Configurations, Parameter, hi, hr, hf, ho, 1/ho, , 330, , Chapter 7, , CE, , CC, , CB, , 01 k, 02.5 104, 50, 25 A/V, 40 k, , 01 k, 1, 50, 25 A/V, 40 k, , 20 , 03.0 104, 0.98, 00.5 A/V0, 2 M, , BJT Transistor Modeling
Page 342 :
re, Note in retrospect (Section 3.5: Transistor Amplifying Action) that the input resistance of the common-base configuration is low, while the output resistance is high., Consider also that the short-circuit current gain is very close to 1. For the commonemitter and common-collector configurations, note that the input resistance is much, higher than that of the common-base configuration and that the ratio of output to input resistance is about 401. Consider also for the common-emitter and common-base, configurations that hr is very small in magnitude. Transistors are available today with, values of hfe that vary from 20 to 600. For any transistor, the region of operation and, conditions under which it is being used will have an effect on the various h-parameters. The effect of temperature and collector current and voltage on the h-parameters, is discussed in Section 7.8., , 7.8 VARIATIONS OF TRANSISTOR, PARAMETERS, There are a large number of curves that can be drawn to show the variations of the, h-parameters with temperature, frequency, voltage, and current. The most interesting, and useful at this stage of the development include the h-parameter variations with, junction temperature and collector voltage and current., In Fig. 7.45, the effect of the collector current on the h-parameter has been indicated. Take careful note of the logarithmic scale on the vertical and horizontal axes., Logarithmic scales will be examined in Chapter 11. The parameters have all been normalized to unity so that the relative change in magnitude with collector current can, easily be determined. On every set of curves, such as in Fig. 7.46, the operating point, at which the parameters were found is always indicated. For this particular situation,, the quiescent point is at the intersection of VCE 5.0 V and IC 1.0 mA. Since the, frequency and temperature of operation will also affect the h-parameters, these quantities are also indicated on the curves. At 0.1 mA, hfe is about 0.5 or 50% of its value, at 1.0 mA, while at 3 mA, it is 1.5 or 150% of that value. In other words, if hfe 50, at IC 1.0 mA, hfe has changed from a value of 0.5(50) 25 to 1.5(50) 75, with, , Figure 7.45 Hybrid parameter variations with collector current., , 7.8 Variations of Transistor Parameters, , 331
Page 343 :
re, , Figure 7.46 Hybrid parameter variations with collector–emitter potential., , a change of IC from 0.1 to 3 mA. Consider, however, the point of operation at, IC 50 mA. The magnitude of hre is now approximately 11 times that at the defined, Q-point, a magnitude that may not permit eliminating this parameter from the equivalent circuit. The parameter hoe is approximately 35 times the normalized value. This, increase in hoe will decrease the magnitude of the output resistance of the transistor, to a point where it may approach the magnitude of the load resistor. There would then, be no justification in eliminating hoe from the equivalent circuit on an approximate, basis., In Fig. 7.46, the variation in magnitude of the h-parameters on a normalized basis has been indicated with changes in collector voltage. This set of curves was normalized at the same operating point of the transistor discussed in Fig. 7.45 so that a, comparison between the two sets of curves can be made. Note that hie and hfe are relatively steady in magnitude while hoe and hre are much larger to the left and right of, the chosen operating point. In other words, hoe and hre are much more sensitive to, changes in collector voltage than are hie and hfe., It is interesting to note from Figs. 7.45 and 7.46 that the value of hfe appears to, change the least. Therefore, the specific value of current gain, whether hfe or , can,, on an approximate and relative basis, be considered fairly constant for the range of, collector current and voltage., The value of hie re does vary considerably with collector current as one might, expect due to the sensitivity of re to emitter (IE IC) current. It is therefore a quantity that should be determined as close to operating conditions as possible. For values below the specified VCE, hre is fairly constant, but it does increase measurably for, higher values. It is indeed fortunate that for most applications the magnitude of hre, and hoe are such that they can usually be ignored. They are quite sensitive to collector current and collector-to-emitter voltage., In Fig. 7.47, the variation in h-parameters has been plotted for changes in junction temperature. The normalization value is taken to be room temperature: T 25°C., The horizontal scale is a linear scale rather than a logarithmic scale as was employed, for Figs. 7.45 and 7.46. In general, all the parameters increase in magnitude with temperature. The parameter least affected, however, is hoe, while the input impedance hie, changes at the greatest rate. The fact that hfe will change from 50% of its normalized, value at 50°C to 150% of its normalized value at 150°C indicates clearly that the, operating temperature must be carefully considered in the design of transistor circuits., 332, , Chapter 7, , BJT Transistor Modeling
Page 344 :
re, , Figure 7.47 Hybrid parameter, variations with temperature., , PROBLEMS, , § 7.2 Amplification in the AC Domain, 1. (a) What is the expected amplification of a BJT transistor amplifier if the dc supply is set to, zero volts?, (b) What will happen to the output ac signal if the dc level is insufficient? Sketch the effect on, the waveform., (c) What is the conversion efficiency of an amplifier in which the effective value of the current through a 2.2-k load is 5 mA and the drain on the 18-V dc supply is 3.8 mA?, 2. Can you think of an analogy that would explain the importance of the dc level on the resulting, ac gain?, , §, , 7.3 BJT Transistor Modeling, , 3. What is the reactance of a 10- F capacitor at a frequency of 1 kHz? For networks in which the, resistor levels are typically in the kilohm range, is it a good assumption to use the short-circuit, equivalence for the conditions just described? How about at 100 kHz?, 4. Given the common-base configuration of Fig. 7.48, sketch the ac equivalent using the notation, for the transistor model appearing in Fig. 7.5., , Figure 7.48 Problem 4, , Problems, , 333
Page 345 :
re, 5. (a) Describe the differences between the re and hybrid equivalent models for a BJT transistor., (b) For each model, list the conditions under which it should be applied., , §, , 7.4 The Important Parameters: Zi, Zo, Av, Ai, , 6. (a) For the configuration of Fig. 7.7, determine Zi if Vs 40 mV, Rsense 0.5 k, and Ii , 20 A., (b) Using the results of part (a), determine Vi if the applied source is changed to 12 mV with, an internal resistance of 0.4 k., 7. (a) For the network of Fig. 7.10, determine Zo if V 600 mV, Rsense 10 k, and Io , 10 A., (b) Using the Zo obtained in part (a), determine IL for the configuration of Fig. 7.11 if RL , 2.2 k and Iamplifier 6 mA., 8. Given the BJT configuration of Fig. 7.49, determine:, (a), (b), (c), (d), , Vi., Zi., AvNL., Avs., , Ii = 10 µA, , +, Vs, , Zi, , 18 mV, , +, , +, , 0.6 kΩ, , Vi, , –, , –, , BJT, transistor, amplifier, Aυ, , Vo = 3.6 V, , –, , NL, , Figure 7.49 Problem 8, , 9. For the BJT amplifier of Fig. 7.50, determine:, (a), (b), (c), (d), (e), (f), , Ii., Zi., Vo., Io., Ai using the results of parts (a) and (d)., Ai using Eq. (7.10)., , Ii, 1 kΩ, , +, Vs, , Zi, 12 mV, , –, , Io, , Vi = 4 mV, , –, , Figure 7.50 Problem 9, , 334, , Chapter 7, , +, , +, , BJT Transistor Modeling, , BJT, transistor, amplifier, Aυ = –180, , Vo, , –, , RL, , 0.51 kΩ
Page 346 :
re, §, , 7.5 The re Transistor Model, , 10. For the common-base configuration of Fig. 7.17, an ac signal of 10 mV is applied, resulting in, an emitter current of 0.5 mA. If 0.980, determine:, (a) Zi., (b) Vo if RL 1.2 k., (c) Av Vo / Vi., (d) Zo with ro ., (e) Ai Io /Ii., (f) Ib., 11. For the common-base configuration of Fig. 7.17, the emitter current is 3.2 mA and, Determine the following if the applied voltage is 48 mV and the load is 2.2 k., (a) re., (b) Zi., (c) Ic., (d) Vo., (e) Av., (f) Ib., , is 0.99., , 12. Using the model of Fig. 7.27, determine the following for a common-emitter amplifier if, 80, IE (dc) 2 mA, and ro 40 k., (a) Zi., (b) Ib., (c) Ai Io / Ii IL /Ib if RL 1.2 k., (d) Av if RL 1.2 k., 13. The input impedance to a common-emitter transistor amplifier is 1.2 k with, ro 50 k, and RL 2.7 k. Determine:, (a) re., (b) Ib if Vi 30 mV., (c) Ic., (d) Ai Io/Ii IL/Ib., (e) Av Vo/Vi., , §, , 140,, , 7.6 The Hybrid Equivalent Model, , 14. Given IE (dc) 1.2 mA, 120, and ro 40 k, sketch the:, (a) Common-emitter hybrid equivalent model., (b) Common-emitter re equivalent model., (c) Common-base hybrid equivalent model., (d) Common-base re equivalent model., 15. Given hie 2.4 k, hfe 100, hre 4104, and hoe 25 S, sketch the:, (a) Common-emitter hybrid equivalent model., (b) Common-emitter re equivalent model., (c) Common-base hybrid equivalent model., (d) Common-base re equivalent model., 16. Redraw the common-emitter network of Fig. 7.3 for the ac response with the approximate hybrid equivalent model substituted between the appropriate terminals., , Problems, , 335
Page 347 :
re, 17. Redraw the network of Fig. 7.51 for the ac response with the re model inserted between the appropriate terminals. Include ro., 18. Redraw the network of Fig. 7.52 for the ac response with the re model inserted between the appropriate terminals. Include ro., , Figure 7.52 Problem 18, , Figure 7.51 Problem 17, , 19. Given the typical values of hie 1 k, hre 2 104, and Av 160 for the input configuration of Fig. 7.53:, (a) Determine Vo in terms of Vi., (b) Calculate Ib in terms of Vi., (c) Calculate Ib if hreVo is ignored., (d) Determine the percent difference in Ib using the following equation:, Ib(without hre) Ib(with hre), % difference in Ib 100%, Ib(without hre), Figure 7.53 Problems 19, 21, , (e) Is it a valid approach to ignore the effects of hreVo for the typical values employed in this, example?, 20. Given the typical values of RL 2.2 k and hoe 20 S, is it a good approximation to ignore, the effects of 1/hoe on the total load impedance? What is the percent difference in total loading, on the transistor using the following equation?, RL RL(1/hoe), 100%, % difference in total load , RL, 21. Repeat Problem 19 using the average values of the parameters of Fig. 7.28 with Av 180., 22. Repeat Problem 20 for RL 3.3 k and the average value of hoe in Fig. 7.28., , §, , 7.7 Graphical Determination of the h-Parameters, , 23. (a) Using the characteristics of Fig. 7.40, determine hfe at IC 6 mA and VCE 5 V., (b) Repeat part (a) at IC 1 mA and VCE 15 V., , 336, , Chapter 7, , BJT Transistor Modeling
Page 348 :
re, 24. (a) Using the characteristics of Fig. 7.41, determine hoe at IC 6 mA and VCE 5 V., (b) Repeat part (a) at IC 1 mA and VCE 15 V., 25. (a) Using the characteristics of Fig. 7.42, determine hie at IB 20 A and VCE 20 V., (b) Repeat part (a) at IB 5 A and VCE 10 V., 26. (a) Using the characteristics of Fig. 7.43, determine hre at IB 20 A., (b) Repeat part (a) at IB 30 A., * 27. Using the characteristics of Figs. 7.40 and 7.42, determine the approximate CE hybrid equivalent model at IB 25 A and VCE 12.5 V., * 28. Determine the CE re model at IB 25 A and VCE 12.5 V using the characteristics of Figs., 7.40 and 7.42., * 29. Using the results of Fig. 7.44, sketch the re equivalent model for the transistor having the characteristics appearing in Figs. 7.40 through 7.43. Include ro., , §, , 7.8 Variations of Transistor Parameters, , For Problems 30 through 34, use Figs. 7.45 through 7.47., 30. (a) Using Fig. 7.45, determine the magnitude of the percent change in hfe for an IC change from, 0.2 mA to 1 mA using the equation, hfe(0.2 mA) hfe(1 mA), % change , 100%, hfe(0.2 mA), , , , , , (b) Repeat part (a) for an IC change from 1 mA to 5 mA., 31. Repeat Problem 30 for hie (same changes in IC)., 32. (a) If hoe 20 S at IC 1 mA on Fig. 7.45, what is the approximate value of hoe at IC , 0.2 mA?, (b) Determine its resistive value at 0.2 mA and compare to a resistive load of 6.8 k. Is it a, good approximation to ignore the effects of 1/hoe in this case?, 33. (a) If hoe 20 S at IC 1 mA on Fig. 7.45, what is the approximate value of hoe at IC , 10 mA?, (b) Determine its resistive value at 10 mA and compare to a resistive load of 6.8 k. Is it a, good approximation to ignore the effects of 1/hoe in this case?, 34. (a) If hre 2 104 at IC 1 mA on Fig. 7.45, determine the approximate value of hre at, 0.1 mA., (b) Using the value of hre determined in part (a), can hre be ignored as a good approximation, if Av 210?, * 35. (a) Reviewing the characteristics of Fig. 7.45, which parameter changed the least for the full, range of collector current?, (b) Which parameter changed the most?, (c) What are the maximum and minimum values of 1/hoe? Is the approximation 1/hoeRL RL, more appropriate at high or low levels of collector current?, (d) In which region of current spectrum is the approximation hreVce 0 the most appropriate?, 36. (a) Reviewing the characteristics of Fig. 7.47, which parameter changed the most with increase, in temperature?, (b) Which changed the least?, (c) What are the maximum and minimum values of hfe? Is the change in magnitude significant? Was it expected?, (d) How does re vary with increase in temperature? Simply calculate its level at three or four, points and compare their magnitudes., (e) In which temperature range do the parameters change the least?, *Please Note: Asterisks indicate more difficult problems., , Problems, , 337
Page 349 :
CHAPTER, , 8, , BJT Small-Signal, Analysis, 8.1 INTRODUCTION, The transistor models introduced in Chapter 7 will now be used to perform a smallsignal ac analysis of a number of standard transistor network configurations. The networks analyzed represent the majority of those appearing in practice today. Modifications of the standard configurations will be relatively easy to examine once the, content of this chapter is reviewed and understood., Since the re model is sensitive to the actual point of operation, it will be our primary model for the analysis to be performed. For each configuration, however, the, effect of an output impedance is examined as provided by the hoe parameter of the, hybrid equivalent model. To demonstrate the similarities in analysis that exist between, models, a section is devoted to the small-signal analysis of BJT networks using solely, the hybrid equivalent model. The analysis of this chapter does not include a load resistance RL or source resistance Rs. The effect of both parameters is reserved for a, systems approach in Chapter 10., The computer analysis section includes a brief description of the transistor model, employed in the PSpice software package. It demonstrates the range and depth of the, computer analysis systems available today and how relatively easy it is to enter a complex network and print out the desired results., , 8.2 COMMON-EMITTER FIXED-BIAS, CONFIGURATION, The first configuration to be analyzed in detail is the common-emitter fixed-bias network of Fig. 8.1. Note that the input signal Vi is applied to the base of the transistor, while the output Vo is off the collector. In addition, recognize that the input current, Ii is not the base current but the source current, while the output current Io is the collector current. The small-signal ac analysis begins by removing the dc effects of VCC, and replacing the dc blocking capacitors C1 and C2 by short-circuit equivalents, resulting in the network of Fig. 8.2., Note in Fig. 8.2 that the common ground of the dc supply and the transistor emitter terminal permits the relocation of RB and RC in parallel with the input and output, sections of the transistor, respectively. In addition, note the placement of the important network parameters Zi, Zo, Ii, and Io on the redrawn network. Substituting the re, model for the common-emitter configuration of Fig. 8.2 will result in the network of, Fig. 8.3., 338
Page 350 :
VCC, , RC, RB, , Io, , C, , C, , Ii, , Vo, C2, , B, , Vi, , Io, , B, , Vi, , RC, , Zo, , C1, Zi, , Vo, , Ii, , RB, , Zi, , E, , Figure 8.1 Common-emitter fixed-bias configuration., , Zo, , E, , Figure 8.2 Network of Figure 8.1 following, the removal of the effects of VCC, C1, and C 2., , Ib, , Ii, , +Z, , Ic, c, , b, , Io, , i, , Vi, , Figure 8.3 Substituting the re, model into the network of Fig., 8.2., , β re, , RB, , β Ib, , ro, , +, Vo, , RC, , –, , –, Zo, , The next step is to determine , re, and ro. The magnitude of is typically obtained from a specification sheet or by direct measurement using a curve tracer or, transistor testing instrument. The value of re must be determined from a dc analysis, of the system, and the magnitude of ro is typically obtained from the specification, sheet or characteristics. Assuming that , re, and ro have been determined will result, in the following equations for the important two-port characteristics of the system., Zi: Figure 8.3 clearly reveals that, Zi RBre, , ohms, , (8.1), , For the majority of situations RB is greater than re by more than a factor of 10, (recall from the analysis of parallel elements that the total resistance of two parallel, resistors is always less than the smallest and very close to the smallest if one is much, larger than the other), permitting the following approximation:, Zi re, , ohms, , (8.2), , RB10re, , Zo: Recall that the output impedance of any system is defined as the impedance, Zo determined when Vi 0. For Fig. 8.3, when Vi 0, Ii Ib 0, resulting in an, open-circuit equivalence for the current source. The result is the configuration of, Fig. 8.4., Zo RCro, , ohms, , Zo, ro, , RC, , (8.3), , If ro 10 RD, the approximation RCro RC is frequently applied and, Zo RC, , 8.2, , ro10RC, , (8.4), , Common-Emitter Fixed-Bias Configuration, , Figure 8.4 Determining Zo for, the network of Fig. 8.3., , 339
Page 351 :
Av:, , The resistors ro and RC are in parallel,, , and, , Vo Ib(RC ro), , but, , Vi, Ib , rc, , , , so that, , Vi, Vo (RC ro), re, , and, , Vo, (RC ro), Av , re, Vi, , (8.5), , RC, Av , re, , (8.6), , If ro 10RC,, , ro10RC, , Note the explicit absence of in Eqs. (8.5 and 8.6), although we recognize that , must be utilized to determine re., Ai: The current gain is determined in the following manner: Applying the current-divider rule to the input and output circuits,, , with, , (ro)(Ib), Io , ro RC, , and, , Io, ro, , ro RC, Ib, , (RB)(Ii), Ib , RB re, , or, , RB, Ib, , RB re, Ii, , The result is, RB, Io, Io Ib, ro, Ai , ro RC RB re, Ii, Ib Ii, , , , and, , , , , , RBro, Io, Ai , (ro RC)(RB re), Ii, , (8.7), , which is certainly an unwieldy, complex expression., However, if ro 10RC and RB 10re, which is often the case,, Io, RBro, Ai , Ii, (ro)(RB), and, , Ai , , (8.8), ro10RC, RB10re, , The complexity of Eq. (8.7) suggests that we may want to return to an equation such, as Eq. (7.10), which utilizes Ao and Zi. That is,, Zi, Ai Av, RC, , (8.9), , Phase Relationship: The negative sign in the resulting equation for Av reveals, that a 180° phase shift occurs between the input and output signals, as shown in Fig., 8.5., 340, , Chapter 8, , BJT Small-Signal Analysis
Page 352 :
VCC, Vo, RC, RB, Vi, 0, , Vo, t, , 0, , t, , Vi, , Figure 8.5 Demonstrating the, 180° phase shift between input, and output waveforms., , For the network of Fig. 8.6:, (a) Determine re., (b) Find Zi (with ro )., (c) Calculate Zo (with ro )., (d) Determine Av (with ro )., (e) Find Ai (with ro )., (f) Repeat parts (c) through (e) including ro 50 k in all calculations and compare, results., , EXAMPLE 8.1, , 12 V, 3 kΩ, 470 kΩ, Ii, Vi, 10 µ F, , Io, Vo, 10 µ F, , β = 100, ro = 50 kΩ, , Zo, , Zi, , Figure 8.6, , Example 8.1., , Solution, (a) DC analysis:, VCC VBE, 12 V 0.7 V, IB 24.04 A, RB, 470 k, IE ( 1)IB (101)(24.04 A) 2.428 mA, 26 mV, 26 mV, re 10.71 , IE, 2.428 mA, (b) re (100)(10.71 ) 1.071 k, Zi RBre 470 k1.071 k 1.069 k, (c) Zo RC 3 k, RC, 3 k, (d) Av 280.11, re, 10.71 , (e) Since RB 10re(470 k 10.71 k), Ai 100, 8.2, , Common-Emitter Fixed-Bias Configuration, , 341
Page 353 :
(f) Zo roRC 50 k3 k 2.83 k vs. 3 k, 2.83 k, roRC, Av 264.24 vs. 280.11, 10.71 , re, (100)(470 k)(50 k), RBro, Ai , (ro RC)(RB re), (50 k 3 k)(470 k 1.071 k), 94.13 vs. 100, As a check:, (264.24)(1.069 k), Zi, Ai Av , 94.16, 3 k, RC, which differs slightly only due to the accuracy carried through the calculations., , 8.3 VOLTAGE-DIVIDER BIAS, The next configuration to be analyzed is the voltage-divider bias network of Fig. 8.7., Recall that the name of the configuration is a result of the voltage-divider bias at the, input side to determine the dc level of VB., VCC, Io, RC, R1, Vo, , C, Ii, , C2, , B, Vi, , Zo, , C1, E, , Zi, , R2, RE, , CE, , Figure 8.7 Voltage-divider bias, configuration., , Substituting the re equivalent circuit will result in the network of Fig. 8.8. Note, the absence of RE due to the low-impedance shorting effect of the bypass capacitor,, CE. That is, at the frequency (or frequencies) of operation, the reactance of the capacitor is so small compared to RE that it is treated as a short circuit across RE. When, Ii, b, , c, , Ib, , +, Vi, , +, , Io, Zi, , R1, , –, , β re, , R2, e, , β Ib, , ro, , Vo, , RC, e, , Zo, , –, , R', , Figure 8.8 Substituting the re equivalent circuit into the ac equivalent network of Fig. 8.7., , 342, , Chapter 8, , BJT Small-Signal Analysis
Page 355 :
And if R 10re,, Io, R, Ai , Ii, R, Io, Ai , Ii, , and, , (8.18), ro10RC, R 10re, , As an option,, Zi, Ai Av, RC, Phase relationship:, between Vo and Vi., , EXAMPLE 8.2, , For, (a), (b), (c), (d), (e), (f), , (8.19), , The negative sign of Eq. (8.14) reveals a 180° phase shift, , the network of Fig. 8.9, determine:, re., Zi., Zo (ro )., Av (ro )., Ai (ro )., The parameters of parts (b) through (e) if ro 1/hoe 50 k and compare results., 22 V, Io, 6.8 kΩ, 10 µF, , 56 kΩ, , Vo, 10 µ F, , β = 90, , Vi, , Zo, , Ii, 8.2 kΩ, Zi, , 1.5 kΩ, , 20 µ F, , Figure 8.9 Example 8.2., , Solution, (a) DC: Testing RE, , 10R2, (90)(1.5 k), 135 k, , 10(8.2 k), 82 k (satisfied), , Using the approximate approach,, R2, (8.2 k)(22 V), VB VCC 2.81 V, R1 R2, 56 k 8.2 k, VE VB VBE 2.81 V 0.7 V 2.11 V, 344, , Chapter 8, , BJT Small-Signal Analysis
Page 356 :
VE, 2.11 V, IE 1.41 mA, RE, 1.5 k, 26 mV, 26 mV, re 18.44 , IE, 1.41 mA, (b) R R1R2 (56 k)(8.2 k) 7.15 k, Zi R re 7.15 k(90)(18.44 ) 7.15 k1.66 k, 1.35 k, (c) Zo RC 6.8 k, 6.8 k, RC, (d) Av 368.76, 18.44 , re, (e) The condition R 10re (7.15 k 10(1.66 k) 16.6 k is not, satisfied. Therefore,, (90)(7.15 k), R, Ai , 7.15 k 1.66 k 73.04, R re, (f) Zi 1.35 k, Zo RCro 6.8 k50 k 5.98 k vs. 6.8 k, RC ro, 5.98 k, Av 324.3 vs. 368.76, re, 18.44 , The condition, ro 10RC (50 k 10(6.8 k) 68 k), is not satisfied. Therefore,, , R ro, (90)(7.15 k)(50 k), , Ai , , (ro RC)(R re), (50 k 6.8 k)(7.15 k 1.66 k), 64.3 vs. 73.04, There was a measurable difference in the results for Zo, Av, and Ai because the, condition ro 10RC was not satisfied., , 8.4 CE EMITTER-BIAS CONFIGURATION, The networks examined in this section include an emitter resistor that may or may, not be bypassed in the ac domain. We will first consider the unbypassed situation and, then modify the resulting equations for the bypassed configuration., , Unbypassed, The most fundamental of unbypassed configurations appears in Fig. 8.10. The re, equivalent model is substituted in Fig. 8.11, but note the absence of the resistance ro., The effect of ro is to make the analysis a great deal more complicated, and considering the fact that in most situations its effect can be ignored, it will not be included in, the current analysis. However, the effect of ro will be discussed later in this section., Applying Kirchhoff’s voltage law to the input side of Fig. 8.11 will result in, Vi Ibre Ie RE, or, , Vi Ibre ( 1)IbRE, 8.4, , CE Emitter-Bias Configuration, , 345
Page 357 :
VCC, , Ii, b, , c, , Ib, , +, , +, β re, , RC, RB, , Io, , Io, , Vo, , Ii, , β Ib, , Zi, C2, , Zo, , Zb, Vi, , RB, , RC, , Vo, , e, , Vi, , Ie = ( β + 1)Ib, , C1, RE, , Zo, RE, , –, , Zi, , Figure 8.10 CE emitter-bias configuration., , –, , Figure 8.11 Substituting the re equivalent circuit into the ac equivalent network of Fig. 8.10., , and the input impedance looking into the network to the right of RB is, Vi, Zb re ( 1)RE, Ib, β, , re, , Zb, , The result as displayed in Fig. 8.12 reveals that the input impedance of a transistor with an unbypassed resistor RE is determined by, Zb re ( 1)RE, , RE, , (8.20), , Since is normally much greater than 1, the approximate equation is the following:, Zb re RE, Figure 8.12 Defining the input, impedance of a transistor with an, unbypassed emitter resistor., , Zb (re RE), , and, , (8.21), , Since RE is often much greater than re, Eq. (8.21) can be further reduced to, Zb RE, Zi:, , (8.22), , Returning to Fig. 8.11, we have, Zi RBZb, , (8.23), , Zo: With Vi set to zero, Ib 0 and Ib can be replaced by an open-circuit equivalent. The result is, Zo RC, , (8.24), , Av :, Vi, Ib , Zb, and, , Vo Io RC IbRC, , , , Vi, RC, Zb, with, , 346, , Chapter 8, , Vo, RC, Av , Zb, Vi, BJT Small-Signal Analysis, , (8.25)
Page 358 :
Substituting Zb (re RE) gives, RC, Vo, Av , re RE, Vi, , (8.26), , and for the approximation Zb RE,, Vo, RC, Av , Vi, RE, , (8.27), , Note again the absence of from the equation for Av., Ai: The magnitude of RB is often too close to Zb to permit the approximation, Ib Ii. Applying the current-divider rule to the input circuit will result in, RBIi, Ib , RB Zb, and, , Ib, RB, , Ii, RB Zb, , In addition,, , Io Ib, , and, , Io, , Ib, , so that, , Io, Io Ib, Ai , Ii, Ib Ii, RB, , RB Zb, , and, , or, , Io, RB, Ai , Ii, RB Zb, , (8.28), , Zi, Ai Av, RC, , (8.29), , Phase relationship: The negative sign in Eq. (8.25) again reveals a 180° phase, shift between Vo and Vi., Effect of ro: The equations appearing below will clearly reveal the additional, complexity resulting from including ro in the analysis. Note in each case, however,, that when certain conditions are met, the equations return to the form just derived., The derivation of each equation is beyond the needs of this text and is left as an exercise for the reader. Each equation can be derived through careful application of the, basic laws of circuit analysis such as Kirchhoff’s voltage and current laws, source, conversions, Thévenin’s theorem, and so on. The equations were included to remove, the nagging question of the effect of ro on the important parameters of a transistor, configuration., Zi:, ( 1) RC /ro, Zb re 1, (RC RE)/ro RE, , , , , , (8.30), , 8.4 CE Emitter-Bias Configuration, , 347
Page 359 :
Since the ratio RC/ro is always much less than ( 1),, ( 1)RE, Zb re , 1 (RC RE)/ro, For ro 10(RC RE),, Zb re ( 1)RE, which compares directly with Eq. (8.20)., In other words, if ro 10(RC RE), all the equations derived earlier will result., Since 1 , the following equation is an excellent one for most applications:, Zb (re RE), Zo:, , (8.31), ro10(RCRE), , (ro re), Zo RC ro , re, 1 , RE, , , , However, ro, , , , (8.32), , re, and, , , Zo RC ro 1 , re, 1 , RE, , , , , , , , , , which can be written as, 1, Zo RC ro 1 , re, 1, , , RE, , Typically 1/ and re/RE are less than one with a sum usually less than one. The, result is a multiplying factor for ro greater than one. For 100, re 10 , and, RE 1 k:, 1, 1, 1, 50, re, 1, 10 , 1, 0.02, , , , RE, 100, 1000 , Zo RC 51ro, , and, , which is certainly simply RC. Therefore,, Zo RC, , (8.33), Any level of ro, , which was obtained earlier., Av :, , RC, RC, re, 1 , ro, Zb, ro, Vo, Av , R, C, Vi, 1 , ro, , , , 348, , Chapter 8, , BJT Small-Signal Analysis, , , , (8.34)
Page 361 :
(b) Testing the condition ro 10(RC RE),, 40 k 10(2.2 k 0.56 k), 40 k 10(2.76 k) 27.6 k (satisfied ), Therefore,, Zb (re RE) 120(5.99 560 ), 67.92 k, Zi RB Zb 470 k67.92 k, 59.34 k, , and, , (c) Zo RC 2.2 k, (d) ro 10RC is satisfied. Therefore,, Vo, RC, (120)(2.2 k), Av , Zb, Vi, 67.92 k, 3.89, compared to 3.93 using Eq. (8.27): Av RC/RE., Zi, 59.34 k, (e) Ai Av (3.89) , RC, 2.2 k, 104.92, compared to 104.85 using Eq. (8.28): Ai RB/(RB Zb)., , , , EXAMPLE 8.4, , , , Repeat the analysis of Example 8.3 with CE in place., , Solution, (a) The dc analysis is the same, and re 5.99 ., (b) RE is “shorted out” by CE for the ac analysis. Therefore,, Zi RBZb RBre 470 k(120)(5.99 ), 470 k718.8 717.70 , (c) Zo RC 2.2 k, RC, (d) Av , re, 2.2 k, 367.28 (a significant increase), 5.99 , , RB, (120)(470 k), (e) Ai , 470, k 718.8 , RB Zb, 119.82, , EXAMPLE 8.5, , 350, , For the network of Fig. 8.14, determine (using appropriate approximations):, (a) re., (b) Zi., (c) Zo., (d) Av., (e) Ai., Chapter 8, , BJT Small-Signal Analysis
Page 362 :
16 V, Io, 2.2 kΩ, 90 kΩ, , C1, , Ii, , Zo, , Zi, , 10 kΩ, 0.68 kΩ, , +, , C2, β = 210, ro = 50 kΩ, , Vi, , Vo, , CE, , –, Figure 8.14 Example 8.5., , Solution, (a) Testing RE, , 10R2, (210)(0.68 k), 142.8 k, , 10(10 k), , 100 k (satisfied), , R2, 10 k, VB VCC (16 V) 1.6 V, R1 R2, 90 k 10 k, VE VB VBE 1.6 V 0.7 V 0.9 V, VE, 0.9 V, IE 1.324 mA, RE, 0.68 k, 26 mV, 26 mV, re 19.64 , IE, 1.324 mA, (b) The ac equivalent circuit is provided in Fig. 8.15. The resulting configuration is, now different from Fig. 8.11 only by the fact that now, RB R R1R2 9 k, Ii, , +, Io, , +, Vi, , 10 kΩ, , 90 kΩ, , 2.2 kΩ, , Vo, , 0.68 kΩ, , –, , Zi, , Zo, , –, R', , Figure 8.15 The ac equivalent circuit of Fig. 8.14., , The testing conditions of ro 10 (RC RE) and ro 10RC are both satisfied. Using, the appropriate approximations yields, Zb RE 142.8 k, Zi RBZb 9 k142.8 k, 8.47 k, 8.4 CE Emitter-Bias Configuration, , 351
Page 363 :
(c) Zo RC 2.2 k, 2.2 k, RC, (d) Av 3.24, 0.68 k, RE, Zi, 8.47 k, (e) Ai Av (3.24) , RC, 2.2 k, 12.47, , , , EXAMPLE 8.6, , , , Repeat Example 8.5 with CE in place., , Solution, (a) The dc analysis is the same, and re 19.64 ., (b) Zb re (210)(19.64 ) 4.12 k, Zi RBZb 9 k4.12 k, 2.83 k, (c) Zo RC 2.2 k, RC, 2.2 k, (d) Av 112.02 (a significant increase), re, 19.64 k, Zi, 2.83 k, (e) Ai Av (112.02) , RL, 2.2 k, 144.1, , , , , , Another variation of an emitter-bias configuration appears in Fig. 8.16. For the dc, analysis, the emitter resistance is RE1 RE2, while for the ac analysis, the resistor RE, in the equations above is simply RE1 with RE2 bypassed by CE., VCC, Io, RC, C2, , RB, , Vo, C1, Vi, Ii, Zo, , RE, , 1, , Zi, RE, , 2, , CE, , Figure 8.16 An emitter-bias, configuration with a portion of, the emitter-bias resistance bypassed in the ac domain., , 8.5 EMITTER-FOLLOWER, CONFIGURATION, When the output is taken from the emitter terminal of the transistor as shown in Fig., 8.17, the network is referred to as an emitter-follower. The output voltage is always, slightly less than the input signal due to the drop from base to emitter, but the ap352, , Chapter 8, , BJT Small-Signal Analysis
Page 364 :
VCC, , C, , RB, Ii, , B, , Vi, C1, , C2, Vo, , E, Io, , Zi, , RE, Zo, , Figure 8.17 Emitter-follower, configuration., , proximation Av 1 is usually a good one. Unlike the collector voltage, the emitter, voltage is in phase with the signal Vi. That is, both Vo and Vi will attain their positive and negative peak values at the same time. The fact that Vo “follows” the magnitude of Vi with an in-phase relationship accounts for the terminology emitterfollower., The most common emitter-follower configuration appears in Fig. 8.17. In fact, because the collector is grounded for ac analysis, it is actually a common-collector configuration. Other variations of Fig. 8.17 that draw the output off the emitter with Vo , Vi will appear later in this section., The emitter-follower configuration is frequently used for impedance-matching purposes. It presents a high impedance at the input and a low impedance at the output,, which is the direct opposite of the standard fixed-bias configuration. The resulting effect is much the same as that obtained with a transformer, where a load is matched, to the source impedance for maximum power transfer through the system., Substituting the re equivalent circuit into the network of Fig. 8.17 will result in, the network of Fig. 8.18. The effect of ro will be examined later in the section., Ii, , b, , c, , Ib, , +, β Ib, , β re, Zi, Vi, , RB, e, Zb, , –, , RE, , +, , Io, Zo, Ie = ( β + 1) Ib, , Vo, , Figure 8.18 Substituting the re, equivalent circuit into the ac, equivalent network of Fig. 8.17., , –, , Zi: The input impedance is determined in the same manner as described in the, preceding section:, , with, , Zi RBZb, , (8.37), , Zb re ( 1)RE, , (8.38), , 8.5 Emitter-Follower Configuration, , 353
Page 365 :
or, , Zb (re RE), , (8.39), , Zb RE, , (8.40), , and, , Zo: The output impedance is best described by first writing the equation for the, current Ib:, Vi, Ib , Zb, and then multiplying by ( 1) to establish Ie. That is,, Vi, Ie ( 1)Ib ( 1) , Zb, Substituting for Zb gives, ( 1)Vi, Ie , re ( 1)RE, or, , Vi, Ie , [re/( 1)] RE, , but, , ( 1) , , and, , re, re, re, 1, , Vi, Ie , re RE, , so that, re, , +, , Vo, Ie, , (8.41), , If we now construct the network defined by Eq. (8.41), the configuration of Fig., 8.19 will result., To determine Zo, Vi is set to zero and, , RE, , Vi, , –, , Zo, , Figure 8.19 Defining the output impedance for the emitter-follower configuration., , Zo REre, , (8.42), , Since RE is typically much greater than re, the following approximation is often applied:, Zo re, , (8.43), , Av: Figure 8.19 can be utilized to determine the voltage gain through an application of the voltage-divider rule:, REVi, Vo , RE re, and, , Vo, RE, Av , Vi, RE re, , (8.44), , Since RE is usually much greater than re, RE re RE and, Vo, Av 1, Vi, 354, , Chapter 8, , BJT Small-Signal Analysis, , (8.45)
Page 367 :
Av:, , ( 1)RE/Zb, Av , RE, 1 , ro, , (8.52), , If the condition ro 10RE is satisfied and we use the approximation 1 ,, , RE, Av , Zb, , EXAMPLE 8.7, , But, , Zb (re RE), , so that, , RE, Av , (re RE), , and, , RE, Av , re RE, , (8.53), ro10RE, , For the emitter-follower network of Fig. 8.20, determine:, (a) re., (b) Zi., (c) Zo., (d) Av., (e) Ai., (f) Repeat parts (b) through (e) with ro 25 k and compare results., 12 V, , 220 kΩ, 10 µ F, , β = 100, ro = ∞ Ω, , Vi, Ii, , 10 µ F, Vo, Io, , Zi, , 3.3 kΩ, Zo, , Figure 8.20 Example 8.7., , Solution, , VCC VBE, (a) IB , RB ( 1)RE, 12 V 0.7 V, 20.42 A, 220 k (101)3.3 k, IE ( 1)IB, (101)(20.42 A) 2.062 mA, 26 mV, 26 mV, re 12.61 , 2.062 mA, IE, 356, , Chapter 8, , BJT Small-Signal Analysis
Page 368 :
(b) Zb re ( 1)RE, (100)(12.61 ) (101)(3.3 k), 1.261 k 333.3 k, 334.56 k RE, Zi RB Zb 220 k334.56 k, 132.72 k, (c) Zo REre 3.3 k12.61 , 12.56 re, 3.3 k, Vo, RE, (d) Av , RE re, 3.3 k 12.61 , Vi, 0.996 1, (100)(220 k), RB, (e) Ai 39.67, 220 k 334.56 k, RB Zb, versus, , , , , , Zi, 132.72 k, Ai Av (0.996) 40.06, RE, 3.3 k, (f) Checking the condition ro 10RE, we have, 25 k 10(3.3 k) 33 k, which is not satisfied. Therefore,, ( 1)RE, (100 1)3.3 k, (100)(12.61 ) , Zb re , RE, 3.3 k, 1 , 1 , ro, 25 k, , with, , 1.261 k 294.43 k, 295.7 k, Zi RBZb 220 k295.7 k, 126.15 k vs. 132.72 k obtained earlier, Zo RE re 12.56 as obtained earlier, ( 1)RE/Zb, (100 1)(3.3 k)/295.7 k, Av , RE, 3.3 k, 1 , 1, 25 , k, ro, 0.996 1, , , , , , , , , , matching the earlier result., In general, therefore, even though the condition ro 10RE was not satisfied, the, results for Zo and Av are the same, with Zi only slightly less. The results suggest that, for most applications a good approximation for the actual results can be obtained by, simply ignoring the effects of ro for this configuration., The network of Fig. 8.21 is a variation of the network of Fig. 8.17, which employs a voltage-divider input section to set the bias conditions. Equations (8.37), through (8.47) are changed only by replacing RB by R R1R2., The network of Fig. 8.22 will also provide the input/output characteristics of an, emitter-follower but includes a collector resistor RC. In this case RB is again replaced, by the parallel combination of R1 and R2. The input impedance Zi and output impedance Zo are unaffected by RC since it is not reflected into the base or emitter equiv8.5 Emitter-Follower Configuration, , 357
Page 369 :
VCC, , VCC, , R1, , RC, , R1, , Ii, , C1, , Vi, , Vi, C2, , C1, , C2, Vo, , R2, , Zi, , Vo, , Io, , R2, , Zi, , RE, , Io, RE, , Zo, , Zo, , Figure 8.22 Emitter-follower, configuration with a collector, resistor RC., , Figure 8.21 Emitter-follower, configuration with a voltagedivider biasing arrangement., , alent networks. In fact, the only effect of RC will be to determine the Q-point of operation., , 8.6 COMMON-BASE CONFIGURATION, The common-base configuration is characterized as having a relatively low input and, a high output impedance and a current gain less than 1. The voltage gain, however,, can be quite large. The standard configuration appears in Fig. 8.23, with the commonbase re equivalent model substituted in Fig. 8.24. The transistor output impedance ro, is not included for the common-base configuration because it is typically in the, megohm range and can be ignored in parallel with the resistor RC., Ii, , Ie, , Ic, , +, Vi, , –, , E, Zi, , C, , RE, , +, , Io, RC, , Vo, , B, VEE, , e, , VCC, , –, , +, Zo, , Ic, , Ii, , Vi, , –, , Ie, , c, Io, , RE, , re, , α Ie, , RC, , Zi, , +, Vo, , Zo, , –, , Figure 8.23 Common-base configuration., Figure 8.24 Substituting the re equivalent circuit into the, ac equivalent network of Fig. 8.23., , Zi:, Zi RE re, , (8.54), , Zo RC, , (8.55), , Zo:, , Av :, Vo Io RC (Ic )RC IeRC, 358, , Chapter 8, , BJT Small-Signal Analysis
Page 370 :
Vi, Ie , re, , with, , Vo , , so that, , r R, Vi, , C, , e, , RC, Vo, RC, Av , re, Vi, re, , and, A i:, , Assuming that RE, , (8.56), , re yields, Ie Ii, , and, , Io Ie Ii, , with, , Io, Ai 1, Ii, , (8.57), , Phase relationship: The fact that Av is a positive number reveals that Vo and Vi, are in phase for the common-base configuration., Effect of ro: For the common-base configuration, ro 1/hob is typically in the, megohm range and sufficiently larger than the parallel resistance RC to permit the approximation roRC RC., For, (a), (b), (c), (d), (e), , the network of Fig. 8.25, determine:, re., Zi., Zo., Av., Ai., 10 µ F, , +, , Ii, Zi, , 10 µF, , Ie, , 1 kΩ, Vo, , EXAMPLE 8.8, , α = 0.98, ro = 1 MΩ, , +, , Io, 5 kΩ, , 2V, , 8V, , –, , Zo, , Vo, , –, , Figure 8.25 Example 8.8., , Solution, VEE VBE, 2 V 0.7 V, 1.3 V, (a) IE 1.3 mA, RE, 1 k, 1 k, , (b), (c), (d), (e), , 26 mV, 26 mV, re 20 , IE, 1.3 mA, Zi REre 1 k20 , 19.61 re, Zo RC 5 k, RC, 5 k, Av 250, re, 20 , Ai 0.98 1, , 8.6 Common-Base Configuration, , 359
Page 371 :
8.7 COLLECTOR FEEDBACK, CONFIGURATION, The collector feedback network of Fig. 8.26 employs a feedback path from collector, to base to increase the stability of the system as discussed in Section 4.12. However,, the simple maneuver of connecting a resistor from base to collector rather than base, to dc supply has a significant impact on the level of difficulty encountered when analyzing the network., VCC, , RC, RF, , Io, C, , Vo, C2, , Ii, B, , Vi, , Zo, , C1, E, , Figure 8.26 Collector feedback, configuration., , Zi, , Some of the steps to be performed below are the result of experience working, with such configurations. It is not expected that a new student of the subject would, choose the sequence of steps described below without taking a wrong step or two., Substituting the equivalent circuit and redrawing the network will result in the configuration of Fig. 8.27. The effects of a transistor output resistance ro will be discussed later in the section., B, , +, , Ii, , –, Ib, , β re, , Vi, , RF, I', , +, , Io, , C, , +, , Ic, , β Ib, , RC, , Zi, , –, , Zo V, o, , –, , Figure 8.27 Substituting the re, equivalent circuit into the ac, equivalent network of Fig. 8.26., , Vo Vi, I , RF, , Zi:, with, , Vo IoRC, , and, , Io Ib I, , Since Ib is normally much larger than I ,, Io Ib, , 360, , and, , Vo (Ib)RC IbRC, , but, , Vi, Ib , re, , and, , Vi, RC, Vo RC Vi, re, re, , Chapter 8, , , , BJT Small-Signal Analysis
Page 372 :
Therefore,, Vo, Vi, Vi, 1, Vo Vi, RCVi, RC, I 1 Vi, RF, RF RF, RF, RF, reRF, re, , , , , , The result is, Vi Ibre (Ii I )re Iire I re, 1, RC, Vi Iire 1 reVi, RF, re, , , , , , re, RC, Vi 1 1 Iire, RF, re, , , , or, , , , , , Vi, re, Zi , re, RC, Ii, 1 1 , r, RF, RC eRC, but RC is usually much greater than re and 1 , re, re, , and, , , , , , re, Zi , RC, 1 , RF, , so that, , re, Zi , 1, RC, , , RF, , or, , (8.58), , Zo: If we set Vi to zero as required to define Zo, the network will appear as, shown in Fig. 8.28. The effect of re is removed and RF appears in parallel with RC, and, Zo RC RF, , (8.59), , RF, Ib = 0 A, Vi = 0, , β re, , β Ib = 0 A, , RC, , Zo, , Figure 8.28 Defining Zo for the, collector feedback configuration., , Av:, , At node C of Fig. 8.27,, Io Ib I, , For typical values, Ib, , I and Io Ib., Vo Io RC (Ib)RC, , Substituting Ib Vi/re gives us, Vi, Vo RC, re, and, , Vo, RC, Av , Vi, re, , (8.60), , 8.7 Collector Feedback Configuration, , 361
Page 373 :
Ai:, , Applying Kirchhoff’s voltage law around the outside network loop yields, Vi VRF Vo 0, Ibre (Ib Ii)RF IoRC 0, , and, Using Io Ib, we have, , Ibre Ib RF Ii RF IbRC 0, Ib(re RF RC) IiRF, , and, , Substituting Ib Io/ from Io Ib yields, Io, (re RF RC) IiRF, , , RFIi, Io , re RF RC, , and, , Ignoring re compared to RF and RC gives us, Io, RF, Ai , Ii, RF RC, For RC, , (8.61), , RF,, Io, RF, Ai , Ii, RC, Io, RF, Ai , Ii, RC, , and, , (8.62), , Phase relationship: The negative sign of Eq. (8.60) reveals a 180° phase shift, between Vo and Vi., Effect of ro:, Zi: A complete analysis without applying approximations will result in, RC ro, 1 , RF, , Zi 1, 1, RC ro, , re, RF, RFre, Recognizing that 1/RF 0 and applying the condition ro 10RC,, RC, 1 , RF, , RC, Zi 1, , re, RFre, but typically RC/RF, , 1 and, 1, Zi , RC, 1, , re, RFre, , 362, , Chapter 8, , BJT Small-Signal Analysis, , (8.63)
Page 374 :
re, Zi , 1, RC, , , RF, , or, , (8.64), ro10RC, , as obtained earlier., Zo: Including ro in parallel with RC in Fig. 8.28 will result in, Zo roRC RF, , (8.65), , For ro 10RC,, Zo RC RF, , (8.66), , ro10RC, , as obtained earlier. For the common condition of RF, Zo RC, , RC,, (8.67), , ro10RC, RF, , RC, , Av :, , R r(r R ), 1, , 1, , F, , o, , e, , C, , Av , roRC, 1, , RF, Since RF, , re,, , (8.68), , roRC, , re, , roRC, Av , 1 , RF, , For ro 10RC,, RC, , re, , RC, Av , 1 , RF, , (8.69), ro10RC, , and since RC/RF is typically much less than one,, RC, Av , re, , (8.70), ro10RC, RF, , RC, , as obtained earlier., For, (a), (b), (c), (d), (e), (f), , the network of Fig. 8.29, determine:, re., Zi., Zo., Av., Ai., Repeat parts (b) through (e) with ro 20 k and compare results., 8.7 Collector Feedback Configuration, , EXAMPLE 8.9, , 363
Page 375 :
9V, , 2.7 kΩ, 180 kΩ, , Io, Vo, 10 µF, , Ii, Vi, 10 µF, , β = 200, ro = ∞ Ω, Zo, , Zi, , Figure 8.29 Example 8.9., , Solution, 9 V 0.7 V, VCC VBE, (a) IB , 180, k, (200)2.7 k, RF RC, 11.53 A, IE ( 1)IB (201)(11.53 A) 2.32 mA, 26 mV, 26 mV, re 11.21 , 2.32 mA, IE, 11.21 , re, 11.21 , (b) Zi , 0.005 0.015, 1, RC, 1, 2.7 k, , , 200, 180 k, , RF, 11.21 , 50(11.21 ) 560.5 , 0.02, (c) Zo RCRF 2.7 k180 k 2.66 k, 27 k, RC, (d) Av 240.86, 11.21 , re, (200)(180 k), RF, (e) Ai , 180 k (200)(2.7 k), RF RC, 50, (f) Zi: The condition, R Cro ro 10RC is not satisfied. Therefore,, 2.7 k20 k, 1 , 1 , RF, 180 k, , 1, RC ro , Zi 1, 1, 1, 02.7 k 20 k0, , , re, RF, RFre, (200)(11.21), 180 k, (180 k)(11.21 ), 2.38 k, 1 , 180 k, , 1 0.013, 3, 0.45 10 0.006 103 1.18 103 , 1.64 103, 617.7 vs. 560.5 above, Zo:, Zo roRCRF 20 k2.7 k180 k, 2.35 k vs. 2.66 k above, 364, , Chapter 8, , BJT Small-Signal Analysis
Page 376 :
Av:, , , , , , , , , , 1, 1, 1, 1, (roRC), (2.38 k), RF re, 180 k, 11.21, Av , roRC, 2.38 k, 1, , 1 , RF, 180 k , [5.56 106 8.92 102](2.38 k), , 1 0.013, 209.56 vs. 240.86 above, Ai:, Zi, Ai Av , RC, 617.7 , (209.56), 2.7 k, 47.94 vs. 50 above, For the configuration of Fig. 8.30, Eqs. (8.71) through (8.74) will determine the, variables of interest. The derivations are left as an exercise at the end of the chapter., VCC, , RC, Io, , RF, , Vo, Ii, , C2, , Vi, C1, , Zo, , Zi, , RE, , Figure 8.30 Collector feedback, configuration with an emitter resistor RE., , Zi:, RE, Zi , 1, (RE RC), , , RF, , , , , , (8.71), , Zo:, Zo RCRF, , (8.72), , RC, Av , RE, , (8.73), , Av :, , A i:, 1, Ai , 1, (RE RC), , , RF, , (8.74), , 8.7 Collector Feedback Configuration, , 365
Page 377 :
8.8 COLLECTOR DC FEEDBACK, CONFIGURATION, The network of Fig. 8.31 has a dc feedback resistor for increased stability, yet the capacitor C3 will shift portions of the feedback resistance to the input and output sections of the network in the ac domain. The portion of RF shifted to the input or output side will be determined by the desired ac input and output resistance levels., VCC, , RC, RF, , RF, , 1, , Io, , 2, , Vo, C2, , C3, C1, Vi, , Zo, , Ii, , Figure 8.31 Collector dc feedback configuration., , Zi, , At the frequency or frequencies of operation, the capacitor will assume a shortcircuit equivalent to ground due to its low impedance level compared to the other elements of the network. The small-signal ac equivalent circuit will then appear as, shown in Fig. 8.32., Ii, Ib, , +, Zi, Vi, , +, , Io, RF, , 1, , β re, , β Ib, , ro, , RF, , 2, , RC, , Vo, Zo, , –, , –, , Figure 8.32 Substituting the re, equivalent circuit into the ac, equivalent network of Fig. 8.31., , Zi:, Zi RF1re, , (8.75), , Zo RC RF2ro, , (8.76), , Zo:, , For ro 10RC,, Zo RC RF2, , (8.77), ro10RC, , Av :, R ro RF2RC, Vo Ib R, , and, 366, , Chapter 8, , BJT Small-Signal Analysis
Page 380 :
(d) ro 10RC, therefore,, RF RC, 68 k3 k, Av 2 , re, 9.92 , 2.87 k, , 9.92 , 289.3, , re is satisfied,, , (e) Since the condition RF1, , 140, 140, , 140, Ai , 1.14, 1 0.14, RC, 3 k, 1 , 1 , roRF2, 30 k68 k, 122.8, , 8.9 APPROXIMATE HYBRID EQUIVALENT, CIRCUIT, The analysis using the approximate hybrid equivalent circuit of Fig. 8.35 for the, common-emitter configuration and of Fig. 8.36 for the common-base configuration is, very similar to that just performed using the re model. Although time and priorities, do not permit a detailed analysis of all the configurations discussed thus far, a brief, overview of some of the most important will be included in this section to demonstrate the similarities in approach and the resulting equations., b, , c, Ib, hie, , hfe Ib, , hoe, , e, , e, , e, , Figure 8.35 Approximate, common-emitter hybrid equivalent circuit., , c, Ie, hib, , b, , hfb Ie, , hob, , b, , Figure 8.36 Approximate, common-base hybrid equivalent, circuit., , Since the various parameters of the hybrid model are specified by a data sheet or, experimental analysis, the dc analysis associated with use of the re model is not an, integral part of the use of the hybrid parameters. In other words, when the problem, is presented, the parameters such as hie, hfe, hib, and so on, are specified. Keep in, mind, however, that the hybrid parameters and components of the re model are related by the following equations as discussed in detail in Chapter 7: hie re, hfe , , hoe 1/ro, hfb , and hib re (note Appendix A)., , Fixed-Bias Configuration, For the fixed-bias configuration of Fig. 8.37, the small-signal ac equivalent network, will appear as shown in Fig. 8.38 using the approximate common-emitter hybrid equiv8.9 Approximate Hybrid Equivalent Circuit, , 369
Page 382 :
EXAMPLE 8.11, , For the network of Fig. 8.39, determine:, (a), (b), (c), (d), , 8V, Io, 2.7 kΩ, 330 kΩ, , Zi., Zo., Av., Ai., , Vo, Vi, , hfe = 120, Zo, hie = 1.175 kΩ, hoe = 20 µ A/V, , Ii, , Figure 8.39 Example 8.11., , Zi, , Solution, Zi RBhie 330 k1.175 k, hie 1.171 k, 1, 1, (b) ro 50 k, hoe, 20 A/V, 1, Zo RC 50 k2.7 k 2.56 k RC, hoe, (120)(2.7 k50 k), hfe(RC1/hoe), (c) Av , , 262.34, 1.171 k, hie, (d) Ai hfe 120, (a), , Voltage-Divider Configuration, For the voltage-divider bias configuration of Fig. 8.40, the resulting small-signal ac, equivalent network will have the same appearance as Fig. 8.38, with RB replaced by, R R1R2., VCC, Io, RC, R1, Vo, , Ii, , C2, , hie, hfe, , Vi, C1, , Zo, R2, RE, , Zi, , CE, , Figure 8.40 Voltage-divider, bias configuration., , Zi:, , Zo:, , From Fig. 8.38 with RB R ,, Zi R hie, , (8.87), , Zo RC, , (8.88), , From Fig. 8.38,, , 8.9 Approximate Hybrid Equivalent Circuit, , 371
Page 383 :
Av:, hfe(RC1/hoe), , Av , hie, , (8.89), , hf R, Ai e, R hie, , (8.90), , A i:, , Unbypassed Emitter-Bias Configuration, For the CE unbypassed emitter-bias configuration of Fig. 8.41, the small-signal ac, model will be the same as Fig. 8.11, with re replaced by hie and Ib by hfeIb. The, analysis will proceed in the same manner., VCC, Io, RC, RB, Vo, hie, hfe, , Vi, Ii, , Zo, RE, , Zi, , Figure 8.41 CE unbypassed, emitter-bias configuration., , Zi:, , and, , Zb hfe RE, , (8.91), , Zi RBZb, , (8.92), , Zo RC, , (8.93), , Zo:, , Av :, hfe RC, hfeRC, Av , Zb, hfe RE, and, , RC, Av , RE, , (8.94), , hf RB, Ai e, RB Zb, , (8.95), , A i:, , 372, , Chapter 8, , BJT Small-Signal Analysis
Page 384 :
Zi, Ai Av, RC, , or, , (8.96), , Emitter-Follower Configuration, For the emitter-follower of Fig. 8.42, the small-signal ac model will match Fig. 8.18,, with re hie and hfe. The resulting equations will therefore be quite similar., Zi:, Zb hfe RE, , (8.97), , Zi RBZb, , (8.98), , VCC, , RB, Ii, Vi, , hie, hfe, , Zi, , Vo, Io, , Zo, , RE, , Figure 8.42 Emitter-follower, configuration., , Zo: For Zo, the output network defined by the resulting equations will appear, as shown in Fig. 8.43. Review the development of the equations in Section 8.5 and, hie, Zo RE , 1 hfe, or since 1 hfe hfe,, hie, Zo RE , hfe, , (8.99), , Figure 8.43 Defining Zo for the, emitter-follower configuration., , Av: For the voltage gain, the voltage-divider rule can be applied to Fig. 8.43 as, follows:, RE (Vi), Vo , RE hie/(1 hfe), 8.9 Approximate Hybrid Equivalent Circuit, , 373
Page 386 :
Vi, Ie , hib, , with, so that, , and, , Vi, Vo hfb RC, hib, , Vo, hfb RC, Av , hib, Vi, , (8.105), , Io, Ai hfb 1, Ii, , (8.106), , A i:, , For, (a), (b), (c), (d), , the network of Fig. 8.46, determine:, Zi., Zo., Av., Ai., , EXAMPLE 8.12, , Ii, , +, Vi, , Io, Zi, , 2.2 kΩ, , 4V, , hfb = − 0.99, hib = 14.3 Ω, hob = 0.5 µA/V, , +, , 3.3 kΩ, Vo, , Zo, , 10 V, , –, , –, , Figure 8.46 Example 8.12., , Solution, (a) Zi REhib 2.2 k14.3 14.21 hib, 1, 1, (b) ro 2 M, hob, 0.5 A/V, 1, Zo RC RC 3.3 k, hob, hfb RC, (0.99)(3.3 k), (c) Av 229.91, hib, 14.21, (d) Ai hfb 1, The remaining configurations of Sections 8.1 through 8.8 that were not analyzed, in this section are left as an exercise in the problem section of this chapter. It is assumed that the analysis above clearly reveals the similarities in approach using the re, or approximate hybrid equivalent models, thereby removing any real difficulty with, analyzing the remaining networks of the earlier sections., , 8.10 COMPLETE HYBRID EQUIVALENT, MODEL, The analysis of Section 8.9 was limited to the approximate hybrid equivalent circuit, with some discussion about the output impedance. In this section, we employ the complete equivalent circuit to show the impact of hr and define in more specific terms the, 8.10 Complete Hybrid Equivalent Model, , 375
Page 387 :
impact of ho. It is important to realize that since the hybrid equivalent model has the, same appearance for the common-base, common-emitter, and common-collector configurations, the equations developed in this section can be applied to each configuration. It is only necessary to insert the parameters defined for each configuration. That, is, for a common-base configuration, hfb, hib, and so on, are employed, while for a, common-emitter configuration, hfe, hie, and so on, are utilized. Recall that Appendix, A permits a conversion from one set to the other if one set is provided and the other, is required., Consider the general configuration of Fig. 8.47 with the two-port parameters of, particular interest. The complete hybrid equivalent model is then substituted in Fig., 8.48 using parameters that do not specify the type of configuration. In other words,, the solutions will be in terms of hi, hr, hf, and ho. Unlike the analysis of previous sections of this chapter, the current gain Ai will be determined first since the equations, developed will prove useful in the determination of the other parameters., Io, , +, , Ii, , Rs, , +, , Vi, , Zi, , Vs, , +, , –, , Transistor, , –, , Zo, , Vo, , RL, , –, , Figure 8.47 Two-port system., , Ii, , +, , Ib, hi, , Rs, , +, Vs, , –, , Zi, , Vi, , I, , +, , 1/ho, , Vo, , +, , hr Vo, , hf Ib, , –, –, , Io, , Zo, , –, , Figure 8.48 Substituting the complete hybrid equivalent circuit into the two-port system of Fig. 8.47., , Current Gain, Ai Io /Ii, Applying Kirchhoff’s current law to the output circuit yields, Vo, Io hf Ib I hf Ii hf Ii hoVo, 1/ho, Substituting Vo Io RL gives us, Io hf Ii ho RL Io, Rewriting the equation above, we have, Io ho RL Io hf Ii, and, 376, , Chapter 8, , Io(1 ho RL) hf Ii, BJT Small-Signal Analysis, , RL
Page 388 :
Io, hf, Ai , Ii, 1 hoRL, , so that, , (8.107), , Note that the current gain will reduce to the familiar result of Ai hf if the factor, hoRL is sufficiently small compared to 1., , Voltage Gain, Av Vo /Vi, Applying Kirchhoff’s voltage law to the input circuit results in, Vi Iihi hrVo, Substituting Ii (1 hoRL)Io/hf from Eq. (8.107) and Io Vo/RL from above results in, (1 hoRL)hi, Vo hrVo, Vi , hf RL, Solving for the ratio Vo/Vi yields, hf RL, Vo, Av , hi (hiho hf hr)RL, Vi, , (8.108), , In this case, the familiar form of Av hf RL/hi will return if the factor (hiho , hf hr)RL is sufficiently small compared to hi., , Input Impedance, Zi Vi/Ii, For the input circuit,, Vi hi Ii hrVo, Substituting, , Vo Io RL, , we have, , Vi hi Ii h r RL Io, , Since, , Io, Ai , Ii, Io Ai Ii, , so that the equation above becomes, Vi hiIi hr RL Ai Ii, Solving for the ratio Vi/Ii, we obtain, Vi, Zi hi hr RL Ai, Ii, and substituting, hf, Ai , 1 ho RL, yields, , Vi, h f hr RL, Zi hi , Ii, 1 ho RL, , (8.109), , The familiar form of Zi hi will be obtained if the second factor is sufficiently smaller, than the first., , 8.10 Complete Hybrid Equivalent Model, , 377
Page 389 :
Output Impedance, Zo Vo /Io, The output impedance of an amplifier is defined to be the ratio of the output voltage, to the output current with the signal Vs set to zero. For the input circuit with Vs 0,, hrVo, Ii , Rs hi, Substituting this relationship into the following equation obtained from the output circuit yields, Io hf Ii hoVo, hf hrVo, hoVo, Rs hi, Vo, 1, Zo , Io, ho [hf hr /(hi Rs)], , and, , (8.110), , In this case, the output impedance will reduce to the familiar form Zo 1/ho for the, transistor when the second factor in the denominator is sufficiently smaller than the, first., , EXAMPLE 8.13, , For the network of Fig. 8.49, determine the following parameters using the complete, hybrid equivalent model and compare to the results obtained using the approximate, model., (a) Zi and Z i., (b) Av., (c) Ai Io /Ii and A i Io /I i., (d) Zo (within RC) and, Z o (including RC)., , Figure 8.49 Example 8.13., , Solution, Now that the basic equations for each quantity have been derived, the order in which, they are calculated is arbitrary. However, the input impedance is often a useful quantity to know and therefore will be calculated first. The complete common-emitter hybrid equivalent circuit has been substituted and the network redrawn as shown in Fig., 8.50. A Thévenin equivalent circuit for the input section of Fig. 8.50 will result in the, input equivalent of Fig. 8.51 since ETh Vs and RTh Rs 1 k (a result of RB , 470 k being much greater than Rs 1 k). In this example, RL RC and Io is de378, , Chapter 8, , BJT Small-Signal Analysis
Page 390 :
Ii', , Rs, , 1 kΩ, , Io, , Ii, Ib, , +, , Z'i, , +, , Zi, , 1.6 kΩ, , +, 2 × 10− 4 Vo, , 470 kΩ, , Vi, , Z'o, , Zo, 110 Ib, , 50 kΩ, , 4.7 kΩ, , +, Vo, , –, , Vs, , –, , –, , –, Thevenin, , Figure 8.50 Substituting the complete hybrid equivalent circuit into the ac, equivalent network of Fig. 8.49., I'i, , Rs, , 1 kΩ, , Ii, Z'i, , +, , +, , Zi, , Io, , hie, 1.6 kΩ, , Z'o, , +, hre Vo, 2 × 10− 4 Vo, , Vi, , hfe Ib, 110 Ib, , –, , Vs, , –, , 1, hoe = 50 kΩ, hoe = 20 µS, , –, , +, Zo, 4.7 kΩ, , Vo, , –, , Figure 8.51 Replacing the input section of Fig. 8.50 with a Thévenin equivalent circuit., , fined as the current through RC as in previous examples of this chapter. The output, impedance Zo as defined by Eq. (8.110) is for the output transistor terminals only. It, does not include the effects of RC. Z o is simply the parallel combination of Zo and, RL. The resulting configuration of Fig. 8.51 is then an exact duplicate of the defining, network of Fig. 8.48, and the equations derived above can be applied., Vi, h fe h re RL, (a) Eq. (8.109): Zi hie , Ii, 1 hoe RL, (110)(2 104)(4.7 k), 1.6 k , 1 (20 S)(4.7 k), 1.6 k 94.52 , 1.51 k, versus 1.6 k using simply hie., Z i 470 kZi Zi 1.51 k, (b) Eq. (8.108):, , hfeRL, Vo, Av , hie (hiehoe hfehre)RL, Vi, (110)(4.7 k), , 1.6 k [(1.6 k)(20 S) (110)(2 104)]4.7 k, 517 103 , , 1.6 k (0.032 0.022)4.7 k, 517 103 , , 1.6 k 47 , 313.9, , 8.10 Complete Hybrid Equivalent Model, , 379
Page 391 :
versus 323.125 using Av hfeRL/hie., Io, hfe, 110, (c) Eq. (8.107): Ai , Ii, 1 hoe RL, 1 (20 S)(4.7 k), 110, 100.55, 1 0.094, versus 110 using simply hfe. Since 470 k, , Zi, I i Ii and A i 100.55 also., , Vo, 1, Zo , hoe [hfehre/(hie Rs)], Io, 1, , 20 S [(110)(2 104)/(1.6 k 1 k)], 1, , 20 S 8.46 S, 1, , 11.54 S, 86.66 k, , (d) Eq. (8.110):, , which is greater than the value determined from 1/hoe 50 k., Z o RCZo 4.7 k86.66 k 4.46 k, versus 4.7 k using only RC., Note from the results above that the approximate solutions for Av and Zi were very, close to those calculated with the complete equivalent model. In fact, even Ai was off, by less than 10%. The higher value of Zo only contributed to our earlier conclusion, that Zo is often so high that it can be ignored compared to the applied load. However,, keep in mind that when there is a need to determine the impact of hre and hoe, the, complete hybrid equivalent model must be used, as described above., The specification sheet for a particular transistor typically provides the commonemitter parameters as noted in Fig. 7.28. The next example will employ the same transistor parameters appearing in Fig. 8.49 in a pnp common-base configuration to introduce the parameter conversion procedure and emphasize the fact that the hybrid, equivalent model maintains the same layout., , EXAMPLE 8.14, For the common-base amplifier of Fig. 8.52, determine the following parameters using the complete hybrid equivalent model and compare the results to those obtained, using the approximate model., (a) Zi and Z i., (b) Ai and A i., hie = 1.6 kΩ, hre = 2 × 10− 4, , +, Rs, , Ii', , 1 kΩ, , +, , +, , Ii, , Z'i, , 2.2 kΩ, Zi, , 6V, , –, , Figure 8.52 Example 8.14., , 380, , Chapter 8, , Io, , 3 kΩ, Vi, , Vs, , –, , hfe = 110, hoe = 20 µS, , BJT Small-Signal Analysis, , Z'o, , Zo, , Vo, , 12 V, , –
Page 392 :
(c) Av., (d) Zo and Z o., , Solution, The common-base hybrid parameters are derived from the common-emitter parameters using the approximate equations of Appendix A:, hie, 1.6 k, hib 14.41 , 1 hfe, 1 110, Note how closely the magnitude compares with the value determined from, hie, 1.6 k, hib re 14.55 , , 110, hiehoe, (1.6 k)(20 S), hrb hre 2 104, 1 hfe, 1 110, 0.883 104, hfe, 110, hfb 0.991, 1 hfe, 1 110, hoe, 20 S, hob 0.18 S, 1 hfe, 1 110, Substituting the common-base hybrid equivalent circuit into the network of Fig., , Rs, , 1 kΩ, , Ii', , Ii, , Z'i, , Zi, , +, , +, 3 kΩ, , Vi, , Vs, , –, , hib, , e, Ie, , c, , 14.41 Ω, , Zo, , +, 0.883 × 10−4 Vo, hrb Vo, , − 0.991Ie, hfb Ie, , hob = 0.18 µ S, , Z'o, 2.2 kΩ, , +, Vo, , –, , –, Thévenin, , Io, , –, , b, , b, , Figure 8.53 Small-signal equivalent for the network of Fig. 8.52., , 8.52 will then result in the small-signal equivalent network of Fig. 8.53. The Thévenin, network for the input circuit will result in RTh 3 k1 k 0.75 k for Rs in the, equation for Zo., Vi, h f b h rb RL, (a) Eq. (8.109): Zi hib , Ii, 1 hob RL, (0.991)(0.883 104)(2.2 k), 14.41 , 1 (0.18 S)(2.2 k), 14.41 0.19 , 14.60 , versus 14.41 using Zi hib., Z i 3 kZi Zi 14.60 , (b) Eq. (8.107):, , hfb, Io, Ai , 1 hob RL, Ii, , 8.10 Complete Hybrid Equivalent Model, , 381
Page 393 :
0.991, , 1 (0.18 S)(2.2 k), Since 3 k, , 0.991 hfb, Zi, I i Ii and A i Io/I i 1 also., , Vo, h fb RL, (c) Eq. (8.108): Av , hib (hib hob hfbhrb)RL, Vi, (0.991)(2.2 k), , 14.41 [(14.41 )(0.18 S) (0.991)(0.883 104)]2.2 k, 149.25, versus 151.3 using Av hfb RL/hib., (d) Eq. (8.110):, , 1, Zo , hob[hf b hrb /(hib Rs)], 1, , 0.18 S [(0.991)(0.883 104)/(14.41 0.75 k)], 1, , 0.295 S, 3.39 M, , versus 5.56 M using Zo 1/hob. For Z o as defined by Fig. 8.53:, Z o RCZo 2.2 k3.39 M 2.199 k, versus 2.2 k using Z o RC., , 8.11 SUMMARY TABLE, Now that the most familiar configurations of the small-signal transistor amplifiers, have been introduced, Table 8.1 is presented to review the general characteristics of, each for immediate recall. It must be absolutely clear that the values listed are simply typical values to establish a basis for comparison. The levels obtained in an actual analysis will most likely be different, and certainly different from one configuration to another. Being able to repeat most of the information in the table is an, important first step in developing a general familiarity with the subject matter. For instance, one should now be able to state with some assurance that the emitter-follower, configuration typically has a high input impedance, low output impedance, and a voltage gain slightly less than 1. There should be no need to perform a variety of calculations to recall salient facts such as those above. For the future, it will permit the, study of a network or system without becoming mathematically involved. The function of each component of a design will become increasingly familiar as general facts, such as those above become part of your background., One obvious advantage of being able to recall general facts like the above is an, ability to check the results of a mathematical analysis. If the input impedance of a, common-base configuration is in the kilohm range, there is good reason to recheck, the analysis. However, on the other side of the coin, a result of 22 suggests that, the analysis may be correct., , 382, , Chapter 8, , BJT Small-Signal Analysis
Page 395 :
8.12 TROUBLESHOOTING, Although the terminology troubleshooting suggests that the procedures to be described, are designed simply to isolate a malfunction, it is important to realize that the same, techniques can be applied to ensure that a system is operating properly. In any case,, the testing, checking, or isolating procedures require an understanding of what to expect at various points in the network in both the dc and ac domains. In most cases, a, network operating correctly in the dc mode will also behave properly in the ac domain. In addition, a network providing the expected ac response is most likely biased, as planned. In a typical laboratory setting, both the dc and ac supplies are applied and, the ac response at various points in the network is checked with an oscilloscope as, shown in Fig. 8.54. Note that the black (gnd) lead of the oscilloscope is connected, directly to ground and the red lead is moved from point to point in the network, providing the patterns appearing in Fig. 8.54. The vertical channels are set in the ac mode, to remove any dc component associated with the voltage at a particular point. The, small ac signal applied to the base is amplified to the level appearing from collector, to ground. Note the difference in vertical scales for the two voltages. There is no ac, VCC, , υ o (V), RC, RB, C2, , υo, 0, , C1, , υi, , +, , υe, , υ i (mV), , Rs, , υe, , 0, , t, , 0, , t, Oscilloscope, , RE, , Vs, , t, , CE, , –, (AC-GND-DC switch on AC), Ground strap, , Figure 8.54 Using the oscilloscope to measure and display various voltages of a BJT amplifier., , response at the emitter terminal due to the short-circuit characteristics of the capacitor at the applied frequency. The fact that vo is measured in volts and vi in millivolts, suggests a sizable gain for the amplifier. In general, the network appears to be operating properly. If desired, the dc mode of the multimeter could be used to check VBE, and the levels of VB, VCE, and VE to review whether they lie in the expected range., Of course, the oscilloscope can also be used to compare dc levels simply by switching to the dc mode for each channel., Needless to say, a poor ac response can be due to a variety of reasons. In fact,, there may be more than one problem area in the same system. Fortunately, however,, with time and experience, the probability of malfunctions in some areas can be predicted and an experienced person can isolate problem areas fairly quickly., In general, there is nothing mysterious about the general troubleshooting process., If you decide to follow the ac response, it is good procedure to start with the applied, 384, , Chapter 8, , BJT Small-Signal Analysis
Page 396 :
Figure 8.55 The waveforms resulting from a malfunction in the emitter area., , signal and progress through the system toward the load, checking critical points along, the way. An unexpected response at some point suggests that the network is fine up, to that area, thereby defining the region that must be investigated further. The waveform obtained on the oscilloscope will certainly help in defining the possible problems with the system., If the response for the network of Fig. 8.54 is as appears in Fig. 8.55, the network, has a malfunction that is probably in the emitter area. An ac response across the emitter is unexpected, and the gain of the system as revealed by vo is much lower. Recall, for this configuration that the gain is much greater if RE is bypassed. The response, obtained suggests that RE is not bypassed by the capacitor and the terminal connections of the capacitor and the capacitor itself should be checked. In this case, a checking of the dc levels will probably not isolate the problem area since the capacitor has, an “open-circuit” equivalent for dc. In general, a prior knowledge of what to expect,, a familiarity with the instrumentation, and most important, experience are all factors, that contribute to the development of an effective approach to the art of troubleshooting., , 8.13 PSPICE WINDOWS, Voltage-Divider Configuration Using the Software Transistor, Parameters, Now that the basic maneuvers for developing the network on the schematics grid have, been introduced, the current description will concentrate on the variations introduced, by the ac analysis., Using schematics, the network of Fig. 8.9 (Example 8.2) is developed as shown, in Fig. 8.56. Note the ac source of 1 mV and the printer symbol at the output terminal of the network., The sinusoidal ac source is listed in the SOURCE.slb library as VSIN. Once, 8.13 PSpice Windows, , 385
Page 397 :
Figure 8.56 Using PSpice Windows to analyze the network of, Figure 8.9 (Example 8.2)., , placed on the diagram, double-clicking the symbol will result in the PartName: VSIN, dialog box with a list of options. Each choice can be made by double-clicking the desired quantity, which will then appear in the Name and Value rectangles at the top, of the box. The cursor appears in the Value box, and the desired value can be entered. After each entry, be sure to Save Attr to save the entered attribute. If done properly, the assigned value will appear in the listing., For our analysis, the following choices will be made:, VAMPL 1mV (the peak value of the sinusoidal signal)., FREQ 10kHz (the frequency of interest)., PHASE 0 (no initial phase angle for the sinusoidal signal)., VOFF 0 (no dc offset voltage for the sinusoidal signal)., AC 1mV., If you want to display the value of the ac signal, simply click on Change Display after saving the attribute. For instance, if AC 1mV was just saved and Change, Display was chosen, a Change Attribute dialog box would appear. Since AC is the, name and 1mV the value, choose Value Only, and only the 1mV will be displayed, after the sequence OK-OK., The printer symbol on the collector of the transistor is listed as VPRINT1 under, the SPECIAL.slb library. When placed on the schematic, it dictates that the ac voltage at that point will be printed in the output file (*.out). Double-clicking on the, printer symbol will result in a PRINT1 dialog box, within which the following choices, should be made:, AC ok., MAG ok., PHASE ok., After each entry, be sure to Save Attr or the computer will remind you. The above, choices can be listed next to the printer symbol on the schematic by simply clicking, the Change Display option and choosing the Display Value and Name for each item., The transistor is obtained through the sequence Get New Part icon-LibrariesEVAL.slb-Q2N2222-OK-Place & Close. Since we will want the parameters of the, transistor to match those of the example as closely as possible, one must first click, on the transistor to put it in the active mode (red) and then choose Edit-Model-Edit, Instance Model (Text). Next, the beta (Bf) is set to 90 and Is is set to 2E-15A to result in a base-to-emitter voltage close to 0.7 V. This value of I is the result of nu386, , Chapter 8, , BJT Small-Signal Analysis
Page 398 :
merous runs of the network to find that value of IS that provided a level of VBE closest to 0.7 V. For the remainder of this text, however, this chosen level of IS will remain the same. In most cases, it provides the desired results., VIEWPOINTs have been inserted to display the three dc voltages of interest., Since it has been used recently, VIEWPOINT can be found in the scroll listing at, the top right of the menu bar rather than by returning to the library listing., Choosing the Setup Analysis icon will result in the Analysis Setup dialog box,, in which the AC Sweep must be chosen because of the applied ac source. Clicking, on AC Sweep will result in an AC Sweep and Noise Analysis dialog box, in which, Linear is chosen along with Total Pts: 1, Start Freq: 10kHz, and End Freq: 10kHz., The result will be an analysis at only one frequency. Our initial interest will simply, be in the magnitude of the quantities of interest and not their shape or appearance., Therefore, we should turn to Analysis-Probe Setup and choose Do not auto-run, Probe to save time getting to the desired results., Clicking the Analysis icon will result in a PSpiceAD dialog box that will indicate the AC Analysis is finished. Note also the listing of the frequency applied at the, bottom of the dialog box. Within this box, if we choose File followed by Examine, Output, we will obtain a lengthy listing of input and output data on the analyzed network. Specific headings are duplicated in Fig. 8.57. Under Schematics Netlist, the, nodes assigned to the network are revealed. Note that ground is always defined as the, 0 node and the assumed node of higher potential listed first. The transistor is listed, in the order Collector-Base-Emitter. Under BJT MODEL PARAMETERS, the defining parameters of the device are listed with the set values of IS 2E-15A and , 90. Under SMALL-SIGNAL BIAS SOLUTION, the dc levels at the various nodes, are revealed, which compare directly with the VIEWPOINT values. In particular,, note that VBE is exactly 0.7 V., The next listing, OPERATING POINT INFORMATION, reveals that even, though beta of the BJT MODEL PARAMETERS listing was set at 90, the operating conditions of the network resulted in a dc beta of 48.3 and an ac beta of 55. Fortunately, however, the voltage-divider configuration is less sensitive to changes in beta, in the dc mode, and the dc results are excellent. However, the drop in ac beta had an, effect on the resulting level of Vo: 296.1 mV versus the hand-written solution (with, ro 50 k) of 324.3 mV—a 9% difference. The results are certainly close, but probably not as close as one would like. A closer result (within 7%) could be obtained by, setting all the parameters of the device except IS and beta to zero. However, for the, moment, the impact of the remaining parameters has been demonstrated, and the results will be accepted as sufficiently close to the hand-written levels. Later in this, chapter, an ac model for the transistor will be introduced with results that will be an, exact match with the hand-written solution. The phase angle is 178° versus the ideal, of 180°—a very close match., A plot of the output waveform can be obtained using the Probe option. The, sequence Analysis-Probe Setup-Automatically run Probe after simulation-OK, will result in a MicroSim Probe screen when the Analysis icon is chosen. However, if we follow this procedure without setting the horizontal scale, we will simply end up with a plot point of 296 mV at a frequency of 10 kHz. The horizontal, scale is set by the sequence Analysis-Setup-Transient with the AC Sweep disabled. Clicking the Transient option will result in a Transient dialog box, in which, a number of choices have to be made based on the waveform to be viewed. The, period of the applied signal of 10 kHz is 0.1 ms 100 s. The Print Step option, refers to the time interval between printing or plotting the results of the transient, analysis. For our example, we will choose 1 s to provide 100 plot points per cycle. The Final Time is the last instant the network’s response will be determined., Our choice is 500 s or 0.5 ms to provide five full cycles of the waveform. The, No-Print Delay was chosen as 0 since all the capacitors are essentially short cir8.13 PSpice Windows, , 387
Page 399 :
Figure 8.57 Output file for, the network of Figure 8.56., , 388
Page 400 :
cuits at 10 kHz. If we felt there was a transient phase between energizing the network and reaching a steady-state response, the No-Print Delay could be used to, effectively eliminate this period of time. The last choice of Step Ceiling sets a, maximum time period between response calculations for the system, which we will, set at 1 s. The time between calculations will be adjusted internally by the software package to ensure sufficient data at times when the response may change, faster than usual. However, they will never be separated by a time period greater, than that set by the Step Ceiling., After Simulation, a MicroSim Probe screen will appear showing only the horizontal scale from 0 to 500 s as specified in the Transient dialog box. To obtain a, waveform, one can either choose Trace on the menu bar or the Trace icon (red pattern on a black axis). If the Trace on the menu bar is chosen, one must follow with, Add, and the Add Traces dialog box will appear. Using the icon results in the dialog box immediately. Now one must choose the waveform to be displayed from the, list of Simulation Output Variables. Since we want the collector-to-emitter voltage, of the transistor, V(Q1:c)—an option under Alias names—will be chosen, followed, by an OK. The result is the waveform of Fig. 8.58, with the waveform riding on the, , Figure 8.58 Voltage vc for the network of Figure 8.56., , dc level of 13.45 V. The range of the vertical axis was automatically chosen by the, computer. Five full cycles of the output waveform are displayed (as we expected) with, 100 data points for each cycle. If you would like to see the data points (as shown in, Fig. 8.58), simply turn to Tools-Options-Probe Options and choose Mark Data, Points. Click OK, and the data points will appear. Using the scale of the graph, the, peak-to-peak value of the curve is approximately 13.76 V 13.16 V 0.6 V , 600 mV, resulting in a peak value of 300 mV. Since a 1-mV signal was applied, the, gain is 300, or very close to the values displayed above., If a comparison is to be made between the input and output voltages on the same, graph, the Add Y-Axis option under Plot can be chosen. After it is triggered, choose, 8.13 PSpice Windows, , 389
Page 401 :
Figure 8.59 The voltages vc and vs for the network of Figure 8.56., , the Add Trace icon and select V(Vs:). The result is that both waveforms will appear on the same screen, each with their own vertical scale. Labels can be added to, the waveforms as shown in Fig. 8.59 using Tools-Label-Text. A Text Label dialog, box will appear, in which the desired text can be entered. Click OK, and it can be, placed with the mouse in any location on the graph. Lines can also be added with, Tools-Label-Line. A pencil will appear, which can be used to draw the line with a, left-click at the starting point and another click when the line is in place. Each plot, , Figure 8.60 Two separate plots of vc and vs in Figure 8.56., , 390, , Chapter 8, , BJT Small-Signal Analysis
Page 402 :
can be printed with File-Print-Copies-OK., If two separate graphs are preferred, we can choose the Plot option and select, Add Plot after V has been displayed. Upon selection, another graph will appear, waiting for the next choice. The sequence Trace-Add-V(Vs:) will then result in the graphs, of Fig. 8.60. The labels Vs and Vc were added using the Tools option. If further operations are to be performed on either graph, the SEL defines the active plot., The last waveform of this section will demonstrate the use of the Cursor option, that can be called up using the Tools menu choice or the Cursor Point icon (having, a graph with an arrow drawn from the graph to the vertical axis). The sequence ToolsCursor-Display will result in a line at the dc level of 13.453 V, as shown in the dialog box at the bottom right of the graph of Fig. 8.61. Left-clicking on the mouse, once will result in a horizontal and vertical line intersecting at some point on the, curve. By clicking on the vertical line and holding it down, the vertical line and corresponding horizontal line (on the graph) can be moved across the waveform. At each, point, the vertical and horizontal intersections will appear in the dialog box. If moved, to the first peak value, A1 will be at 13.754 V and 74.825 s. By right-clicking, on the mouse, a second intersection, defined by A2, appears, which also has its location registered in the dialog box. These intersecting lines are moved by holding down, , Figure 8.61 Demonstrating the use of cursors to read specific points on a plot., , the right side of the mouse. The remaining information on the third line of the box, is the difference between the two intersections on the two axis. If A2 is set at the, bottom of the waveform as shown in Fig. 8.61, it will read 13.162 V at 125.17 s,, resulting in a difference between the two of 591.999 mV, or 0.592 V vertically and, 50.35 s horizontally. This is as expected, because the peak-to-peak value matches, the 2 0.296 V 0.592 V obtained earlier. The time interval is essentially 1/4 of, the total period (200 s) of the waveform. The labels A1 and A2 were added using, the Tools-Label-Text sequence or the ABC text icon., The peak and minimum values for the graph of Fig. 8.61 can also be found using the icons appearing in the top right region of the menu bar. Once the desired wave8.13 PSpice Windows, , 391
Page 403 :
form is obtained and the sequence Tools-Cursor-Display applied or the Toggle cursor icon (the icon in the center region of the menu bar with the black dashed axis and, red curve passing through the origin) is chosen, the six icons to the right of the Toggle cursor icon will change to a color pattern indicating they are ready for use. Clicking on the icon with the intersection at the top will automatically place the A1 intersection at the top of the curve. Clicking the next icon to the right will place the, intersection at the bottom (trough) of the curve. The next icon will place the intersec-, , B, , C, , B, , C, βre, , Ib, βre, , βIb, , GAIN = β, F1, , B, βre, , βIb, , Ib, , C, , βIb, , Ib, , F, , E, , E, , E, , Figure 8.62 Using a controlled source to represent the transistor of Figure 8.56., , tion at the steepest slope and the next at the minimum value (matching the trough value)., , Voltage-Divider Configuration—Controlled Source Substitution, The results obtained for any analysis using the transistors provided in the software, package will always be different from those obtained with an equivalent model that, only includes the effect of beta and re. This was demonstrated for the network of Fig., 8.56. If a solution is desired that is limited to the approximate model, then the transistor must be represented by a model such as appearing in Fig. 8.62., For Example 8.2, is 90, with re 1.66 k. The current controlled current, source (CCCS) is found in the ANALOG.slb library as Part F. When you click on, F, the Description above will read Current-controlled current source. After OKPlace & Close, the graphical symbol for the CCCS will appear on the screen as, shown in Fig. 8.63. Since re does not appear within the basic structure of the CCCS,, it must be added in series with the controlling current indicated by the arrow on the, , Figure 8.63 Substituting the controlled source of Figure 8.62 for the transistor, of Figure 8.56., , 392, , Chapter 8, , BJT Small-Signal Analysis
Page 406 :
8. For the network of Fig. 8.71, determine RE and RB if Av 10 and re 3.8 . Assume that, Zb RE., 9. Repeat Problem 7 with RE bypassed. Compare results., * 10. For, (a), (b), (c), , the network of Fig. 8.72:, Determine re., Find Zi and Av., Calculate Ai., , 22 V, 5.6 kΩ, 20 V, , Io, , 330 kΩ, , Vo, Ii, , CC, , β = 80, ro = 40 kΩ, , Vi, , 8.2 kΩ, , CC, , RB, Vo, , Zi, 1.2 kΩ, , β = 120, ro = 80 kΩ, , Vi, , 0.47 kΩ, , RE, , CE, , Figure 8.72 Problem 10, , Figure 8.71 Problem 8, , § 8.5 Emitter-Follower Configuration, 11. For, (a), (b), (c), * 12. For, (a), (b), (c), , the network of Fig. 8.73:, Determine re and re., Find Zi and Zo., Calculate Av and Ai., the network of Fig. 8.74:, Determine Zi and Zo., Find Av., Calculate Vo if Vi 1 mV., 16 V, 12 V, Ii, , 270 kΩ, , β = 110, ro = 50 kΩ, , Vi, , β = 120, ro = 40 kΩ, , Vi, , Ii, Zi, , Io, 2.7 kΩ, , Vo, , Zi, , Vo, , 390 kΩ, , Io, 5.6 kΩ, Zo, , Zo, −8 V, , Figure 8.73 Problem 11, , Figure 8.74 Problem 12, , Problems, , 395
Page 409 :
§ 8.9 Approximate Hybrid Equivalent Circuit, 20. (a) Given 120, re 4.5 , and ro 40 k, sketch the approximate hybrid equivalent, circuit., (b) Given hie 1 k, hre 2104, hfe 90, and hoe 20 S, sketch the re model., 21. For, (a), (b), (c), (d), (e), (f), (g), , the network of Problem 1:, Determine re., Find hfe and hie., Find Zi and Zo using the hybrid parameters., Calculate Av and Ai using the hybrid parameters., Determine Zi and Zo if hoe 50 S., Determine Av and Ai if hoe 50 S., Compare the solutions above with those of Problem 1. (Note: The solutions are available, in Appendix E if Problem 1 was not performed.), , 22. For, (a), (b), (c), , the network of Fig. 8.81:, Determine Zi and Zo., Calculate Av and Ai., Determine re and compare re to hie., 18 V, , 2.2 kΩ, , 68 kΩ, , Io, Ii, , 5 µF, Zo, , 5 µF, , 12 kΩ, Zi, , 1.2 kΩ, , Vo, hfe = 180, hie = 2.75 kΩ, hoe = 25 µS, , 10 µF, , Figure 8.81 Problems 22 and 24, , * 23. For, (a), (b), (c), , the common-base network of Fig. 8.82:, Determine Zi and Zo., Calculate Av and Ai., Determine , , re, and ro., hfb = −0.992, hib = 9.45 Ω, hob = 1 µ A/V, , Ii, , +, , Io, , 10 µ F, 1.2 kΩ, , 2.7 kΩ, , 4V, , 12 V, , 10 µF, , Vi, , Vo, Zi, , –, , Chapter 8, , Zo, , –, , Figure 8.82 Problem 23, , 398, , +, , BJT Small-Signal Analysis
Page 410 :
§ 8.10 Complete Hybrid Equivalent Model, 4, * 24. Repeat parts (a) and (b) of Problem 22 with hre 2 10 and compare results., * 25. For the network of Fig. 8.83, determine:, (a) Zi., (b) Av., (c) Ai Io/Ii., (d) Zo., , 20 V, , 2.2 kΩ, 470 kΩ, , 5 µF, , Vo, , 5 µF, , Ii, , 1 kΩ, , +, , Io, , +, , Zo, , Vi, , Vs, , 1.2 kΩ, , –, Zi, , hfe = 140, hie = 0.86 kΩ, hre = 1.5 × 10− 4, hoe = 25 µS, , 10 µ F, , –, , Figure 8.83 Problem 25, , * 26. For, (a), (b), (c), (d), , the common-base amplifier of Fig. 8.84, determine:, Zi., Ai., Av., Zo., hib = 9.45 Ω, hfb = −0.997, hob = 0.5 µ A/V, hrb = 1 × 10− 4, , Ii, , 0.6 kΩ, 5 µF, , Io, , +, , +, , 5 µF, , +, 1.2 kΩ, Vs, , Zi, , 2.2 kΩ, , Vi, , –, , Zo, 4V, , –, , Vo, , 14 V, , –, , Figure 8.84 Problem 26, , § 8.12 Troubleshooting, * 27. Given the network of Fig. 8.85:, (a) Determine if the system is operating properly based on the voltage-divider bias levels and, expected waveforms for vo and vE., (b) Determine the reason for the dc levels obtained and why the waveform for vo was obtained., Problems, , 399
Page 411 :
VCC = 14 V, , υi (mV), , RC, R1, , υo (V), , 2.2 kΩ, , 150 kΩ, 10 µ F, , t, , 0, 10 µ F, , vo, VB = 6.22 V, , β = 70, , +, , C1, , –, , R2, , +, , υe, , VBE = 0.7 V, , Rs, , t, , 0, , C2, , 0, , t, , 39 kΩ, RE, , 1.5 kΩ, , 10 µ F, , Vs, , –, Figure 8.85 Problem 27, , § 8.13 PSpice Windows, 28. Using PSpice Windows, determine the gain for the network of Fig. 8.6. Use Probe to display, the input and output waveforms., 29. Using PSpice Windows, determine the gain for the network of Fig. 8.13. Use Probe to display, the input and output waveforms., 30. Using PSpice Windows, determine the gain for the network of Fig. 8.25. Use Probe to display, the input and output waveforms., *Please Note: Asterisks indicate more difficult problems., , 400, , Chapter 8, , BJT Small-Signal Analysis
Page 412 :
gm, , CHAPTER, , FET Small-Signal, Analysis, , 9, , 9.1 INTRODUCTION, Field-effect transistor amplifiers provide an excellent voltage gain with the added feature of a high input impedance. They are also considered low-power consumption, configurations with good frequency range and minimal size and weight. Both JFET, and depletion MOSFET devices can be used to design amplifiers having similar voltage gains. The depletion MOSFET circuit, however, has a much higher input impedance than a similar JFET configuration., While a BJT device controls a large output (collector) current by means of a relatively small input (base) current, the FET device controls an output (drain) current, by means of a small input (gate-voltage) voltage. In general, therefore, the BJT is a, current-controlled device and the FET is a voltage-controlled device. In both cases,, however, note that the output current is the controlled variable. Because of the high, input characteristic of FETs, the ac equivalent model is somewhat simpler than that, employed for BJTs. While the BJT had an amplification factor (beta), the FET has, a transconductance factor, gm., The FET can be used as a linear amplifier or as a digital device in logic circuits., In fact, the enhancement MOSFET is quite popular in digital circuitry, especially in, CMOS circuits that require very low power consumption. FET devices are also widely, used in high-frequency applications and in buffering (interfacing) applications. Table, 9.1, located at the end of the chapter, provides a summary of FET small-signal amplifier circuits and related formulas., While the common-source configuration is the most popular providing an inverted,, amplified signal, one also finds common-drain (source-follower) circuits providing, unity gain with no inversion and common-gate circuits providing gain with no inversion. As with BJT amplifiers, the important circuit features described in this chapter, include voltage gain, input impedance, and output impedance. Due to the very high, input impedance, the input current is generally assumed to be 0 A and the current, gain is an undefined quantity. While the voltage gain of an FET amplifier is generally less than that obtained using a BJT amplifier, the FET amplifier provides a much, higher input impedance than that of a BJT configuration. Output impedance values, are comparable for both BJT and FET circuits., FET ac amplifier networks can also be analyzed using computer software. Using, PSpice, one can perform a dc analysis to obtain the circuit bias conditions and an ac, analysis to determine the small-signal voltage gain. Using PSpice transistor models,, 401
Page 413 :
gm, one can analyze the circuit using specific transistor models. On the other hand, one, can develop a program using a language such as BASIC that can perform both the dc, and ac analyses and provide the results in a very special format., , 9.2 FET SMALL-SIGNAL MODEL, The ac analysis of an FET configuration requires that a small-signal ac model for the, FET be developed. A major component of the ac model will reflect the fact that an, ac voltage applied to the input gate-to-source terminals will control the level of current from drain to source., The gate-to-source voltage controls the drain-to-source (channel) current of an, FET., Recall from Chapter 6 that a dc gate-to-source voltage controlled the level, of dc drain current through a relationship known as Shockley’s equation: ID , IDSS(1 VGS/VP)2. The change in collector current that will result from a change, in gate-to-source voltage can be determined using the transconductance factor gm, in the following manner:, ID gm VGS, , (9.1), , The prefix trans- in the terminology applied to gm reveals that it establishes a relationship between an output and input quantity. The root word conductance was chosen because gm is determined by a voltage-to-current ratio similar to the ratio that defines the conductance of a resistor G 1/R I/V., Solving for gm in Eq. (9.1), we have:, ID, gm , VGS, , (9.2), , Graphical Determination of gm, If we now examine the transfer characteristics of Fig. 9.1, we find that gm is actually, the slope of the characteristics at the point of operation. That is,, y, ID, gm m , x, VGS, , (9.3), , Following the curvature of the transfer characteristics, it is reasonably clear that, the slope and, therefore, gm increase as we progress from VP to IDSS. Or, in other, words, as VGS approaches 0 V, the magnitude of gm increases., ID, IDSS, gm ≡, , ∆ID, (= Slope at Q-point), ∆VGS, , Q-Point, , ∆ID, , ∆VGS, VP, , 402, , Chapter 9, , FET Small-Signal Analysis, , 0, , VGS, , Figure 9.1 Definition of gm, using transfer characteristic.
Page 414 :
gm, Equation (9.2) reveals that gm can be determined at any Q-point on the transfer, characteristics by simply choosing a finite increment in VGS (or in ID) about the, Q-point and then finding the corresponding change in ID (or VGS, respectively). The, resulting changes in each quantity are then substituted in Eq. (9.2) to determine gm., , Determine the magnitude of gm for a JFET with IDSS 8 mA and VP 4 V at the, following dc bias points:, (a) VGS 0.5 V., (b) VGS 1.5 V., (c) VGS 2.5 V., , EXAMPLE 9.1, , Solution, The transfer characteristics are generated as Fig. 9.2 using the procedure defined in, Chapter 6. Each operating point is then identified and a tangent line is drawn at each, point to best reflect the slope of the transfer curve in this region. An appropriate increment is then chosen for VGS to reflect a variation to either side of each Q-point., Equation (9.2) is then applied to determine gm., 2.1 m A, ID, (a) gm , 3.5 mS, 0.6 V, VGS, 1.8 m A, ID, (b) gm 2.57 mS, 0.7 V, VGS, 1.5 m A, ID, (c) gm 1.5 mS, 1.0 V, VGS, Note the decrease in gm as VGS approaches VP., , ID (mA), 8, 7, gm at − 0.5 V, , (, , ID = 8 mA 1 −, , VGS, −4 V, , ), , 2, , 0.6 V, , 4, , 1.8 mA, , 3, 2, , gm at −2.5 V, , −3, , 2.1 mA, , 5, , gm at −1.5 V, , −4, VP, , 6, , 0.7 V, 1.5 mA, −2, , −1, , 1.0 V, , 1, 0, , VGS (V), , Figure 9.2 Calculating gm at, various bias points., , Mathematical Definition of gm, The graphical procedure just described is limited by the accuracy of the transfer plot, and the care with which the changes in each quantity can be determined. Naturally,, the larger the graph the better the accuracy, but this can then become a cumbersome, 9.2 FET Small-Signal Model, , 403
Page 415 :
gm, problem. An alternative approach to determining gm employs the approach used to, find the ac resistance of a diode in Chapter 1, where it was stated that:, The derivative of a function at a point is equal to the slope of the tangent line, drawn at that point., If we therefore take the derivative of ID with respect to VGS (differential calculus) using Shockley’s equation, an equation for gm can be derived as follows:, ID, gm , VGS, , , , , , dID, , dVGS, Q-pt., , , , V, d, IDSS 1 GS, VP, dVGS, , , , , , V, d, IDSS 1 GS, VP, dVGS, Q-pt., , , , 2, , , , , , , 2, , , , V, V, d, 2IDSS 1 GS 1 GS, VP dVGS, VP, , , , , , , , , , , V, V, d, 1 dVGS, 1, 2IDSS 1 GS (1) , 2IDSS 1 GS 0 , VP dVGS, VP, VP dVGS, VP, , , , 2I SS, V, gm D, 1 GS, VP, VP, , and, , , , , (9.4), , where VP denotes magnitude only to ensure a positive value for gm., It was mentioned earlier that the slope of the transfer curve is a maximum at, VGS 0 V. Plugging in VGS 0 V into Eq. (9.4) will result in the following equation, for the maximum value of gm for a JFET in which IDSS and VP have been specified:, , , , 2I SS, 0, 1 , gm D, VP, VP, , , , 2I SS, gm0 D, VP, , and, , (9.5), , where the added subscript 0 reminds us that it is the value of gm when VGS 0 V., Equation (9.4) then becomes, , , , V, gm gm0 1 GS, VP, , EXAMPLE 9.2, , , , (9.6), , For the JFET having the transfer characteristics of Example 9.1:, (a) Find the maximum value of gm., (b) Find the value of gm at each operating point of Example 9.1 using Eq. (9.6) and, compare with the graphical results., , Solution, 2I SS, 2(8 mA), (a) gm0 D, 4 mS, VP, 4V, (b) At VGS 0.5 V,, , (maximum possible value of gm), , V, 0.5 V, gm gm0 1 GS 4 mS 1 3.5 mS, VP, 4 V, , , , 404, , Chapter 9, , , , FET Small-Signal Analysis, , , , , , (versus 3.5 mS, graphically)
Page 416 :
gm, At VGS 1.5 V,, V, 1.5 V, gm gm0 1 GS 4 mS 1 2.5 mS, VP, 4 V, , , , , , , , , , (versus 2.57 mS, graphically), , At VGS 2.5 V,, V, 2.5 V, gm gm0 1 GS 4 mS 1 1.5 mS, VP, 4 V, , , , , , , , , , (versus 1.5 mS, graphically), , The results of Example 9.2 are certainly sufficiently close to validate Eq. (9.4), through (9.6) for future use when gm is required., On specification sheets, gm is provided as yfs where y indicates it is part of an admittance equivalent circuit. The f signifies forward transfer parameter, and the s reveals that it is connected to the source terminal., In equation form,, gm yfs, , (9.7), , For the JFET of Fig. 5.18, yfs ranges from 1000 to 5000 S or 1 to 5 mS., , Plotting gm vs. VGS, , , , , , V, Since the factor 1 GS of Eq. (9.6) is less than 1 for any value of VGS other than, VP, V, 0 V, the magnitude of gm will decrease as VGS approaches VP and the ratio GS, VP, increases in magnitude. At VGS VP, gm gm0(1 1) 0. Equation (9.6) defines a, straight line with a minimum value of 0 and a maximum value of gm as shown by the, plot of Fig. 9.3., gm (S), gm0, , gm0, 2, , VP, , VP, 2, , 0, , VGS (V), , Figure 9.3 Plot of gm vs. VGS., , Figure 9.3 also reveals that when VGS is one-half the pinch-off value, gm will be, one-half the maximum value., , EXAMPLE 9.3, , Plot gm vs. VGS for the JFET of examples 9.1 and 9.2., , Solution, Note Fig. 9.4., 9.2 FET Small-Signal Model, , 405
Page 417 :
gm, gm (S), 4 mS, , 2 mS, , −4 V, , −2 V, , 0, , VGS (V), , Figure 9.4 Plot of gm vs. VGS for, a JFET with IDSS 8 mA and, VP 4 V., , Impact of ID on gm, A mathematical relationship between gm and the dc bias current ID can be derived by, noting that Shockley’s equation can be written in the following form:, V, 1 GS , VP, , I, D, IDSS, , (9.8), , Substituting Eq. (9.8) into Eq. (9.6) will result in, , , , , , V, gm gm0 1 GS gm0, VP, , I, D, IDSS, , Using Eq. (9.9) to determine gm for a few specific values of ID, the results are, (a) If ID IDSS,, gm gm0, , I SS, D, gm0, IDSS, , (b) If ID IDSS/2,, gm gm0, , IDSS/2, , 0.707gm0, IDSS, , (c) If ID IDSS/4,, gm gm0, , EXAMPLE 9.4, , Plot gm vs. ID for the JFET of Examples 9.1 through 9.3., , Solution, See Fig. 9.5., , 406, , IDSS/4, g, , m0, 0.5gm0, IDSS, 2, , Chapter 9, , FET Small-Signal Analysis, , (9.9)
Page 418 :
gm, gm (S), , 4, , 3, , 2, , 4 mS, , 2.83 mS, , 2 mS, , 1, , 0, , 1, , 2, IDSS, 4, , 3, , 4, IDSS, , 5, , 6, , 7, , 8, IDSS, , 9, , 10, , ID (mA), , 2, , Figure 9.5 Plot of gm vs. ID for a JFET with IDSS 8 mA and VGS 4 V., , The plots of Examples 9.3 and 9.4 clearly reveal that the highest values of gm are, obtained when VGS approaches 0 V and ID its maximum value of IDSS., , FET Input Impedance Zi, The input impedance of all commercially available FETs is sufficiently large to assume that the input terminals approximate an open circuit. In equation form,, Zi (FET) , , (9.10), , For a JFET a practical value of 109 (1000 M) is typical, while a value of 1012, to 1015 is typical for MOSFETs., , FET Output Impedance Zo, The output impedance of FETs is similar in magnitude to that of conventional BJTs., On FET specification sheets, the output impedance will typically appear as yos with, the units of S. The parameter yos is a component of an admittance equivalent circuit, with the subscript o signifying an output network parameter and s the terminal, (source) to which it is attached in the model. For the JFET of Fig. 5.18, yos has a, range of 10 to 50 S or 20 k (R 1/G 1/50 S) to 100 k (R 1/G , 1/10 S)., In equation form,, 1, Zo (FET) rd , yos, , (9.11), , The output impedance is defined on the characteristics of Fig. 9.6 as the slope of, the horizontal characteristic curve at the point of operation. The more horizontal the, curve, the greater the output impedance. If perfectly horizontal, the ideal situation is, on hand with the output impedance being infinite (an open circuit)—an often applied, approximation., In equation form,, VDS, rd , ID, , , , (9.12), , VGSconstant, , 9.2 FET Small-Signal Model, , 407
Page 419 :
gm, ID (mA), , VGS = 0 V, , rd =, , ∆VDS, ∆ID, , VGS = constant at −1 V, VGS, , Q-point, , −1 V, ∆ ID, , ∆VDS, −2 V, , 0, , VDS (V), , Figure 9.6 Definition of rd using FET drain characteristics., , Note the requirement when applying Eq. (9.12) that the voltage VGS remain constant, when rd is determined. This is accomplished by drawing a straight line approximating the VGS line at the point of operation. A VDS or ID is then chosen and the other, quantity measured off for use in the equation., , EXAMPLE 9.5, , Determine the output impedance for the FET of Fig. 9.7 for VGS 0 V and VGS , 2 V at VDS 8 V., ID (mA), VGS = 0 V, , 8, 7, , ∆VDS = 5 V, , 6, , ∆ ID = 0.2 mA, VGS = −1 V, , 5, 4, 3, ∆ VDS = 8 V, , 2, , VGS = −2 V, ∆ ID = 0.1 mA, VGS = −3 V, VGS = −4 V, , 1, 0, , 1, , 2, , 3, , 4, , 5, , 6, , 7, , 8, , 9, , 10 11 12 13 14, , VDS (V), , Figure 9.7 Drain characteristics used to calculate rd in Example 9.5., , Solution, For VGS 0 V, a tangent line is drawn and VDS is chosen as 5 V, resulting in a ID, of 0.2 mA. Substituting into Eq. (9.12),, VDS, rd , ID, , , , 5V, 25 k, 0.2 mA, VGS0 V, , For VGS 2 V, a tangent line is drawn and VDS is chosen as 8 V, resulting in a, ID of 0.1 mA. Substituting into Eq. (9.12),, 408, , Chapter 9, , FET Small-Signal Analysis
Page 420 :
gm, VDS, rd , ID, , , , 8V, 80 k, 0.1, mA, VGS2 V, , revealing that rd does change from one operating region to another, with lower values typically occurring at lower levels of VGS (closer to 0 V)., , FET AC Equivalent Circuit, Now that the important parameters of an ac equivalent circuit have been introduced, and discussed, a model for the FET transistor in the ac domain can be constructed., The control of Id by Vgs is included as a current source gmVgs connected from drain, to source as shown in Fig. 9.8. The current source has its arrow pointing from drain, to source to establish a 180° phase shift between output and input voltages as will, occur in actual operation., G, , D, , +, gmVgs, , Vgs, , rd, , −, , S, , S, , Figure 9.8 FET ac equivalent circuit., , The input impedance is represented by the open circuit at the input terminals and, the output impedance by the resistor rd from drain to source. Note that the gate to, source voltage is now represented by Vgs (lower-case subscripts) to distinguish it from, dc levels. In addition, take note of the fact that the source is common to both input, and output circuits while the gate and drain terminals are only in “touch” through the, controlled current source gmVgs., In situations where rd is ignored (assumed sufficiently large to other elements of, the network to be approximated by an open circuit), the equivalent circuit is simply, a current source whose magnitude is controlled by the signal Vgs and parameter gm —, clearly a voltage-controlled device., Given yfs 3.8 mS and yos 20 S, sketch the FET ac equivalent model., , EXAMPLE 9.6, , Solution, gm yfs 3.8 mS, , and, , 1, 1, rd 50 k, yos, 20 S, , resulting in the ac equivalent model of Fig. 9.9., G, , D, , +, 3.8 × 10−3 Vgs, , Vgs, , S, , 50 kΩ, , −, , S, , Figure 9.9 FET ac equivalent model for Example 9.6., , 9.2 FET Small-Signal Model, , 409
Page 421 :
gm, , 9.3 JFET FIXED-BIAS CONFIGURATION, Now that the FET equivalent circuit has been defined, a number of fundamental FET, small-signal configurations will be investigated. The approach will parallel the ac, analysis of BJT amplifiers with a determination of the important parameters of Zi, Zo,, and Av for each configuration., The fixed-bias configuration of Fig. 9.10 includes the coupling capacitors C1 and, C2 that isolate the dc biasing arrangement from the applied signal and load; they act, as short-circuit equivalents for the ac analysis., +VDD, RD, , C2, , D, C1, , Vo, , G, , Vi, , RG, , S, , Zo, , –, , Zi, , VGG, , +, , Figure 9.10 JFET fixed-bias configuration., , Once the level of gm and rd are determined from the dc biasing arrangement, specification sheet, or characteristics, the ac equivalent model can be substituted between, the appropriate terminals as shown in Fig. 9.11. Note that both capacitors have the, short-circuit equivalent because the reactance XC 1/(2 fC) is sufficiently small compared to other impedance levels of the network, and the dc batteries VGG and VDD are, set to zero volts by a short-circuit equivalent., XC ≈ 0 Ω, , XC ≈ 0 Ω, , 1, , 2, , G, , Vi, , D, , RG, , gmVgs, , Zi, Battery VGG, replaced by, short, , rd, , Vo, RD, Zo, Battery VDD, replaced by, short, , S, , Figure 9.11 Substituting the JFET ac equivalent circuit unit into the network of Fig. 9.10., , The network of Fig. 9.11 is then carefully redrawn as shown in Fig. 9.12. Note, the defined polarity of Vgs, which defines the direction of gmVgs. If Vgs is negative,, the direction of the current source reverses. The applied signal is represented by Vi, and the output signal across RD by Vo., Zi: Figure 9.12 clearly reveals that, Zi RG, because of the open-circuit equivalence at the input terminals of the JFET., 410, , Chapter 9, , FET Small-Signal Analysis, , (9.13)
Page 422 :
gm, D, , G, , +, Vi, , +, Zi, , RG, , +, gmVgs, , Vgs, , –, , –, , rd, , RD, , Zo, , Vo, , –, , S, , Figure 9.12 Redrawn network of Fig. 9.11., , Zo: Setting Vi 0 V as required by the definition of Zo will establish Vgs as 0, V also. The result is gmVgs 0 mA, and the current source can be replaced by an, open-circuit equivalent as shown in Fig. 9.13. The output impedance is, Zo RD rd, , (9.14), , If the resistance rd is sufficiently large (at least 101) compared to RD, the approximation rd RD RD can often be applied and, Zo RD, , (9.15), rd 10RD, , D, gmVgs = 0 mA, , rd, , RD, , Zo, S, , Figure 9.13 Determining Zo., , Av: Solving for Vo in Fig. 9.12, we find, Vo gmVgs(rd RD), Vgs Vi, , but, , Vo gmVi(rd RD), , and, so that, , Vo, gm(rd RD), Av , Vi, If rd, , (9.16), , 10RD:, Vo, gmRD, Av , Vi, , (9.17), rd 10RD, , Phase Relationship: The negative sign in the resulting equation for Av clearly reveals a phase shift of 180° between input and output voltages., , 9.3 JFET Fixed-Bias Configuration, , 411
Page 423 :
gm, EXAMPLE 9.7, , The fixed-bias configuration of Example 6.1 had an operating point defined by VGSQ, 2 V and IDQ 5.625 mA, with IDSS 10 mA and VP 8 V. The network is, redrawn as Fig. 9.14 with an applied signal Vi. The value of yos is provided as 40 S., (a) Determine gm., (b) Find rd., (c) Determine Zi., (d) Calculate Zo., (e) Determine the voltage gain Av., (f) Determine Av ignoring the effects of rd., , 20 V, 2 kΩ, D, , +, , C1, , IDSS = 10 mA, VP = −8 V, , G, , +, 1 MΩ, Vi, , C2, , S, Zo, , Zi, , Vo, , 2V, , –, , –, , Figure 9.14 JFET configuration for Example 9.7., , Solution, 2I SS, 2(10 mA), (a) gm0 D, 2.5 mS, VP, 8V, VGSQ, (2 V), gm gm0 1 , 2.5 mS 1 1.88 mS, (8 V), VP, , , , , , , , , , 1, 1, (b) rd 25 k, yos, 40 S, (c) Zi RG 1 M, (d) Zo RD rd 2 k 25 k 1.85 k, (e) Av gm(RD rd) (1.88 mS)(1.85 k), 3.48, (f) Av gmRD (1.88 mS)(2 k) 3.76, As demonstrated in part (f), a ratio of 25 k2 k 12.51 between rd and RD, resulted in a difference of 8% in solution., , 9.4 JFET SELF-BIAS CONFIGURATION, Bypassed RS, The fixed-bias configuration has the distinct disadvantage of requiring two dc voltage sources. The self-bias configuration of Fig. 9.15 requires only one dc supply to, establish the desired operating point., 412, , Chapter 9, , FET Small-Signal Analysis
Page 424 :
gm, RD, C2, , D, C1, , Vo, , G, , Vi, , S, Zo, , RG, , Zi, , CS, , RS, , Figure 9.15 Self-bias JFET configuration., , The capacitor CS across the source resistance assumes its short-circuit equivalence, for dc, allowing RS to define the operating point. Under ac conditions, the capacitor, assumes the short-circuit state and “short circuits” the effects of RS. If left in the ac,, gain will be reduced as will be shown in the paragraphs to follow., The JFET equivalent circuit is established in Fig. 9.16 and carefully redrawn in, Fig. 9.17., XC ≈ 0 Ω, , XC ≈ 0 Ω, , 1, , 2, , G, , Vi, , D, , gmVgs, , Zi, , Vo, , rd, RD, , RG, S, , RS bypassed, by X C, , Zo, , VDD, , S, , Figure 9.16 Network of Fig. 9.15 following the substitution of the JFET ac equivalent circuit., , D, , G, , +, Vi, , +, Zi, , –, , RG, , +, gmVgs, , Vgs, , –, , rd, , RD, , Zo, , Vo, , –, , S, , Figure 9.17 Redrawn network of Fig. 9.16., , Since the resulting configuration is the same as appearing in Fig. 9.12, the resulting equations Zi, Zo, and Av will be the same., Zi:, Zi RG, , (9.18), , 9.4 JFET Self-Bias Configuration, , 413
Page 425 :
gm, Zo:, Zo rd RD, If rd, , (9.19), , 10RD,, Zo RD, , (9.20), , rd 10RD, , Av :, , If rd, , Av gm(rd RD), , (9.21), , Av gmRD, , (9.22), , 10RD,, rd 10RD, , Phase relationship: The negative sign in the solutions for Av again indicates a, phase shift of 180° between Vi and Vo., , Unbypassed RS, If CS is removed from Fig 9.15, the resistor RS will be part of the ac equivalent circuit as shown in Fig. 9.18. In this case, there is no obvious way to reduce the network to lower its level of complexity. In determining the levels of Zi, Zo, and Av, one, must simply be very careful with notation and defined polarities and direction. Initially, the resistance rd will be left out of the analysis to form a basis for comparison., , D, , G, , +, , +, gmVgs, , Zi, Vi, , +, , ID, , Vgs, RG, , –, , Zo, , S, , Vo, , RD, , RS, Io, , –, , –, , Figure 9.18 Self-bias JFET configuration including the effects of RS with rd, , ., , Zi: Due to the open-circuit condition between the gate and output network, the, input remains the following:, Zi RG, , (9.23), , Zo: The output impedance is defined by, , , , Vo, Zo , Io, , Vi 0, , Setting Vi 0 V in Fig. 9.18 will result in the gate terminal being at ground potential (0 V). The voltage across RG is then 0 V, and RG has been effectively “shorted, out” of the picture., 414, , Chapter 9, , FET Small-Signal Analysis
Page 426 :
gm, Applying Kirchhoff’s current law will result in:, ID gmVgS, , Io, , Vgs (Io, , with, so that, , ID gm (Io, , Io, , or, Io ID, , ID)RS gmIoRS gmIDRS, , gmRS] ID[1, , Io[1, , and, , ID)RS, gmRS], , (the controlled current source gmVgs 0 A, for the applied conditions), , Since, , Vo IDRD, , then, , Vo (Io)RD IoRD, , and, , Vo, Zo , RD, Io, , (9.24), rd ∝, , If rd is included in the network, the equivalent will appear as shown in Fig. 9.19., a, , G, +, , +, , Vi, , +, , RG, , Zo, , −, , Vgs, −, , +, , Io, , ID, , I′, , rd, , gmVgs, , Zi, , D, , RD, , S, , Vo, , RS, −, , −, Io + ID, , Io, , Figure 9.19 Including the, effects of rd in the self-bias JFET, configuration., , , , Vo, Zo , Io, , Since, , IDRD, , , Io, Vi 0 V, , we should try to find an expression for Io in terms of ID., Applying Kirchhoff’s current law:, Io gmVgs, Vrd Vo, , but, , , , Io gm, , , , 1, IDRD, Vgs , ID using Vo IDRD, rd, rd, Vgs (ID, , Now,, so that, with the result that, , or, , Vgs, , Vo Vgs, ID, rd, , Io gmVgs, , and, or, , Ird ID, , , , Io gm, , , , 1, (ID, rd, , , I 1, , Io) RS, IDRD, Io) RS , ID, rd, , , , , , RS, ID 1, , rd, RS, RD, gmRS , , D, rd, rd, Io , RS, 1 gmRS , rd, Io 1, , gmRs, , gmRS, , RS, , rd, , RD, , rd, , , , , , 9.4 JFET Self-Bias Configuration, , 415
Page 427 :
gm, , IDRD, Vo, Zo , , R, RD, Io, ID 1 gmRs s , rd, rd, RS, 1 gmRS , rd, , and, , , , , , 1 g R r, , , R, R R, 1, g, R, , , , , , r, r , RS, , m S, , and finally,, , Zo, , d, , S, , D, , d, , d, , (9.25a), , D, , m S, , , , 10 RD, 1, , For rd, 1, , gmRS, , , , RS, , rd, , gmRS, , RS, and, , rd, , RD, and 1, , rd, , Zo RD, , gmRS, , RS, , rd, , RD, , rd, , (9.25b), rd, , 10RD, , Av: For the network of Fig. 9.19, an application of Kirchhoff’s voltage law on, the input circuit will result in, Vi Vgs VRS 0, Vgs Vi ID RS, The voltage across rd using Kirchhoff’s voltage law is, Vo VRS, Vo VRS, I , rd, , and, , so that an application of Kirchhoff’s current law will result in, Vo VRS, ID gmVgs , rd, Substituting for Vgs from above and substituting for Vo and VRS we have, ID gm[Vi IDRS], so that, , , , ID 1, , gmRS, , (IDRD) (IDRS), , , rd, , , , RD RS, gmVi, , rd, , gmVi, ID , RD RS, 1 gmRS , , rd, , or, , The output voltage is then, gmRDVi, Vo IDRD , RD RS, 1 gmRS , , rd, and, , 416, , Chapter 9, , gmRD, Vo, Av , , RD RS, Vi, 1 gmRS , , rd, , FET Small-Signal Analysis, , (9.26)
Page 428 :
gm, Again, if rd, , 10(RD, , RS),, gmRD, Vo, Av , , , Vi, 1 gmRS, , (9.27), rd 10(RD, , RS), , Phase Relationship: The negative sign in Eq. (9.26) again reveals that a 180°, phase shift will exist between Vi and Vo., The self-bias configuration of Example 6.2 has an operating point defined by VGSQ , 2.6 V and IDQ 2.6 mA, with IDSS 8 mA and VP 6 V. The network is redrawn as Fig. 9.20 with an applied signal Vi. The value of yos is given as 20 S., (a) Determine gm., (b) Find rd., (c) Find Zi., (d) Calculate Zo with and without the effects of rd. Compare the results., (e) Calculate Av with and without the effects of rd. Compare the results., , EXAMPLE 9.8, , 20 V, 3.3 kΩ, C2, Vo, C1, , IDSS = 10 mA, VP = −6 V, , Vi, , Zo, , Zi, , 1 MΩ, , 1 kΩ, , Figure 9.20 Network for Example 9.8., , Solution, 2I SS, 2(8 mA), (a) gm0 D, 2.67 mS, VP, 6V, VGSQ, (2.6 V), gm gm0 1 2.67 mS 1 1.51 mS, (6 V), VP, 1, 1, (b) rd 50 k, yos, 20 S, (c) Zi RG 1 M, (d) With rd:, , , , , , , , rd 50 k, , , , 10 RD 33 k, , Therefore,, Zo RD 3.3 k, If rd , , , Zo RD 3.3 k, , (e) With rd:, gmRD, (1.51 mS)(3.3 k), , Av , RD RS, 3.3 k 1 k, 1 gmRS , , 1 (1.51 mS)(1 k) , 50 k, rd, 1.92, 9.4 JFET Self-Bias Configuration, , 417
Page 429 :
gm, Without rd:, gm RD, (1.51 mS)(3.3 k), Av 1.98, 1 gmRS, 1 (1.51 mS)(1 k), As above, the effect of rd was minimal because the condition rd 10(RD RS), was satisfied., Note also that the typical gain of a JFET amplifier is less than that generally encountered for BJTs of similar configurations. Keep in mind, however, that Zi is magnitudes greater than the typical Zi of a BJT, which will have a very positive effect on, the overall gain of a system., , 9.5 JFET VOLTAGE-DIVIDER, CONFIGURATION, The popular voltage-divider configuration for BJTs can also be applied to JFETs as, demonstrated in Fig. 9.21., +VDD, , RD, C2, , R1, C1, , Vo, , D, G, Zo, , S, Vi, , Zi, , R2, , RS, , CS, , Figure 9.21 JFET voltage-divider configuration., , Substituting the ac equivalent model for the JFET will result in the configuration, of Fig. 9.22. Replacing the dc supply VDD by a short-circuit equivalent has grounded, one end of R1 and RD. Since each network has a common ground, R1 can be brought, down in parallel with R2 as shown in Fig. 9.23. RD can also be brought down to ground, but in the output circuit across rd. The resulting ac equivalent network now has the, basic format of some of the networks already analyzed., , RD, , R1, , Vi, , Zi, , Vo, , +, R2, , gmVgs, , Vgs, , RD, , Zi, Zo, , Zo, R1, , R2, , gmVgs, , Vgs, , –, , Figure 9.22 Network of Fig. 9.21 under ac conditions., , Chapter 9, , Vo, , +, , –, , 418, , D, , G, , Vi, , Figure 9.23 Redrawn network of Fig. 9.22., , FET Small-Signal Analysis, , rd, , RD
Page 430 :
gm, Zi: R1 and R2 are in parallel with the open-circuit equivalence of the JFET resulting in, Zi R1 R2, , (9.28), , Zo: Setting Vi 0 V will set Vgs and gmVgs to zero and, Zo rd RD, For rd, , (9.29), , 10RD,, Zo RD, , (9.30), rd 10RD, , Av :, Vgs Vi, Vo gmVgs(rd RD), , and, , gmVgs(rd RD), Vo, , Av , Vgs, Vi, , so that, , Vo, Av , gm(rd RD), Vi, , and, If rd, , (9.31), , 10RD,, Vo, gmRD, Av , Vi, , (9.32), rd 10RD, , Note that the equations for Zo and Av are the same as obtained for the fixed-bias, and self-bias (with bypassed RS) configurations. The only difference is the equation, for Zi, which is now sensitive to the parallel combination of R1 and R2., , 9.6 JFET SOURCE-FOLLOWER, (COMMON-DRAIN) CONFIGURATION, The JFET equivalent of the BJT emitter-follower configuration is the source-follower, configuration of Fig. 9.24. Note that the output is taken off the source terminal and,, when the dc supply is replaced by its short-circuit equivalent, the drain is grounded, (hence, the terminology common-drain)., , VDD, D, C1, , G, , Vi, , S, Zi, , C2, Vo, , RG, RS, , Zo, , Figure 9.24 JFET source-follower configuration., , 9.6 JFET Source-Follower (Common-Drain) Configuration, , 419
Page 431 :
gm, Substituting the JFET equivalent circuit will result in the configuration of Fig., 9.25. The controlled source and internal output impedance of the JFET are tied to, ground at one end and RS on the other, with Vo across RS. Since gmVgs, rd, and RS are, connected to the same terminal and ground, they can all be placed in parallel as shown, in Fig. 9.26. The current source reversed direction but Vgs is still defined between the, gate and source terminals., G, , Vi, , D, , +, gmVgs, , Vgs, , Zi, RG, , rd, , –, S, , Vo, , Io, , S, , G, , Vi, , +, , –, , Vgs, , +, , Zi, RS, , gmVgs, , RG, , Zo, , Zo, rd, , RS, , Vo, , D, , –, Figure 9.25 Network of Fig. 9.24 following the, substitution of the JFET ac equivalent model., , Figure 9.26 Network of Fig. 9.25 redrawn., , Zi: Figure 9.26 clearly reveals that Zi is defined by, Zi RG, , (9.33), , Zo: Setting Vi 0 V will result in the gate terminal being connected directly to, ground as shown in Fig. 9.27. The fact that Vgs and Vo are across the same parallel, network results in Vo Vgs., Io, , S, , –, , +, gmVgs, , Vgs, , Zo, rd, , Vo, , RS, , –, , +, , Figure 9.27 Determining Zo for, the network of Fig. 9.24., , Applying Kirchhoff’s current law at node s,, gmVgs Ird, , Io, , Vo, , rd, The result is, , , 1, V , r, 1, V , r, , 1, Io Vo , rd, o, , d, , o, , d, , 420, , Chapter 9, , FET Small-Signal Analysis, , IRS, Vo, , RS, , , 1, g [V ], R, 1, g , R, 1, gmVgs, RS, m, , S, , m, , S, , o
Page 432 :
gm, Vo, 1, 1, Vo, Zo , , , 1, 1, 1, 1, 1, 1, 1, Io, Vo gm, gm, , rd, RS, rd, RS, rd, RS, 1/gm, which has the same format as the total resistance of three parallel resistors. Therefore,, and, , , , , , Zo rd RS 1/gm, For rd, , (9.34), , 10RS,, Zo RS 1/gm, , (9.35), , rd 10RS, , Av: The output voltage Vo is determined by, Vo gmVgs(rd RS), and applying Kirchhoff’s voltage law around the perimeter of the network of Fig. 9.26, will result in, Vi Vgs, , Vo, , Vgs Vi Vo, , and, , Vo gm(Vi Vo)(rd RS), , so that, or, , Vo gmVi(rd RS) gmVo(rd RS), , and, , Vo[1, , gm(rd RS)] gmVi(rd RS), , gm(rd RS), Vo, Av , , , Vi, 1 gm(rd RS), , so that, In the absence of rd or if rd, , (9.36), , 10RS,, , Vo, gmRS, Av , , , Vi, 1 gmRS, , (9.37), rd, , 10RS, , Since the bottom of Eq. (9.36) is larger than the numerator by a factor of one, the, gain can never be equal to or greater than one (as encountered for the emitter-follower BJT network)., Phase Relationship: Since Av of Eq. (9.36) is a positive quantity, Vo and Vi are, in phase for the JFET source-follower configuration., A dc analysis of the source-follower network of Fig. 9.28 will result in VGSQ 2.86 V, EXAMPLE 9.9, and IDQ 4.56 mA., (a) Determining gm., (b) Find rd., (c) Determine Zi., +9 V, (d) Calculate Zo with and without rd. Compare results., IDSS = 16 mA, (e) Determine Av with and without rd. Compare results., VP = − 4 V, yos = 25 µS, , +, , 0.05 µ F, , Vi, , Zi, , 1 MΩ, , +, , 0.05 µ F, 2.2 kΩ, , –, , Zo, , Vo, , –, , Figure 9.28 Network to be analyzed in Example 9.9., , 9.6 JFET Source-Follower (Common-Drain) Configuration, , 421
Page 433 :
gm, Solution, 2I SS, 2(16 mA), (a) gm0 D, 8 mS, VP, 4V, VGSQ, (2.86 V), gm gm0 1 8 mS 1 2.28 mS, VP, (4 V), 1, 1, (b) rd 40 k, yos, 25 S, (c) Zi RG 1 M, (d) With rd:, , , , , , , , , , Zo rd RS 1/gm 40 k 2.2 k 1/2.28 mS, 40 k 2.2 k 438.6 , 362.52 , revealing that Zo is often relatively small and determined primarily by 1/gm. Without rd:, Zo RS 1/gm 2.2 k 438.6 365.69 , revealing that rd typically has little impact on Zo., (e) With rd:, (2.28 mS)(40 k 2.2 k), gm(rd RS), , Av , 1 (2.28 mS)(40 k 2.2 k), 1 gm(rd RS), (2.28 mS)(2.09 k), 4.77, 0.83, 1 (2.28 mS)(2.09 k), 1 4.77, which is less than 1 as predicted above., Without rd:, (2.28 mS)(2.2 k), gmRS, , Av , 1 (2.28 mS)(2.2 k), 1 gmRS, 5.02, 0.83, 1 5.02, revealing that rd usually has little impact on the gain of the configuration., , 9.7 JFET COMMON-GATE, CONFIGURATION, The last JFET configuration to be analyzed in detail is the common-gate configuration of Fig. 9.29, which parallels the common-base configuration employed with BJT, transistors., Substituting the JFET equivalent circuit will result in Fig. 9.30. Note the continuing requirement that the controlled source gmVgs be connected from drain to source, with rd in parallel. The isolation between input and output circuits has obviously been, lost since the gate terminal is now connected to the common ground of the network., In addition, the resistor connected between input terminals is no longer RG but the, resistor RS connected from source to ground. Note also the location of the controlling voltage Vgs and the fact that it appears directly across the resistor RS., , 422, , Chapter 9, , FET Small-Signal Analysis
Page 434 :
gm, –, C1, C1, , S, , C2, , D, , +, , Vi, , RD, , G, , RS, , Vi, , Zo, , C2, , b, , D, , S, , Zi, , +, gmVgs, , RS, , Vgs, , Z'o, , RD, , Zo, , Vo, , Vo, , Z'i, VDD, , –, , +, , –, , +, , +, Zi, , a, , rd, , –, , –, , +G, , –, , Figure 9.30 Network of Fig. 9.29 following substitution of, JFET ac equivalent model., , Figure 9.29 JFET common-gate configuration., , Zi: The resistor RS is directly across the terminals defining Zi. Let us therefore, find the impedance Zi of Fig. 9.29, which will simply be in parallel with RS when Zi, is defined., The network of interest is redrawn as Fig. 9.31. The voltage V Vgs. Applying Kirchhoff’s voltage law around the output perimeter of the network will result in, V Vrd VRD 0, Vrd V VRD V IRD, , and, , I', , I', , –, , +, , a, , +, , Ird, , Z'i, , rd V r d, , gmVgs, Vi, , Vgs, , –, +, , –, , +, , RD VRD, , I', , –, , Figure 9.31 Determining Zi for, the network of Fig. 9.29., , Applying Kirchhoff’s current law at node a results in, I, and, , gmVgs Ird, , (V IRD), I Ird gmVgs , gmVgs, rd, , or, , V, IRD, I , gm[V], rd, rd, , so that, , I 1, , , , , , , , RD, 1, , V , rd, rd, , gm, , 1 r, V , Z , 1, I, g r, , , , RD, d, , and, , i, , (9.38), , m, , d, , or, , V, rd RD, , Zi , I, 1 gmrd, , 9.7 JFET Common-Gate Configuration, , 423
Page 435 :
gm, Zi RS Zi, , and, , , , rd RD, Zi RS , , 1 gmrd, , results in, , , , (9.39), , If rd 10RD, Eq. (9.38) permits the following approximation since RD /rd 1 and, 1/rd gm:, 1 , , r , 1, Z , 1 , g, g, , , r, RD, d, , i, , m, , m, , d, , Zi RS 1/gm, , and, , (9.40), rd 10RD, , Zo: Substituting Vi 0 V in Fig. 9.30 will “short-out” the effects of RS and set, Vgs to 0 V. The result is gmVgs 0, and rd will be in parallel with RD. Therefore,, Zo RD rd, For rd, , (9.41), , 10RD,, Zo RD, , (9.42), rd 10RD, , Av: Figure 9.30 reveals that, Vi Vgs, Vo IDRD, , and, The voltage across rd is, , Vrd Vo Vi, Vo Vi, Ird , , rd, , and, , Applying Kirchhoff’s current law at node b in Fig. 9.30 results in, ID, , Ird, , gmVgs 0, , ID Ird gmVgs, , and, , Vo Vi, , gm[Vi], rd, , , , , , Vi Vo, ID , , rd, so that, , gmVi, , Vi Vo, Vo IDRD , , rd, , , , V RD, V RD, i , o , rd, rd, and, , 424, , Chapter 9, , , , Vo 1, , , , , , RD, RD, , Vi , rd, rd, , FET Small-Signal Analysis, , , , gmVi RD, gm, gmRD, ,
Page 436 :
gm, g R, , , r , V, A , R, V, 1 r, RD, , m D, , d, , o, , with, , v, , (9.43), , D, , i, , d, , For rd 10RD, the factor RD /rd of Eq. (9.43) can be dropped as a good approximation and, Av gmRD, , (9.44), , rd 10RD, , Phase Relationship: The fact that Av is a positive number will result in an inphase relationship between Vo and Vi for the common-gate configuration., Although the network of Fig. 9.32 may not initially appear to be of the common-gate, variety, a close examination will reveal that it has all the characteristics of Fig. 9.29., If VGSQ 2.2 V and IDQ 2.03 mA:, (a) Determine gm., (b) Find rd., (c) Calculate Zi with and without rd. Compare results., (d) Find Zo with and without rd. Compare results., (e) Determine Vo with and without rd. Compare results., , EXAMPLE 9.10, , +12 V, , 3.6 kΩ, 10 µ F, Vo, IDSS = 10 mA, VP = − 4 V, yos = 50 µS, 10 µ F, , +, Vi = 40 mV, , 1.1 kΩ, , –, Figure 9.32 Network for Example 9.10., , Solution, 2I SS, 2(10 mA), (a) gm0 D, 5 mS, VP, 4V, VGSQ, (2.2 V), 5 mS 1 2.25 mS, gm gm0 1 , VP, (4 V), , , , , , , , , , 1, 1, (b) rd 20 k, yos, 50 S, (c) With rd:, , , , , , , , 20 k 3.6 k, rd RD, Zi RS , 1.1 k , 1 (2.25 ms)(20 k), 1 gmrd, 1.1 k 0.51 k 0.35 k, , , , 9.7 JFET Common-Gate Configuration, , 425
Page 437 :
gm, Without rd:, Zi RS 1/gm 1.1 k 1/2.25 ms 1.1 k 0.44 k, 0.31 k, Even though the condition,, rd, , 10RD , , 20 k, , 10(3.6 k) , , 20 k, , 36 k, , is not satisfied, both equations result in essentially the same level of impedance., In this case, 1/gm was the predominant factor., (d) With rd:, Zo RD rd 3.6 k 20 k 3.05 k, Without rd:, Zo RD 3.6 k, Again the condition rd 10RD is not satisfied, but both results are reasonably, close. RD is certainly the predominant factor in this example., (e) With rd:, RD, 3.6 k, gmRD , (2.25 mS)(3.6 k) , rd, 20 k , , , Av , RD, 3.6 k, 1 , 1 , rd, 20 k , , , , , , , , , , , , , , , , 8.1 0.18, 7.02, 1 0.18, Vo, Av , ➤ Vo AvVi (7.02)(40 mV) 280.8 mV, Vi, , and, Without rd:, , Av gmRD (2.25 mS)(3.6 k) 8.1, with, , Vo AvVi (8.1)(40 mV) 324 mV, , In this case, the difference is a little more noticeable but not dramatically so., , Example 9.10 demonstrates that even though the condition rd 10RD was not satisfied, the results for the parameters given were not significantly different using the, exact and approximate equations. In fact, in most cases, the approximate equations, can be used to find a reasonable idea of particular levels with a reduced amount of, effort., , 9.8 DEPLETION-TYPE MOSFETs, The fact that Shockley’s equation is also applicable to depletion-type MOSFETs results in the same equation for gm. In fact, the ac equivalent model for D-MOSFETs, is exactly the same as that employed for JFETs as shown in Fig. 9.33., The only difference offered by D-MOSFETs is that VGSQ can be positive for, n-channel devices and negative for p-channel units. The result is that gm can be greater, than gm0 as demonstrated by the example to follow. The range of rd is very similar to, that encountered for JFETs., , 426, , Chapter 9, , FET Small-Signal Analysis
Page 439 :
gm, (d) Eq. (9.28): Zi R1 R2 10 M 110 M 9.17 M, (e) Eq. (9.29): Zo rd RD 100 k 1.8 k 1.77 k RD 1.8 k, (f) rd 10RD → 100 k 18 k, Eq. (9.32): Av gmRD (4.47 mS)(1.8 k) 8.05, , 9.9 ENHANCEMENT-TYPE MOSFETs, The enhancement-type MOSFET can be either an n-channel (nMOS) or p-channel, (pMOS) device, as shown in Fig. 9.36. The ac small-signal equivalent circuit of either device is shown in Fig. 9.36, revealing an open-circuit between gate and drainsource channel and a current source from drain to source having a magnitude dependent on the gate-to-source voltage. There is an output impedance from drain to source, rd, which is usually provided on specification sheets as an admittance yos. The device, transconductance, gm, is provided on specification sheets as the forward transfer admittance, yfs., , D, pMOS, , G, , D, , G, , S, , +, Vgs, , D, , gmVgs, , rd, , –, S, , nMOS, , G, S, , gm =yfs , rd = 1, yos, , Figure 9.36 Enhancement MOSFET ac small-signal model., , In our analysis of JFETs, an equation for gm was derived from Shockley’s equation. For E-MOSFETs, the relationship between output current and controlling voltage is defined by, ID k(VGS VGS(Th))2, Since gm is still defined by, ID, gm , VGS, we can take the derivative of the transfer equation to determine gm as an operating, point. That is,, dID, d, d, k(VGS VGS(Th))2 k (VGS VGS(Th))2, gm , dVGS, dVGS, dVGS, d, 2k(VGS VGS(Th)) (VGS VGS(Th)) 2k(VGS VGS(Th))(1 0), dVGS, and, 428, , Chapter 9, , gm 2k(VGSQ VGS(Th)), FET Small-Signal Analysis, , (9.45)
Page 440 :
gm, Recall that the constant k can be determined from a given typical operating point on, a specification sheet. In every other respect, the ac analysis is the same as that employed for JFETs or D-MOSFETs. Be aware, however, that the characteristics of an, E-MOSFET are such that the biasing arrangements are somewhat limited., , 9.10 E-MOSFET DRAIN-FEEDBACK, CONFIGURATION, The E-MOSFET drain-feedback configuration appears in Fig. 9.37. Recall from dc, calculations that RG could be replaced by a short-circuit equivalent since IG 0 A, and therefore VRG 0 V. However, for ac situations it provides an important high impedance between Vo and Vi. Otherwise, the input and output terminals would be connected directly and Vo Vi., VDD, RD, , RF, C2, , RF, , Vo, , Zo, , C1, Vi, , Ii, , Ii, , D, , +, , G, Zi, , Vi, , G, , D, , Vgs, , –, , S, , gmVgs, , rd, , –, , Zi, , Figure 9.37 E-MOSFET, drain-feedback configuration., , Vo, , +, RD, , Zo, , S, , Figure 9.38 AC equivalent of the, network of Fig. 9.37., , Substituting the ac equivalent model for the device will result in the network of, Fig. 9.38. Note that RF is not within the shaded area defining the equivalent model, of the device but does provide a direct connection between input and output circuits., Zi: Applying Kirchhoff’s current law to the output circuit (at node D in Fig., 9.38) results in, Vo, Ii gmVgs , rd RD, Vgs Vi, , and, , Vo, , rd RD, , so that, , Ii gmVi, , or, , Vo, Ii gmVi , rd RD, , Therefore,, with, , Vo (rd RD)(Ii gmVi), Vi (rd RD)(Ii gmVi), Vi Vo, Ii , , RF, RF, , and, , IiRF Vi (rd RD)Ii, , so that, , Vi[1, , and finally,, , (rd RD)gmVi, , gm(rd RD)] Ii[RF, , rd RD], , RF rd RD, V, Zi i , 1 gm(rd RD), Ii, , (9.46), , 9.10 E-MOSFET Drain-Feedback Configuration, , 429
Page 441 :
gm, Typically, RF, , rd RD, so that, RF, Zi , 1 gm(rd RD), , For rd, , 10RD,, RF, Zi , 1 gmRD, , (9.47), RF, , rd RD, rd, , 10RD, , Zo: Substituting Vi 0 V will result in Vgs 0 V and gmVgs 0, with a shortcircuit path from gate to ground as shown in Fig. 9.39. RF, rd, and RD are then in, parallel and, Zo RF rd RD, , (9.48), , RF, , gmVgs = 0 mA, , Vi = Vgs = 0 V, , rd, , RD, , Zo, , Figure 9.39 Determining Zo for the network of Fig. 9.37., , Normally, RF is so much larger than rd RD that, Zo rd RD, and with rd, , 10RD,, Zo RD, , (9.49), RF, , rd RD, rd, , 10RD, , Av: Applying Kirchhoff’s current law at node D of Fig. 9.38 will result in, Ii gmVgs, but, , Vi Vo, Vgs Vi and Ii , , RF, , so that, , Vi Vo, , gmVi, RF, , Vo, , rd RD, , and, , V, Vo, i , gmVi, RF, RF, , Vo, , rd RD, , so that, , and, , 430, , Vo, , rd RD, , Chapter 9, , , , 1, Vo , rd RD, , , , , , , , , 1, 1, Vi gm, RF, RF, 1, gm, RF, Vo , Av 1 1, Vi, rd RD RF, , FET Small-Signal Analysis
Page 442 :
1, , rd RD, , but, and, , 1, , RF, , gm, , Av gm(RF rd RD), , so that, Since RF is usually, , gm, , 1, 1, , RF, RF rd RD, , rd RD and if rd, , (9.50), , 10RD,, , Av gmRD, , (9.51), RF, , rd RD, rd 10RD, , Phase Relationship: The negative sign for Av reveals that Vo and Vi are out of, phase by 180°., , The E-MOSFET of Fig. 9.40 was analyzed in Example 6.11, with the result that, k 0.24 103 A/V2, VGSQ 6.4 V, and IDQ 2.75 mA., (a) Determine gm., (b) Find rd., (c) Calculate Zi with and without rd. Compare results., (d) Find Zo with and without rd. Compare results., (e) Find Av with and without rd. Compare results., , EXAMPLE 9.12, , 12 V, 2 kΩ, Vo, 1 µF, 10 MΩ, Vi, 1 µF, , Zo, , ID ( on) = 6 mA, VGS (on) = 8 V, VGS (Th) = 3 V, yos = 20 µS, , Zi, , Figure 9.40 Drain-feedback amplifier from Example 6.11., , Solution, (a) gm 2k(VGSQ VGS(Th)) 2(0.24 103 A/V2)(6.4 V 3 V), 1.63 mS, 1, 1, (b) rd 50 k, yos, 20 S, (c) With rd:, 10 M 50 k 2 k, RF rd RD, Zi , , 1, (1.63 mS)(50 k 2 k), 1 gm(rd RD), 10 M 1.92 k, 2.42 M, 1 3.13, , 9.10 E-MOSFET Drain-Feedback Configuration, , 431
Page 443 :
gm, Without rd:, RF, 10 M, Zi , 2.53 M, 1 (1.63 mS)(2 k), 1 gmRD, revealing that since the condition rd 10RD 50 k, results for Zo with or without rd will be quite close., (d) With rd:, , 40 k is satisfied, the, , Zo RF rd RD 10 M 50 k 2 k 49.75 k 2 k, 1.92 k, Without rd:, Zo RD 2 k, again providing very close results., (e) With rd:, Av gm(RF rd RD), (1.63 mS)(10 M 50 k 2 k), (1.63 mS)(1.92 k), 3.21, Without rd:, Av gmRD (1.63 mS)(2 k), 3.26, which is very close to the above result., , 9.11 E-MOSFET VOLTAGE-DIVIDER, CONFIGURATION, The last E-MOSFET configuration to be examined in detail is the voltage-divider network of Fig. 9.41. The format is exactly the same as appearing in a number of earlier discussions., Substituting the ac equivalent network for the E-MOSFET will result in the configuration of Fig. 9.42, which is exactly the same as Fig. 9.23. The result is that Eqs., (9.28) through (9.32) are applicable as listed below for the E-MOSFET., , VDD, , RD, Vo, , R1, D, C1, , Zo, G, , Vi, Vi, , S, Zi, , R2, RS, , CS, , D, , G, , Vo, , +, Zi, R1, , R2, , Zo, , Vgs, , gmVgs, , rd, , RD, , –, S, , Figure 9.41 E-MOSFET, voltage-divider configuration., , 432, , Figure 9.42 AC equivalent network for the configuration of Fig. 9.41., , Chapter 9, , FET Small-Signal Analysis
Page 444 :
gm, Zi:, Zi R1 R2, , (9.52), , Zo rd RD, , (9.53), , Zo:, , For rd, , 10RD,, Zo RD, , rd 10RD, , (9.54), , Av :, , and if rd, , Vo, Av , gm(rD RD), Vi, , (9.55), , Vo, gmRD, Av , Vi, , (9.56), , 10RD,, , 9.12 DESIGNING FET, AMPLIFIER NETWORKS, Design problems at this stage are limited to obtaining a desired dc bias condition or, ac voltage gain. In most cases, the various equations developed are used “in reverse”, to define the parameters necessary to obtain the desired gain, input impedance, or, output impedance. To avoid unnecessary complexity during the initial stages of the, design, the approximate equations are often employed because some variation will, occur when calculated resistors are replaced by standard values. Once the initial design is completed, the results can be tested and refinements made using the complete, equations., Throughout the design procedure be aware that although superposition permits a, separate analysis and design of the network from a dc and an ac viewpoint, a parameter chosen in the dc environment will often play an important role in the ac response. In particular, recall that the resistance RG could be replaced by a short-circuit, equivalent in the feedback configuration because IG 0 A for dc conditions, but, for the ac analysis, it presents an important high impedance path between Vo and, Vi. In addition, recall that gm is larger for operating points closer to the ID axis, (VGS 0 V), requiring that RS be relatively small. In the unbypassed RS network, a, small RS will also contribute to a higher gain, but for the source-follower, the gain is, reduced from its maximum value of 1. In total, simply keep in mind that network parameters can affect the dc and ac levels in different ways. Often a balance must be, made between a particular operating point and its impact on the ac response., In most situations, the available dc supply voltage is known, the FET to be employed has been determined, and the capacitors to be employed at the chosen frequency are defined. It is then necessary to determine the resistive elements necessary, to establish the desired gain or impedance level. The next three examples will determine the required parameters for a specific gain., 9.12 Designing FET Amplifier Networks, , 433
Page 445 :
gm, EXAMPLE 9.13, , Design the fixed-bias network of Fig. 9.43 to have an ac gain of 10. That is, determine the value of RD., , VDD (+30 V), , RD, Vo, C1, Vi, 0.1 µF, , RG, 10 MΩ, , IDSS = 10 mA, VP = – 4 V, yos = 20 µS, , Figure 9.43 Circuit for desired, voltage gain in Example 9.13., , Solution, Since VGSQ 0 V, the level of gm is gm0. The gain is therefore determined by, Av gm(RD rd) gm0(RD rd), 2I SS, 2(10 mA), gm0 D, 5 mS, VP, 4V, , with, The result is, , 10 5 mS(RD rd), , and, , 10, RD rd 2 k, 5 mS, , From the device specifications,, 1, 1, rd , 50 k, yos, 20 106 S, Substituting, we find, RD rd RD 50 k 2 k, and, or, , RD(50 k), , 2 k, RD 50 k, 50RD 2(RD, , 50 k) 2RD, , with, , 48RD 100 k, , and, , 100 k, RD 2.08 k, 48, , 100 k, , The closest standard value is 2 k (Appendix C), which would be employed for this, design., The resulting level of VDSQ would then be determined as follows:, VDSQ VDD IDQRD 30 V (10 mA)(2 k) 10 V, The levels of Zi and Zo are set by the levels of RG and RD, respectively. That is,, Zi RG 10 M, Zo RD rd 2 k 50 k 1.92 k RD 2 k., 434, , Chapter 9, , FET Small-Signal Analysis
Page 446 :
gm, Choose the values of RD and RS for the network of Fig. 9.44 that will result in a gain, of 8 using a relatively high level of gm for this device defined at VGSQ 14VP., , EXAMPLE 9.14, , VDD, +20 V, , RD, , C2, Vo, , C1, Vi, , 0.1 µF, , 0V, , RL, 10 MΩ, , 0.1 µF, RG, 10 MΩ, , CS, 40 µF, , RS, , IDSS = 10 mA, VP = – 4 V, yos = 20 µS, , gm 0 = 5 mS, , Figure 9.44 Network for desired voltage gain in Example 9.14., , Solution, The operating point is defined by, 1, 1, VGSQ VP (4 V) 1 V, 4, 4, and, , VGSQ, ID IDSS 1 , VP, , , , (1 V), 10 mA 1 , (4 V), , , , , , 2, , , , 2, , 5.625 mA, , Determining gm,, VGSQ, gm gm0 1 , VP, (1 V), 5 mS 1 3.75 mS, (4 V), , , , , , , , , , The magnitude of the ac voltage gain is determined by, Av gm(RD rd), Substituting known values will result in, 8 (3.75 mS)(RD rd), so that, , 8, RD rd 2.13 k, 3.75 mS, , The level of rd is defined by, 1, 1, rd 50 k, yos, 20 S, and, , RD 50 k 2.13 k, , with the result that, RD 2.2 k, which is a standard value., 9.12 Designing FET Amplifier Networks, , 435
Page 447 :
gm, The level of RS is determined by the dc operating conditions as follows:, VGSQ IDRS, 1 V (5.625 mA)RS, 1V, RS 177.8 , 5.625 mA, , and, , The closest standard value is 180 . In this example, RS does not appear in the ac, design because of the shorting effect of CS., In the next example, RS is unbypassed and the design becomes a bit more complicated., , EXAMPLE 9.15, , Determine RD and RS for the network of Fig. 9.44 to establish a gain of 8 if the bypass capacitor CS is removed., , Solution, VGSQ and IDQ are still 1 V and 5.625 mA, and since the equation VGS IDRS has, not changed, RS continues to equal the standard value of 180 obtained in Example 9.14., The gain of an unbypassed self-bias configuration is, gmRD, , Av , 1 gmRS, For the moment it is assumed that rd 10(RD RS). Using the full equation for, Av at this stage of the design would simply complicate the process unnecessarily., Substituting (for the specified magnitude of 8 for the gain),, (3.75 mS)RD, (3.75 mS)RD, , 8 , 1 (3.75 mS)(180 ), 1 0.675, , , , , , 0.675) (3.75 mS)RD, , and, , 8(1, , so that, , 13.4, RD 3.573 k, 3.75 mS, , with the closest standard value at 3.6 k., We can now test the condition:, rd, and, , 10(RD, , RS), , 50 k, , 10(3.6 k, , 50 k, , 37.8 k, , 0.18 k) 10(3.78 k), , which is satisfied—the solution stands!, , 9.13 SUMMARY TABLE, In an effort to provide a quick comparison between configurations and offer a listing, that can be helpful for a variety of reasons, Table 9.1 was developed. The exact and, approximate equation for each important parameter are provided with a typical range, of values for each. Although all the possible configurations are not present, the majority of the most frequently encountered are included. In fact, any configuration not, 436, , Chapter 9, , FET Small-Signal Analysis
Page 450 :
gm, listed will probably be some variation of those appearing in the table, so at the very, least, the listing will provide some insight as to what expected levels should be and, which path will probably generate the desired equations. The format chosen was designed to permit a duplication of the entire table on the front and back of one 812 by, 11 inch page., , 9.14 TROUBLESHOOTING, As mentioned before, troubleshooting a circuit is a combination of knowing the theory and having experience using meters and an oscilloscope to check the operation, of the circuit. A good troubleshooter has a “nose” for finding the trouble in a, circuit—this ability to “see” what is happening being greatly developed through building, testing, and repairing many different circuits. For an FET small-signal amplifier,, one could go about troubleshooting a circuit by performing a number of basic steps:, 1. Look at the circuit board to see if any obvious problems can be seen: an area, charred by excess heating of a component; a component that feels or seems too, hot to touch; what appears to be a poor solder joint; any connection that appears, to have come loose., 2. Use a dc meter: make some measurements as marked in a repair manual containing the circuit schematic diagram and a listing of test dc voltages., 3. Apply a test ac signal: measure the ac voltages starting at the input and working, along toward the output., 4. If the problem is identified at a particular stage, the ac signal at various points, should be checked using an oscilloscope to see the waveform, its polarity, amplitude, and frequency, as well as any unusual waveform “glitches” that may be present. In particular, observe that the signal is present for the full signal cycle., , Possible Symptoms and Actions, If there is no output ac voltage:, 1., 2., 3., 4., , Check, Check, Check, Check, , if the supply voltage is present., if the output voltage at VD is between 0 V and VDD., if there is any input ac signal at the gate terminal., the ac voltage at each side of the coupling capacitor terminals., , When building and testing a FET amplifier circuit in the laboratory:, 1. Check the color code of resistor values to be sure that they are correct. Even better, measure the resistor value as components used repeatedly may get overheated, when used incorrectly, causing the nominal value to change., 2. Check that all dc voltages are present at the component terminals. Be sure that all, ground connections are made common., 3. Measure the ac input signal to be sure the expected value is provided to the circuit., , 9.15 PSPICE WINDOWS, JFET Fixed-Bias Configuration, The first JFET configuration to be analyzed using PSpice Windows is the fixed-bias, configuration of Fig. 9.45, which has a JFET with VP 4 V and IDSS , 10 mA. The 10-M resistor was added to act as a path to ground for the capacitor, 9.15 PSpice Windows, , 439
Page 451 :
gm, but is essentially an open-circuit as a load. The J2N3819 n-channel JFET from the, EVAL.slb library will be used, and the ac voltage will be determined at four different points for comparison and review., , Figure 9.45 Fixed-bias JFET, configuration with an ac source., , The constant Beta is determined by, 10 mA, I SS, Beta D, , 0.625 mA/V2, 42, Vp 2, and inserted as a Model Parameter using the sequence Edit-Model-Edit Instance, Model (Text). Vto must also be changed to 4 V. The remaining elements of the network are set as described for the transistor in Chapter 8., An analysis of the network will result in the printout of Fig. 9.46. The Schematics Netlist reveals the nodes assigned to each parameter and defines the nodes for, which the ac voltage is to be printed. In this case, note that Vi is set at 10 mV at a, frequency of 10kHz from node 2 to 0. In the list of Junction FET MODEL, PARAMETERS, VTO is 4 V and BETA is 625E-6 as entered. The SMALLSIGNAL BIAS SOLUTION reveals that the voltage at both ends of RG is 1.5 V,, resulting in VGS 1.5 V. The voltage from drain to source (ground) is 12 V, leaving a drop of 8 V across RD. The AC ANALYSIS at the end of the listing reveals that, the voltage at the source (node 2) is 10 mV as set, but the voltage at the other end of, the capacitor is 3 V less due to the impedance of the capacitor at 10 kHz—certainly, a drop to be ignored. The choice of 0.02 F for this frequency was obviously a good, one. The voltages before and after the capacitor on the output side are exactly the, same (to three places), revealing that the larger the capacitor, the closer the characteristics to a short circuit. The output of 6.275E-2 62.75 mV reflects a gain of 6.275., The OPERATING POINT INFORMATION reveals that ID is 4 mA and gm is, 3.2 mS. Calculating the value of gm from:, VGSQ, 2I SS, gm D, 1 , VP, VP, 2 (10 mA), (1.5 V), 1 , 4V, (4 V), , , , , , , , 3.125 mS, confirming our analysis., 440, , Chapter 9, , FET Small-Signal Analysis, ,
Page 452 :
gm, , Figure 9.46 Output file for the, network of Figure 9.45., , 9.15 PSpice Windows, , 441
Page 453 :
gm, JFET Self-Bias Configuration, The self-bias configuration of Fig. 9.47 will be analyzed using the J2N3819 JFET, from the library and then using an approximate equivalent circuit. It will be interesting to see if there are any major differences in solution., , Figure 9.47 Self-bias, configuration with an ac source., , Again, VP 4 V and IDSS 10 mA, resulting in a Vto of 4 and a Beta of, 6.25E-4. The Analysis is run and the results of Fig. 9.48 obtained. The nodes are, identified in the Schematics Netlist and the parameters in the Junction FET MODEL, PARAMETERS. The SMALL-SIGNAL BIAS SOLUTION reveals that VGS , 1.7114 V and VD 14.228 V—results that are very close to a hand-written solution of 1.68 V and 14.49 V. The OPERATING POINT INFORMATION reveals, that ID is 3.36 mA compared to a hand-calculated level of 3.3 mA and that gm is 2.94, mS compared to a hand-calculated level of 2.90 mS. The AC ANALYSIS provides, an output level of 13.3 mV at an angle of 179.9°, which compares well with a handcalculated level of 13.63 mV at an angle of 180°. The results for JFETs are a lot, closer than those obtained for transistors when we used the provided elements because of the special feature of having essentially infinite input impedance so that the, gate current is zero ampere. Recall that for the transistor, VBE is a function of the operating conditions., We will now investigate the self-bias configuration using the approximate model, as done for the transistor and see if there is an improvement in the results (compared, to the hand-calculated levels). In this case, we need the voltage controlled current, source (VCCS) found in the ANALOG.slb library as G. When selected, the Description reads Voltage-controlled current source. When placed on the schematic,, it will appear as shown in Fig. 9.49. The sensing voltage is between the plus and minus sign, while the controlled current is between the other two external terminals., , Figure 9.49 Network in, Figure 9.47 following substitution, of a VCCS for the JFET in the ac, domain., , 442, , Chapter 9, , FET Small-Signal Analysis
Page 454 :
gm, , Figure 9.48 Output file for the, network of Figure 9.47., , 9.15 PSpice Windows, , 443
Page 455 :
gm, , Figure 9.50 JFET voltage-divider, configuration with an ac source., , Double-clicking on the schematic symbol will result in a PartName: G dialog box,, in which the GAIN(gm) can be set to the hand-calculated level of 2.90 mS., The result of an analysis is a gain of 13.62—almost an exact match with the handwritten gain. This approach is certainly valid for an ac analysis, but if we examine, the SMALL-SIGNAL BIAS SOLUTION, we find that the results are meaningless., Therefore, the equivalent appearing in Fig. 9.49 is only valid for the ac gain since the, only parameter defined is the ac transconductance factor., , JFET Voltage-Divider Configuration, The last network to be analyzed in this PSpice Windows presentation is the voltagedivider configuration of Fig. 9.50. Note that the parameters chosen are different from, those employed in earlier examples, with Vi at 24 mV and a frequency of 5 kHz. In, addition, the dc levels are displayed and a plot of the output and input voltages will, be obtained on the same screen., After setting up the network, the source Vi must be set to the indicated parameters by double-clicking on the source and then sequentially double-clicking on each, parameter and typing in the correct values. Each must be saved and then the display, changed to print the magnitude of the ac voltage and the applied frequency. In this, example, the JFET parameters were printed on the screen using the ABC icon. BETA, is of course calculated from IDSS/VP2. Under Analysis-Probe Setup, the option Do, not auto-run Probe was chosen, and under Setup, AC Sweep was chosen and the, frequency of 5 kHz entered. Finally, since we want the dc levels to be displayed, the, Display Results on Schematic option is chosen under Analysis, and Enable, Voltage Display is enabled. The resulting dc levels of Fig. 9.50 reveal that VGS is, 1.823 V 3.635 V 1.812 V, comparing very well with the 1.8 V calculated in, Example 6.5. VD is 10.18 V compared to the calculated level of 10.24 V, and VDS is, 10.18 V 3.635 V 6.545 V compared to 6.64 V., For the ac solution, we can choose Examine Output under Analysis and find under OPERATING POINT INFORMATION that gm is 2.22 mS, comparing very, well with the hand-calculated value of 2.2 mS, and under AC ANALYSIS that the, output ac voltage is 125.8 mV, resulting in a gain of 125.8 mV/24 mV 5.24. The, hand-calculated level is gmRD (2.2 mS)(2.4 k) 5.28. The ac waveform for the, output can be obtained by first applying the sequence Analysis-Probe SetupAutomatically run Probe after simulation. Then, return to Setup under Analysis,, and enable Transient, disable AC Sweep, and double-click Transient to obtain the, Transient dialog box. For the frequency of 5 kHz, the period is 200 s. A Print Step, to 2 s would then give us 100 plot points for each cycle. The Final Time will be, 5 200 s 1 ms to show five cycles. The No-Print Delay will be 0s and the Step, Ceiling 2s. Then, click the Trace icon, choose V(J1:d), and the output waveform, of Fig. 9.51 will appear. Choose Plot-Add Plot-Trace-Add-V(Vi:+), and both wave444, , Chapter 9, , FET Small-Signal Analysis
Page 456 :
gm, forms will appear as shown. Shift SEL, to the bottom waveform by simply bringing the pointer to the left of the lower waveform and left-clicking the mouse once., Click the Toggle cursor icon, and a horizontal line will appear at the dc level of the, output voltage at 10.184 V. A left click of the mouse and an intersecting set of lines, will appear. Choose the Cursor Peak icon, and the intersection will automatically go, to the peak value of the waveform (A1 in the dialog box). The difference appearing, in the dialog box is 125.496 mV, comparing well with the printed value in the output, file. The difference is simply due to the number of points chosen for the plot; an increased number of plot points would have brought the two levels closer together., , Figure 9.51 The ac drain and gate voltage for the voltage-divider JFET, configuration of Figure 9.50., , PROBLEMS, , § 9.2 FET Small-Signal Model, 1. Calculate gm0 for a JFET having device parameters IDSS 15 mA and VP 5 V., 2. Determine the pinch-off voltage of a JFET with gm0 10 mS and IDSS 12 mA., 3. For a JFET having device parameters gm0 5 mS and VP 3.5 V, what is the device current at VGS 0 V?, 4. Calculate the value of gm for a JFET (IDSS 12 mA, VP 3 V) at a bias point of VGS , 1 V., 5. For a JFET having gm 6 mS at VGSQ 1 V, what is the value of IDSS if VP 2.5 V?, 6. A JFET (IDSS 10 mA, VP 5 V) is biased at ID IDSS/4. What is the value of gm at that, bias point?, 7. Determine the value of gm for a JFET (IDSS 8 mA, VP 5 V) when biased at VGSQ VP/4., 8. A specification sheet provides the following data (at a listed drain–source current), yfs 4.5 mS,, , yos 25 S, , At the listed drain–source current, determine:, (a) gm., (b) rd., 9. For a JFET having specified values of yfs 4.5 mS and yos 25 S, determine the device output impedance, Zo(FET), and device ideal voltage gain, Av(FET)., Problems, , 445
Page 457 :
gm, 10. If a JFET having a specified value of rd 100 k has an ideal voltage gain of Av(FET) , 200, what is the value of gm?, 11. Using the transfer characteristic of Fig. 9.52:, (a) What is the value of gm0?, (b) Determine gm at VGS 1.5 V graphically., (c) What is the value of gm at VGSQ 1.5 V using Eq. (9.6)? Compare with the solution to, part (b)., (d) Graphically determine gm at VGS 2.5 V., (e) What is the value of gm at VGSQ 2.5 V using Eq. (9.6)? Compare with the solution to, part (d)., ID (mA), 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, −5, , −4, , −3, , −2, , −1, , 0, , VGS (V), , Figure 9.52 JFET transfer, characteristic for Problem 11, , 12. Using the drain characteristic of Fig. 9.53:, (a) What is the value of rd for VGS 0 V?, (b) What is the value of gm0 at VDS 10 V?, ID (mA), 10, , VGS = 0 V, , 9, 8, 7, 6, , −1 V, , 5, 4, 3, , −2 V, , 2, −3 V, , 1, 0, , 1, , 2, , 3, , 4, , 5, , 6, , 7, , 8, , 9, , 10 11 12 13 14 15 16 17 18 19 20, , Figure 9.53 JFET drain characteristic for Problem 12, , 13. For a 2N4220 n-channel JFET (yfs(minimum) 750 S, yos(maximum) 10 S):, (a) What is the value of gm?, (b) What is the value of rd?, 14. (a) Plot gm vs. VGS for an n-channel JFET with IDSS 8 mA and VP 6 V., (b) Plot gm vs. ID for the same n-channel JFET as part (a)., , 446, , Chapter 9, , FET Small-Signal Analysis, , −4 V, VDS (V
Page 458 :
gm, 15. Sketch the ac equivalent model for a JFET if yfs 5.6 mS and yos 15 S., 16. Sketch the ac equivalent model for a JFET if IDSS 10 mA, VP 4 V, VGSQ 2 V, and, yos 25 S., , § 9.3 JFET Fixed-Bias Configuration, 17. Determine Zi, Zo and Av for the network of Fig. 9.54 if IDSS 10 mA, VP 4 V, and rd , 40 k., 18. Determine Zi, Zo, and Av for the network of Fig. 9.54 if IDSS 12 mA, VP 6 V, and yos , 40 S., , +18 V, , 1.8 kΩ, Vo, Vi, Zo, 1 MΩ, Zi, 1.5 V, , –, +, , Figure 9.54 Fixed-bias amplifier for Problems 17 and 18, , § 9.4 JFET Self-Bias Configuration, 19. Determine Zi, Zo, and Av for the network of Fig. 9.55 if yfs 3000 S and yos 50 s., 20. Determine Zi, Zo, and Av for the network of Fig. 9.56 if IDSS 6 mA, VP 6 V, and yos , 40 S., 21. Determine Zi, Zo, and Av for the network of Fig. 9.55 if the 20-F capacitor is removed and, the parameters of the network are the same as in Problem 19. Compare results with those of, Problem 19., 22. Repeat Problem 19 if yos is 10 S. Compare the results to those of Problem 19., , +12 V, , 20 V, 2 kΩ, , 3.3 kΩ, , Vo, , Vo, Vi, , Zi, , Zo, , Vi, , Zo, Zi, , 10 MΩ, 1.1 kΩ, , Figure 9.55 Problems 19, 21, and 46, , 1 MΩ, , 20 µF, , Figure 9.56 Self-bias configuration for, Problems 20 and 47, , Problems, , 447
Page 459 :
gm, § 9.5 JFET Voltage-Divider Configuration, 23. Determine Zi, Zo, and Vo for the network of Fig. 9.57 if Vi 20 mV., , +20 V, , 2 kΩ, 82 MΩ, Vo, IDSS = 12 mA, VP = − 3 V, rd = 100 kΩ, , Vi, Zi, 11 MΩ, , RS, 610 Ω, , Zo, , CS, , Figure 9.57 Problems 23–26, and 48, , 24. Determine Zi, Zo, and Vo for the network of Fig. 9.57 if Vi 20 mV and the capacitor CS is, removed., 25. Repeat Problem 23 if rd 20 k and compare results., 26. Repeat Problem 24 if rd 20 k and compare results., , § 9.6 JFET Source-Follower Configuration, 27. Determine Zi, Zo, and Av for the network of Fig. 9.58., 28. Repeat Problem 27 if rd 20 k., 29. Determine Zi, Zo, and Av for the network of Fig. 9.59., , 20 V, +20 V, , 3.3 kΩ, IDSS = 9 mA, VP = −4.5 V, rd = 40 kΩ, , Vi, Zi, , Vi, , Vo, , 10 MΩ, 2.2 kΩ, , IDSS = 6 mA, VP = −6 V, rd = 30 kΩ, Zi, , 3.3 kΩ, , Zo, , Figure 9.58 Problems 27 and 28, , Figure 9.59 Problem 29, , § 9.7 JFET Common-Gate Configuration, 30. Determine Zi, Zo, and Vo for the network of Fig. 9.60 if Vi 0.1 mV., 31. Repeat Problem 30 if rd 25 k., 32. Determine Zi, Zo, and Av for the network of Fig. 9.61 if rd 33 k., , 448, , Chapter 9, , FET Small-Signal Analysis, , Vo, , 10 MΩ, , Zo
Page 461 :
gm, 35. Repeat Problem 34 if rd 25 k., 36. Determine Vo for the network of Fig. 9.64 if Vi 4 mV., 37. Determine Zi, Zo, and Av for the network of Fig. 9.65., +18 V, +20 V, 6.8 kΩ, 91 MΩ, , Vo, 91 MΩ, , yos = 35 µS, yfs = 6000 µS, , Vi, , Vi, , IDSS = 12 mA, VP = −3 V, rd = 45 kΩ, Vo, , 15 MΩ, , Zi, 3.3 kΩ, , Figure 9.64 Problem 36, , 10 MΩ, , 1.1 kΩ, , Zo, , Figure 9.65 Problem 37, , § 9.10 E-MOSFET Drain-Feedback Configuration, 38. Determine gm for a MOSFET if VGS(Th) 3 V and it is biased at VGSQ 8 V. Assume k , 0.3 103., 39. Determine Zi, Zo, and Av for the amplifier of Fig. 9.66 if k 0.3 103., +16 V, , 2.2 kΩ, Vo, 10 MΩ, , Zo, VGS(Th) = 3 V, rd = 100 kΩ, , Vi, Zi, , Figure 9.66 Problems 39, 40, and 51, , 40. Repeat Problem 39 if k drops to 0.2 103. Compare results., 41. Determine Vo for the network of Fig. 9.67 if Vi 20 mV., 42. Determine Vo for the network of Fig. 9.67 if Vi 4 mV, VGS(Th) 4 V, and ID(on) 4 mA, with, VGS(on) 7 V and yos 20 S., +20 V, , 10 kΩ, 22 MΩ, Vo, , Vi, , VGS(Th) = 3.5 V, k = 0.3 × 10−3, yos = 30 µS, , Figure 9.67 Problems 41 and 42, , 450, , Chapter 9, , FET Small-Signal Analysis
Page 462 :
gm, § 9.11 E-MOSFET Voltage-Divider Configuration, 43. Determine the output voltage for the network of Fig. 9.68 if Vi 0.8 mV and rd 40 k., , 30V, , 3.3 kΩ, 40 MΩ, , +, VGS(Th) = 3 V, k = 0.4 × 10 −3, , +, , Vo, , Vi, , 10 MΩ, 1.2 kΩ, , –, , –, Figure 9.68 Problem 43, , § 9.12 Designing FET Amplifier Networks, 44. Design the fixed-bias network of Fig. 9.69 to have a gain of 8., 45. Design the self-bias network of Fig. 9.70 to have a gain of 10. The device should be biased at, VGSQ 13VP., , +VDD (+22 V), +VDD (+20 V), RD, , RD, Vo, IDSS = 8 mA, VP = − 2.5 V, yos = 25 µS, , Vi, 10 MΩ, , Vo, IDSS = 12 mA, VP = − 3 V, rd = 40 kΩ, , Vi, 10 MΩ, RS, , Figure 9.69 Problem 44, , Figure 9.70 Problem 45, , § 9.13 PSpice Windows, 46. Using PSpice Windows, determine the voltage gain for the network of Fig. 9.55., 47. Using PSpice Windows, determine the voltage gain for the network of Fig. 9.56., 48. Using PSpice Windows, determine the voltage gain for the network of Fig. 9.57., 49. Using PSpice Windows, determine the voltage gain for the network of Fig. 9.60., 50. Using PSpice Windows, determine the voltage gain for the network of Fig. 9.63., 51. Using PSpice Windows, determine the voltage gain for the network of Fig. 9.66., Problems, , 451
Page 463 :
Rs /RL, , CHAPTER, , 10, , Systems Approach—, Effects of Rs and RL, 10.1 INTRODUCTION, In recent years, the introduction of a wide variety of packaged networks and systems, has generated an increasing interest in the systems approach to design and analysis., Fundamentally, this approach concentrates on the terminal characteristics of a package and treats each as a building block in the formation of the total package. The content of this chapter is a first step in developing some familiarity with this approach., The techniques introduced will be used in the remaining chapters and broadened as, the need arises. The trend to packaged systems is quite understandable when you consider the enormous advances in the design and manufacturing of integrated circuits, (ICs). The small IC packages contain stable, reliable, self-testing, sophisticated designs that would be quite bulky if built with discrete (individual) components. The, systems approach is not a difficult one to apply once the basic definitions of the various parameters are correctly understood and the manner in which they are utilized, is clearly demonstrated. In the next few sections, we develop the systems approach, in a slow deliberate manner that will include numerous examples to make each salient, point. If the content of this chapter is clearly and correctly understood, a first plateau, in the understanding of system analysis will be accomplished., , 10.2, , Ii, , Io, , +, Zi, , AυNL AiNL, , Vi, , Zo, , –, , TWO-PORT SYSTEMS, , The description to follow can be applied to any two-port system—not only those containing BJTs and FETs—although the emphasis in this chapter is on these active devices. The emphasis in previous chapters on determining the two-port parameters for, various configurations will be quite helpful in the analysis to follow. In fact, many of, the results obtained in the last two chapters are utilized in the analysis to follow., In Fig. 10.1, the important parameters of a two-port system have been identified., Note in particular the absence of a load and a source resistance. The impact of these, + important elements is considered in detail in a later section. For the moment recogVo nize that the impedance levels and the gains of Fig. 10.1 are determined for no-load, (absence of RL) and no-source resistance (Rs) conditions., –, If we take a “Thévenin look” at the output terminals we find with Vi set to zero, that, , Thévenin, , Figure 10.1 Two-port system., , 452, , ZTh Zo Ro, , (10.1)
Page 464 :
Rs /RL, ETh is the open-circuit voltage between the output terminals identified as Vo. However,, Vo, AvNL , Vi, and, so that, , Vo AvNLVi, ETh AvNLVi, , (10.2), , Note the use of the additional subscript notation “NL” to identify a no-load voltage, gain., Substituting the Thévenin equivalent circuit between the output terminals will result in the output configuration of Fig. 10.2. For the input circuit the parameters Vi, and Ii are related by Zi Ri, permitting the use of Ri to represent the input circuit., Since our present interest is in BJT and FET amplifiers, both Zo and Zi can be represented by resistive elements., , Figure 10.2 Substituting the internal elements for the two-port, system of Fig. 10.1., , Before continuing let us check the results of Fig. 10.2 by finding Zo and AvNL in, the usual manner. To find Zo, Vi is set to zero, resulting in AvNLVi 0, permitting, a short-circuit equivalent for the source. The result is an output impedance equal to, Ro as originally defined. The absence of a load will result in Io 0, and the voltage, drop across the impedance Ro will be 0 V. The open-circuit output voltage is therefore, AvNLVi, as it should be. Before looking at an example, take note of the fact that Ai, does not appear in the two-port model of Fig. 10.2 and in fact is seldom part of the, two-port system analysis of active devices. This is not to say that the quantity is seldom calculated, but it is most frequently calculated from the expression Ai , Av(Zi/RL), where RL is the defined load for the analysis of interest., For the fixed-bias transistor network of Fig. 10.3 (Example 8.1), sketch the two-port, equivalent of Fig. 10.2., , EXAMPLE 10.1, , Figure 10.3 Example 10.1., , 10.2, , Two-Port Systems, , 453
Page 465 :
Rs /RL, Solution, From Example 8.1,, Zi 1.069 k, Zo 3 k, AvNL 280.11, Using the information above, the two-port equivalent of Fig. 10.4 can be drawn. Note, in particular the negative sign associated with the controlled voltage source, revealing an opposite polarity for the controlled source than that indicated in the figure. It, also reveals a 180° phase-shift between the input and output voltages., , +, , +, Vi, , –, , Ri, , Ro = 3 kΩ, −280.11Vi, , 1.069 kΩ, , –, , +, Vo, , –, , Figure 10.4 Two-port equivalent for the parameters specified, in Example 10.1., , In Example 10.1, RC 3 k was included in defining the no-load voltage gain., Although this need not be the case (RC could be defined as the load resistor in Chapter 8), the analysis of this chapter will assume that all biasing resistors are part of the, no-load gain and that a loaded system requires an additional load RL connected to the, output terminals., A second format for Fig. 10.2, particularly popular with op-amps (operational, amplifiers), appears in Fig. 10.5. The only change is the general appearance of the, model., , Figure 10.5 Operational amplifier (op-amp) notation., , 10.3 EFFECT OF A LOAD IMPEDANCE (RL), In this section, the effect of an applied load is investigated using the two-port model, of Fig. 10.2. The model can be applied to any current- or voltage-controlled amplifier. AvNL is, as defined earlier, the gain of the system without an applied load. Ri and, Ro are the input and output impedances of the amplifier as defined by the configuration. Ideally, all the parameters of the model are unaffected by changing loads or, 454, , Chapter 10, , Systems Approach—Effects of Rs and RL
Page 466 :
Rs /RL, source resistances (as normally encountered for op-amps to be described in Chapter, 14). However, for some transistor amplifier configurations, Ri can be quite sensitive, to the applied load, while for others Ro can be sensitive to the source resistance. In, any case, once AvNL, Ri, and Ro are defined for a particular configuration, the equations about to be derived can be employed., Applying a load to the two-port system of Fig. 10.2 will result in the configuration of Fig. 10.6. Applying the voltage-divider rule to the output circuit will result in, RLAvNL Vi, Vo , RL Ro, and, , Vo, RL, Av AvNL, Vi, RL Ro, , (10.3), , Figure 10.6 Applying a load to, the two-port system of Fig. 10.2., , Since the ratio RL/(RL Ro) will always be less than 1:, The loaded voltage gain of an amplifier is always less than the no-load level., Note also that the formula for the voltage gain does not include the input impedance, or current gain., Although the level of Ri may change with the configuration, the applied voltage, and input current will always be related by, Vi, Vi, Ii , Zi, Ri, , (10.4), , Defining the output current as the current through the load will result in, Vo, Io , RL, , (10.5), , with the minus sign occurring due to the defined direction for Io in Fig. 10.6., The current gain is then determined by, Vo /RL, Io, Vo Zi, Ai , Vi/Zi, Ii, Vi RL, and, Zi, Ai Av, RL, , (10.6), , for the unloaded situation. In general, therefore, the current gain can be obtained from, the voltage gain and impedance parameters Zi and RL. The next example will demonstrate the usefulness and validity of Eqs. (10.3) through (10.6)., 10.3 Effect of a Load Impedance (RL), , 455
Page 467 :
Rs /RL, EXAMPLE 10.2, , In Fig. 10.7, a load has been applied to the fixed-bias transistor amplifier of Example 10.1 (Fig. 10.3)., (a) Determine the voltage and current gain using the two-port systems approach defined by the model of Fig. 10.4., (b) Determine the voltage and current gain using the re model and compare results., 12 V, , RC, RB, Ii, , 3 kΩ, , 470 kΩ, , Io, , +, , CC, , β = 100, , +, Vi, , Zo, , RL, , 2.2 kΩ Vo, , Zi, , –, , –, , Figure 10.7 Example 10.2., , Solution, (a) Recall from Example 10.1 that, Zi 1.071 k, , (with re 10.71 and 100), , Zo 3 k, Av 280.11, NL, , Applying Eq. (10.3) yields, RL, Av AvNL, RL Ro, 2.2 k, (280.11), 2.2 k 3 k, (0.423)(280.11), 118.5, For the current gain,, Zi, Ai Av , RL, In this case, Zi is unaffected by the applied load and, 1.071 k, Ai (118.5) 57.69, 2.2 k, (b) Substituting the re model will result in the network of Fig. 10.8. Note in particular that the applied load is in parallel with the collector resistor RC defining a, net parallel resistance, RL RC RL 3 k2.2 k 1.269 k, The output voltage, Vo IBRL, , 456, , Chapter 10, , Systems Approach—Effects of Rs and RL
Page 468 :
Rs /RL, Ib, , Ii, , +, Vi, , Io, , RB, , +, , Zo, , Zi, , β Ib, , β re, , 470 kΩ, , RC, , RL, , 3 kΩ, , 2.2 kΩ Vo, , –, , –, R'L, , Figure 10.8 Substituting the re model in the ac equivalent network of Fig. 10.7., , with, , Vi, Ib , re, , and, , Vi, Vo RL, re, RL, RC RL, Vo, Av , re, re, Vi, , so that, , (10.7), , Substituting values gives, 1.269 k, Av 118.5, 10.71 , as obtained above. For the current gain, by the current-divider rule,, (470 k)Ii, Ib 0.9977Ii Ii, 470 k 1.071 k, and, , 3 k(Ib), Io , 3 k 2.2 k, 0.5769Ib, , so that, , 0.5769Ib, 0.5769Ii, Io, Ai , I, Ii, Ii, i, 0.5769(100) 57.69, , as obtained using Eq. (10.6)., Example 10.2 demonstrated two techniques to solve the same problem. Although, any network can be solved using the re model approach, the advantage of the systems, approach is that once the two-port parameters of a system are known, the effect of, changing the load can be determined directly from Eq. (10.3). No need to go back to, the ac equivalent model and analyze the entire network. The advantages of the systems approach are similar to those associated with applying Thévenin’s theorem. They, permit concentrating on the effects of the load without having to re-examine the entire network. Of course, if the network of Fig. 10.7 were presented for analysis without the unloaded parameters, it would be a toss-up as to which approach would yield, the desired results in the most direct, efficient manner. However, keep in mind that, the “package” approach is the developing trend. When you purchase a “system” the, two-port parameters are provided, and as with any trend, the user must be aware of, how to utilize the given data., , 10.3 Effect of a Load Impedance (RL), , 457
Page 469 :
Rs /RL, The AC Load Line, For a system such as appearing in Fig. 10.9a, the dc load line was drawn on the output characteristics as shown in Fig. 10.9b. The load resistance did not contribute to, the dc load line since it was isolated from the biasing network by the coupling capacitor (CC). For the ac analysis, the coupling capacitors are replaced by a short-circuit equivalence that will place the load and collector resistors in a parallel arrangement defined by, RL RC RL, The effect on the load line is shown in Fig. 10.9b with the levels to determine the, new axes intersections. Note of particular importance that the ac and dc load lines, pass through the same Q-point—a condition that must be satisfied to ensure a common solution for the network under dc and/or ac conditions., For the unloaded situation, the application of a relatively small sinusoidal signal, to the base of the transistor could cause the base current to swing from a level of IB2, to IB4 as shown in Fig. 10.9b. The resulting output voltage vce would then have the, swing appearing in the same figure. The application of the same signal for a loaded, situation would result in the same swing in the IB level, as shown in Fig. 10.9b. The, result, however, of the steeper slope of the ac load line is a smaller output voltage, , ICQ +, , IC, , VCEQ, RL', , ac load line, IB, , Du, , t, , et, , oV, , i, , 6, , IB, , 5, , VCEQ, VCC, RC, , IB, , iB, , R'L, , VCC, , 4, , RC, , CC, , +, , 3, , Q-point, , IB, , 2, , CC, , RL V, o, , Ib, , Vi, , –, , ICQ, , dc load line, , (a), , 0, , VCEQ, , ICQ R'L, , 0, , vce, vce, , t, , Figure 10.9 Demonstrating the differences between the dc and ac load lines., , Chapter 10, , Systems Approach—Effects of Rs and RL, , VCC, , VCEQ + ICQ R'L, , (b), , 458, , IB, , 1, , –, 0, , +, , IB, , 0, , RB, , VCE
Page 470 :
Rs /RL, swing (vce) and a drop in the gain of the system as demonstrated in the numerical, analysis above. It should be obvious from the intersection of the ac load line on the, vertical axis that the smaller the level of RL, the steeper the slope and the smaller the, ac voltage gain. Since RL is smaller for reduced levels of RL, it should be fairly clear, that:, For a particular design, the smaller the level of RL, the lower the level of ac, voltage gain., , 10.4 EFFECT OF THE SOURCE IMPEDANCE (RS), Our attention will now turn to the input side of the two-port system and the effect of, an internal source resistance on the gain of an amplifier. In Fig. 10.10, a source with, an internal resistance has been applied to the basic two-port system. The definitions, of Zi and AvNL are such that:, The parameters Zi and AvNL of a two-port system are unaffected by the internal resistance of the applied source., , Figure 10.10 Including the, effects of the source resistance Rs., , However:, The output impedance may be affected by the magnitude of Rs., Recall Eq. (8.110) for the complete hybrid equivalent model. The fraction of the, applied signal reaching the input terminals of the amplifier of Fig. 10.10 is determined, by the voltage-divider rule. That is,, RiVs, Vi , Ri Rs, , (10.8), , Equation (10.8) clearly shows that the larger the magnitude of Rs, the less the voltage at the input terminals of the amplifier. In general, therefore:, For a particular amplifier, the larger the internal resistance of a signal source, the less the overall gain of the system., For the two-port system of Fig. 10.10,, Vo Av Vi, NL, , and, , RiVs, Vi , Ri Rs, , so that, , Ri, Vo Av Vs, Ri Rs, , and, , Vo, Ri, Avs Av, Vs, Ri Rs, , NL, , NL, , (10.9), , 10.4 Effect of the Source Impedance (Rs), , 459
Page 471 :
Rs /RL, The result clearly supports the statement above regarding the reduction in gain with, increase in Rs. Using Eq. (10.9), if Rs 0 (ideal voltage source), Avs Av , which, is the maximum possible value., The input current is also altered by the presence of a source resistance as follows:, NL, , Vs, Ii , Rs Ri, , EXAMPLE 10.3, , (10.10), , In Fig. 10.11, a source with an internal resistance has been applied to the fixed-bias, transistor amplifier of Example 10.1 (Fig. 10.3)., (a) Determine the voltage gain Avs Vo /Vs. What percent of the applied signal appears at the input terminals of the amplifier?, (b) Determine the voltage gain Avs Vo /Vs using the re model., , Figure 10.11 Example 10.3., , Solution, (a) The two-port equivalent for the network appears in Fig. 10.12., Ro, , Rs, , +, , 0.5 kΩ, , Vs, , +, Vi, , –, , –, , +, Ri, , 1.071 kΩ, , –, , 3 kΩ, , +, , AυNLVi, −280.11Vi, , Vo, , –, , Figure 10.12 Substituting the, two-port equivalent network for, the fixed-bias transistor amplifier, of Fig. 10.11., , 1.071 k, Ri, Vo, Eq. (10.9): Avs AvNL (280.11), 1.071 k 0.5 k, Vs, Ri Rs, (0.6817)(280.11), 190.96, (1.071 k)Vs, RiVs, Eq. (10.8): Vi 0.6817Vs, 1.071 k 0.5 k, Ri Rs, or 68.2% of the available signal reached the amplifier and 31.8% was lost across the, internal resistance of the source., 460, , Chapter 10, , Systems Approach—Effects of Rs and RL
Page 472 :
Rs /RL, (b) Substituting the re model will result in the equivalent circuit of Fig. 10.13. Solving for Vo gives, Vo (100Ib)3 k, Vs, Vs, Zi re and Ib Ii , Rs re, 1.571 k, , with, and, , Vs, Vo 100 3 k, 1.571 k, , so that, , (100)(3 k), Vo, Avs , 1.57 k, Vs, , , , , , 190.96, as above., Ii, , Ib, , Rs, 500 Ω, , +, , +, , Vs, , RB, , 470 kΩ β re, , β Ib, 100 Ib, , 1.071 kΩ, , –, , 3 kΩ, , Vo, , –, , Figure 10.13 Substituting the re equivalent circuit for the fixed-bias transistor, amplifier of Fig. 10.11., , Throughout the analysis above, note that Rs was not included in the definition of, Zi for the two-port system. Of course, the resistance “seen” by the source is now Rs, Zi, but Rs remains a quantity associated only with the applied source., Note again in Example 10.3 that the same results were obtained with the systems, approach and using the re model. Certainly, if the two-port parameters are available,, they should be applied. If not, the approach to the solution is simply a matter of preference., , 10.5 COMBINED EFFECT OF Rs AND RL, The effects of Rs and RL have now been demonstrated on an individual basis. The, next natural question is how the presence of both factors in the same network will affect the total gain. In Fig. 10.14, a source with an internal resistance Rs and a load, RL have been applied to a two-port system for which the parameters Zi, Av , and Zo, have been specified. For the moment, let us assume that Zi and Zo are unaffected by, RL and Rs, respectively., NL, , Is, , +, Vs, , –, , Io, , Ii, Rs, , +, Vi, , –, , +, Ri, , +, , Ro, AυNLVi, , RL, , –, , Vo, , –, , Figure 10.14 Considering the effects of Rs and RL on the gain of an amplifier., , 10.5 Combined Effect of Rs and RL, , 461
Page 473 :
Rs /RL, At the input side we find, RiVs, Eq. (10.8): Vi , Ri Rs, Vi, Ri, , Vs, Ri Rs, , or, , (10.11), , and at the output side,, RLAv Vi, Vo , RL Ro, NL, , Vo, RLAV, Av , Vi, RL Ro, , or, , (10.12), , NL, , For the total gain Avs Vo /Vs, the following mathematical steps can be performed:, Vo, Vo Vi, Avs , Vs, Vi Vs, , (10.13), , and substituting Eqs. (10.11) and (10.12) will result in, RLAv, Ri, Avs , RL Ro Ri Rs, NL, , and, Vo, Ri, RL, Avs Av, Vs, Ri Rs RL Ro, , NL, , (10.14), , Since Ii Vi /Ri, as before,, Ri, Ai Av , RL, , (10.15), , Rs Ri, Ais Avs, RL, , (10.16), , or using Is Vs /(Rs Ri),, , However, Ii Is, so Eqs. (10.15) and (10.16) will generate the same result. Equation, (10.14) clearly reveals that both the source and the load resistance will reduce the, overall gain of the system. In fact:, The larger the source resistance and/or smaller the load resistance, the less, the overall gain of an amplifier., The two reduction factors of Eq. (10.14) form a product that has to be carefully, considered in any design procedure. It is not sufficient to ensure that Rs is relatively, small if the impact of the magnitude of RL is ignored. For instance, in Eq. (10.14), if, the first factor is 0.9 and the second factor is 0.2, the product of the two results in an, overall reduction factor equal to (0.9)(0.2) 0.18, which is close to the lower factor., The effect of the excellent 0.9 level was completely wiped out by the significantly, lower second multiplier. If both were 0.9-level factors, the net result would be, (0.9)(0.9) 0.81, which is still quite high. Even if the first were 0.9 and the second, 0.7, the net result of 0.63 would still be respectable. In general, therefore, for good, overall gain the effect of both Rs and RL must be evaluated individually and as a, product., 462, , Chapter 10, , Systems Approach—Effects of Rs and RL
Page 474 :
Rs /RL, For the single-stage amplifier of Fig. 10.15, with RL 4.7 k and Rs 0.3 k, determine:, (a) Avs., (b) Av Vo /Vi., (c) Ai., The two-port parameters for the fixed-bias configuration are Zi 1.071 k, Zo , 3 k, and AvNL 280.11., , EXAMPLE 10.4, , 12 V, , 3 kΩ, 470 kΩ, , +, , 0.3 kΩ, , Vs, , Vo, , 10 µF, , 20 µF, β = 100, , +, , Rs, , Zo, Vi, , RL, , 4.7 kΩ, , Zi, , –, , –, , Figure 10.15 Example 10.4, , Solution, Vo, Ri, RL, (a) Eq. (10.14): Avs Av NL, Vs, Ri Rs RL Ro, 1.071 k, 4.7 k, (280.11), , 1.071 k 0.3 k 4.7 k 3 k, (0.7812)(0.6104)(280.11), (0.4768)(280.11), 133.57, (4.7 k)(280.11), Vo, RLAvNL, (b) Av , 4.7 k 3 k, Vi, RL Ro, (0.6104)(280.11) 170.98, 1.071 k, Ri, (c) Ai Av (170.98) , 4.7 k, RL, 38.96, 1.071 k 0.3 k, Rs Ri, or Ais Avs (133.57) , 4.7 k, RL, 38.96, as above., , , , , , , , , , , , , , , , 10.6 BJT CE NETWORKS, The fixed-bias configuration has been employed throughout the analysis of the early, sections of this chapter to clearly show the effects of Rs and RL. In this section, various CE configurations are examined with a load and a source resistance. A detailed, analysis will not be performed for each configuration since they follow a very similar path to that demonstrated in the last few sections., , 10.6 BJT CE Networks, , 463
Page 476 :
Rs /RL, Zi, Avs Av, Zi Rs, , so that, , (10.18), , Since the load is connected to the collector terminal of the common-emitter configuration,, , and, , Zi re, , (10.19), , Zo RC, , (10.20), , as obtained earlier., , Voltage-Divider Bias, For the loaded voltage-divider bias configuration of Fig. 10.18, the load is again connected to the collector terminal and Zi remains, Zi Rre, , (R R1R2), , (10.21), , and for the system’s output impedance, Zo RC, , (10.22), , VCC, , RC, R1, , +, , Ib, , Rs, C1, , +, Vs, , –, , C2, , +, Vi, , Zo, , R2, , Zi, , RE, , RL Vo, , CE, , –, , –, Figure 10.18 Voltage-divider bias configuration with Rs and RL., , In the small-signal ac model, RC and RL will again be in parallel and, RC RL, Av , r, , (10.23), , Zi, Avs Av, Zi Rs, , (10.24), , e, , with, , CE Unbypassed Emitter Bias, For the common-emitter unbypassed emitter-bias configuration of Fig. 10.19, Zi remains independent of the applied load and, Zi RBRE, , (10.25), , 10.6 BJT CE Networks, , 465
Page 477 :
Rs /RL, VCC, , RC, RB, Rs, , Io, , +, , Ii, , +, , C1, , +, Vs, , Zo, , Vi, , RL Vo, , RE, , Zi, , –, , C2, , –, , –, , Figure 10.19 CE unbypassed emitter-bias configuration with Rs and RL., , For the output impedance,, Zo RC, , (10.26), , For the voltage gain, the resistance RC will again drop down in parallel with RL and, RC RL, Vo, Av , RE, Vi, , (10.27), , with, , Vo, Zi, Avs Av, Vs, Zi Rs, , (10.28), , and, , Io, Zi, Ai Av , Ii, RL, , (10.29), , but keep in mind that Ii Is Vs /(Rs Zi) Vi/Zi., , Collector Feedback, To keep with our connection of the load to the collector terminal the next configuration to be examined is the collector feedback configuration of Fig. 10.20. In the smallsignal ac model of the system, RC and RL will again drop down in parallel and, , VCC, RC, RF, , +, , C1, , Vs, , –, , C2, , Ii, , Rs, , +, Vi, , Zi, , Zo, , –, , Figure 10.20 Collector feedback configuration with Rs and RL., , 466, , Chapter 10, , +, , Io, , Systems Approach—Effects of Rs and RL, , RL, , Vo, , –
Page 478 :
Rs /RL, RC RL, Av , r, , (10.30), , Zi, Avs Av, Zi Rs, , (10.31), , Zo RC RF, , (10.32), , RF, Zi re, Av, , (10.33), , e, , with, The output impedance, , and, , The fact that Av [Eq. (10.30)] is a function of RL will alter the level of Zi from the, no-load value. Therefore, if the no-load model is available, the level of Zi must be, modified as demonstrated in the next example., The collector feedback amplifier of Fig. 10.21 has the following no-load system parameters: AvNL 238.94, Zo RCRF 2.66 k, and Zi 0.553 k, with re , 11.3 , and 200. Using the systems approach, determine:, (a) Av., (b) Avs., (c) Ai., 9V, , EXAMPLE 10.5, , 2.7 kΩ, Io, , 180 kΩ, , Vo, 0.6 kΩ, , Ii, , +, , +, , Vs, , Vi, , –, , –, , β = 200, 3.3 kΩ, , Figure 10.21 Example 10.5., , Solution, (a) For the two-port system:, 2.7 k3.3 k, RC RL, , , , Av , 11.3 , r, e, , 1.485 k, 131.42, 11.3 , with, , 180 k, RF, Zi re (200)(11.3 ), 131.42, Av, 2.26 k1.37 k, 0.853 k, 10.6 BJT CE Networks, , 467
Page 479 :
Rs /RL, The system approach will result in the configuration of Fig. 10.22 with the value of, Zi as controlled by RL and the voltage gain. Now the two-port gain equation can be, applied (slight difference in Av due to approximation Ib IRF in Section 8.7):, (3.3 k)(238.94), RLAvNL, Av 132.3, 3.3 k 2.66 k, RL Ro, Ii, , +, , +, , 0.6 kΩ, , +, , +, , Vi, , Vs, , Figure 10.22 The ac equivalent, circuit for the network of Fig., 10.21., , Io, , 2.66 kΩ, , −238.94Vi, , 0.853 kΩ, , –, , 3.3 kΩ, , Vo, , –, –, , –, , 0.853 k, Zi, (b) Avs Av (132.3), 0.853, k 0.6 k, Zi Rs, 77.67, , , , , , 0.853 k, (132.3)(0.853 k), Zi, (c) Ai Av (132.3) , 3.3, k, 3.3 k, RL, 34.2, or, , Zi Rs, 0.853 k 0.6 k, Ai Avs (77.67) , RL, 3.3 k, 34.2, , , , , , 10.7 BJT EMITTER-FOLLOWER, NETWORKS, The input and output impedance parameters of the two-port model for the emitterfollower network are sensitive to the applied load and source resistance. For the emitter-follower configuration of Fig. 10.23, the small-signal ac model would appear as, shown in Fig. 10.24. For the input section of Fig. 10.24, the resistance RB is neglected, because it is usually so much larger than the source resistance that a Thévenin equivVCC, , RB, Ii, , +, , Rs, , Vs, , Ib, C1, , +, , Zi, , Vi, , –, , Io, C2, RE, , –, Figure 10.23 Emitter-follower, configuraton with Rs and RL., , 468, , Chapter 10, , Systems Approach—Effects of Rs and RL, , +, RL Vo, , Zo, , –
Page 480 :
Rs /RL, b, , c, Ib, , +, , β re, , Rs, , Figure 10.24 Emitter-follower, configuration of Fig. 10.23, following the substitution of, the re equivalent circuit., , β Ib, , Vi, , +, , e, , Ie = (β + 1) Ib, , Vs, , where RE' = RE RL, , +, , RE' Vo, , –, , –, , –, , alent circuit for the configuration of Fig. 10.25 would result in simply Rs and Vs as, shown in Fig. 10.24. Of course, if current levels are to be determined such as Ii in the, original diagram, the effect of RB must be included., Applying Kirchhoff’s voltage law to the input circuit of Fig. 10.24 will result in, Vs Ib(Rs re ( 1)RE) 0, , so that, , Vs, Ib , Rs re ( 1)RE, , +, , RB, , Vs, , Vs IbRs Ibre ( 1)IbRE 0, and, , Rs, , –, Thévenin, , Figure 10.25 Determining the, Thévenin equivalent circuit for, the input circuit of Fig. 10.23., , Establishing Ie, we have, ( 1)Vs, Ie ( 1)Ib , Rs re ( 1)RE, Vs, Ie , [(Rs re)/( 1)] RE, , and, , Using 1 yields, Vs, Ie , (Rs / re) RE, , (10.34), , Drawing the network to “fit” Eq. (10.34) will result in the configuration of Fig., 10.26a. In Fig. 10.26b, RE and the load resistance RL have been separated to permit, a definition of Zo and Io., Rs, β, , Rs, , + re, , +, , β, , Ie, R' E, , Vs, , –, , +, Vo, , –, , + re, Io, , +, Vs, , Zo, RE, , –, , RL, , +, Vo, , –, (b), , (a), , Figure 10.26 Networks resulting from the application of Kirchhoff’s voltage law to the input circuit of Fig. 10.24., , The voltage gain can then be obtained directly from Fig. 10.26a using the voltage, divider rule:, REVs, Vo , RE (Rs / re), or, , RE, Vo, Avs , RE (Rs / re), Vs, 10.7 BJT Emitter-Follower Networks, , 469
Page 481 :
Rs /RL, RERL, Vo, Avs , R, R, Vs, E, L Rs/ re, , and, , (10.35), , Setting Vs 0 and solving for Zo will result in, , , , Rs, Zo RE re, , , , , (10.36), , For the input impedance,, Zb (re RE), Zi RBZb, , and, , Zi RB(re RE RL), , or, , (10.37), , For no-load conditions, the gain equation is, RE, AvNL , RE re, while for loaded conditions,, RE RL, Vo, Av , RE RL re, Vi, , EXAMPLE 10.6, , (10.38), , For the loaded emitter-follower configuration of Fig. 10.27 with a source resistance, and the no-load two-port parameters of Zi 157.54 k, Zo 21.6 , and AvNL , 0.993 with re 21.74 and 65, determine:, (a) The new values of Zi and Zo as determined by the load and Rs, respectively., (b) Av using the systems approach., (c) Avs using the systems approach., 15 V, (d) Ai Io /Ii., , 560 kΩ, Ii, 0.56 kΩ, , C1, , β = 65, C2, , +, , +, Vs, , –, , Vo, Zi, , Io, , Vi, 3.3 kΩ, , –, , Figure 10.27 Example 10.6., , Zo, , Solution, Eq. (10.37):, , Zi RB(re RE RL), , , , , , , , , 560 k65(21.74 3.3 k2.2 k), 560 k87.21 k, 75.46 k, versus 157.54 k (no-load)., 470, , Chapter 10, , Systems Approach—Effects of Rs and RL, , 1.32 k, , 2.2 kΩ
Page 482 :
Rs /RL, , , , Rs, Zo RE re, , , , , , , , , 0.56 k, 3.3 k , 21.74 , 65, 3.3 k30.36 , 30.08 , , versus 21.6 (no Rs)., (b) Substituting the two-port equivalent network will result in the small-signal ac, equivalent network of Fig. 10.28., (2.2 k)(0.993)Vi, RLAvNLVi, , Vo , 2.2 k 30.08 , RL Ro, 0.98Vi, Vo, with Av 0.98, Vi, Ii, , +, Vs, , –, , Io, , 30.08 Ω, 0.56 kΩ, , +, , +, , +, , Vi, , 0.993 Vi, , 75.46 kΩ, , –, , –, , Vo, , 2.2 kΩ, , –, , Figure 10.28 Small-signal ac equivalent circuit for the network of Fig. 10.27., , (75.46 k)Vs, ZiVs, (c) Vi 0.993Vs, 75.46 k 0.56 k, Zi Rs, Vo, Vo Vi, Avs (0.98)(0.993) 0.973, Vs, Vi Vs, , so that, Io, Zi, (d) Ai Av , Ii, RL, , , , 75.46 k, (0.98) , 2.2 k, , , , 33.61, , 10.8 BJT CB NETWORKS, A common-base amplifier with an applied load and source resistance appear in Fig., 10.29. The fact that the load is connected between the collector and base terminals, isolates it from the input circuit, and Zi remains essentially the same for no-load or, loaded conditions. The isolation that exists between input and output circuits also, maintains Zo at a fixed level even though the level of Rs may change. The voltage, gain is now determined by, 10.8 BJT CB Networks, , 471
Page 484 :
Rs /RL, Vo, Av 155.3, Vi, 5 k8.2 k, RCRL, 3.106 k, , , Av , 20, , re, 20 , , and, or, , 155.3, Vo, Vi Vo, (b) Avs , Vs, Vs Vi, 20 , Ri, Av (155.3), 20 200 , Ri Rs, 14.12, , , , , , Note the relatively low gain due to a source impedance much larger than the input, impedance of the amplifier., 20 , Zi, (c) Ai Av (155.3) , 8.2, k, RL, 0.379, , , , , , which is significantly less than 1 due to the division of output current between RC, and RL., , 10.9 FET NETWORKS, As noted in Chapter 9, the isolation that exists between gate and drain or source of, an FET amplifier ensures that changes in RL do not affect the level of Zi and changes, in Rsig do not affect Ro. In essence, therefore:, The no-load two-port model of Fig. 10.2 for an FET amplifier is unaffected by, an applied load or source resistance., , Bypassed Source Resistance, For the FET amplifier of Fig. 10.32, the applied load will appear in parallel with RD, in the small-signal model, resulting in the following equation for the loaded gain:, Av gm(RDRL), , (10.41), , VDD, RD, , +, , C2, C1, , Vs, Zi, , Vi, , Zo, RG, RS, , RL V, o, , CS, , –, , Rsig, , +, , +, –, , –, Figure 10.32 JFET amplifier with Rsig and RL., , 10.9 FET Networks, , 473
Page 487 :
Rs /RL, The loaded voltage gain has the same format as the unloaded gain with RS replaced, by the parallel combination of RS and RL., gm(RS RL), Vo, Av , 1, , gm(RS RL), Vi, , (10.48), , The level of output impedance is as determined in Chapter 9:, 1, Zo RS , gm, , (10.49), , revealing an insensitivity to the magnitude of the source resistance Rsig., , Common Gate, Even though the common-gate configuration of Fig. 10.37 is somewhat different from, those described above with regard to the placement of RL and Rsig, the input and output circuits remain isolated and, RS, Zi , 1 gmRS, , (10.50), , Zo RD, , (10.51), , Av gm(RDRL), , (10.52), , The loaded voltage gain is given by, , VDD, RD, , +, , C2, , Rsig, , +, Vs, , –, , C1, Zi, , Zo, , +, Vi, , RL, , Vo, , RS, , –, , –, , Figure 10.37 Common-gate configuration with Rsig and RL., , 10.10 SUMMARY TABLE, Now that the loaded and unloaded (Chapters 8 and 9) BJT and JFET amplifiers have, been examined in some detail, a review of the equations developed is provided by, Table 10.1. Although all the equations are for the loaded situation, the removal of RL, will result in the equations for the unloaded amplifier. The same is true for the effect, of Rs (for BJTs) and Rsig (for JFETs) on Zo. In each case, the phase relationship between the input and output voltages is also provided for quick reference. A review of, 476, , Chapter 10, , Systems Approach—Effects of Rs and RL
Page 491 :
Rs /RL, , 10.11 CASCADED SYSTEMS, The two-port systems approach is particularly useful for cascaded systems such as, that appearing in Fig. 10.38, where Av1, Av2, Av3, and so on, are the voltage gains of, each stage under loaded conditions. That is, Av1 is determined with the input impedance to Av2 acting as the load on Av1. For Av2, Av1 will determine the signal strength, and source impedance at the input to Av2. The total gain of the system is then determined by the product of the individual gains as follows:, AvT Av1 Av2 Av3, , (10.53), , Zi1, AiT AvT, RL, , (10.54), , and the total current gain by, , No matter how perfect the system design, the application of a load to a two-port, system will affect the voltage gain. Therefore, there is no possibility of a situation, where Av1, Av2, and so on, of Fig. 10.38 are simply the no-load values. The loading, of each succeeding stage must be considered. The no-load parameters can be used to, determine the loaded gains of Fig. 10.38, but Eq. (10.53) requires the loaded values., Vo = Vi, 1, , Vo = Vi, 2, , 2, , 3, , +, , +, , Aυ, , Vi, , Aυ, , 1, , Aυ, , 2, , A υn, , 3, , RL Vo, , –, , –, Zi = Zi, , 1, , Zo, , 1, , Zi, , 2, , Zo, , 2, , Zi, , 3, , Zo, , 3, , Z in, , Zon = Zo, , Figure 10.38 Cascaded system., , EXAMPLE 10.9, , The two-stage system of Fig. 10.39 employed a transistor emitter-follower configuration prior to a common-base configuration to ensure that the maximum percent of, the applied signal appears at the input terminals of the common-base amplifier. In, Fig. 10.39, the no-load values are provided for each system, with the exception of Zi, and Zo for the emitter-follower, which are the loaded values. For the configuration of, Fig. 10.39, determine:, (a) The loaded gain for each stage., (b) The total gain for the system, Av and Avs., (c) The total current gain for the system., (d) The total gain for the system if the emitter-follower configuration were removed., , Figure 10.39 Example 10.9., , 480, , Chapter 10, , Systems Approach—Effects of Rs and RL
Page 492 :
Rs /RL, Solution, (a) For the emitter-follower configuration, the loaded gain is, (26 )(1)Vi1, Zi2 AvNLVi1, Vo1 , 26, 12 0.684Vi1, Zi2 Zo1, Vo1, Av 0.684, Vi1, , and, , 1, , For the common-base configuration,, (8.2 k)(240)Vi2, RLAvNLVi2, Vo2 , 8.2 k 5.1 k 147.97Vi2, RL Ro2, Vo2, AvL 147.97, Vi2, , and, (b) AvT Av1Av2, , (0.684)(147.97), 101.20, (10 k)(101.20), Zi1, Avs AvT , 10 k 1 k, Zi1 Rs, 92, 10 k, Zi1, (c) AiT AvT, (101.20) , 8.2, k, RL, 123.41, (26 )Vs, ZiCBVs, (d) ViCB 0.025Vs, 26 1 k, ZiCB Rs, , , , Vi, and 0.025, Vs, , with, , , , Vo, 147.97, Vi, , from above, , Vi Vo, and Avs (0.025)(147.97) 3.7, Vs Vi, In total, therefore, the gain is about 25 times greater with the emitter-follower configuration to draw the signal to the amplifier stages. Take note, however, that it was, also important that the output impedance of the first stage was relatively close to the, input impedance of the second stage or the signal would have been “lost” again by, the voltage-divider action., , 10.12 PSPICE WINDOWS, Loaded Voltage-Divider BJT Transistor Configuration, The computer analysis of this section includes a PSpice Windows evaluation of the, response of a loaded BJT and FET amplifier with a source resistance. The BJT network of Fig. 10.40 employs the same unloaded configuration examined in the PSpice, analysis of Chapter 8, where the unloaded gain was 369 (Example 8.2, re 18.44 )., For the transistor, all the parameters listed under Model Editor were removed except, Is and beta, which were set to 2E-15A and 90, respectively. In this way, the results, 10.12 PSpice Windows, , 481
Page 493 :
Rs /RL, will be as close to the hand-written solutions as possible without going to the controlled source equivalents. Note the placement of the VPRINT1 option to pick up the, voltage lost across the source resistance and to note if there is any drop in gain across, the capacitor. The option Do not auto-run Probe was chosen, and under Analysis, Setup, the AC Sweep was set at a fixed frequency of 10 kHz. In addition, Display, Results on Schematic under Analysis was chosen and the Voltage Display enabled., , Figure 10.40 Loaded, voltage-divider BJT transistor, configuration., , An Analysis resulted in the dc levels appearing in Fig. 10.40. In particular, note, the zero volt levels at the left side of C1 and the right side of C2. In addition, note, that VBE is essentially 0.7 V and the dc levels of each terminal of the transistor are, very close to those calculated in Example 8.2 (using the approximate approach). Reviewing the output file following Analysis-Examine Output will result in the data, listings of Fig. 10.41. The nodes are defined in the Schematics Netlist, and the BJT, MODEL PARAMETERS reveal our choices for this run—although the last three, are default values. The SMALL-SIGNAL BIAS SOLUTION simply confirms the, levels printed on the schematic, and the Operating Point Information reveals that, beta (dc and ac) is 90, that VBE is 0.7 V, that IC is 1.32 mA, and that IB is 14.7 A, (in addition to a host of other levels). The AC ANALYSIS reveals that the voltage, on the other side of Rsig is about 0.7 mV, resulting in a drop of about 0.3 mV (30%, loss in signal voltage) of the applied signal across Rsig. The remaining two ac levels, are the same, revealing that the capacitor is an effective short circuit for ac. The loaded, gain from source to output is 144.9. The gain from the base of the transistor to the, output is 144.9 mV/0.7 mV 207. Both levels are certainly significantly less than, the no-load level of 369. If we return to the network and change RL to 10 M, the, output voltage will rise to 243.3 mV, resulting in a gain of 243.3 mV/0.7 mV 347.57,, which is quite close to the hand-calculated, approximate level of 369., For interest’s sake, let us now calculate the loaded voltage gain and compare to, the PSpice solution of 144.9., re 18.44 , and, , Zi R1R2re, 56 k8.2 k(90)(18.44 ), 1.35 k, (1.35 k)Vs, ZiVs, Vi , 1.35, k 0.6 k 0.69Vs, Zi Rs, , and, 482, , Chapter 10, , Vi, 0.69, Vs, Systems Approach—Effects of Rs and RL
Page 494 :
Rs /RL, , Figure 10.41 Output file for, the network of Fig. 10.40., , 483
Page 495 :
Rs /RL, (10 k)(350.4), Vo, RLAvNL, Av , 10 k 6.8 k, Vi, RL Ro, 208.57, with, , Vi Vo, Avs (0.69)(208.57), Vs Vi, 144, , which is an excellent comparison with the computer solution., , Loaded JFET Self-Bias Transistor Configuration, The network of Fig. 10.42 is a loaded version of the network examined in Chapter 9,, which resulted in a no-load gain of 13.3. In the Model Editor dialog box, Beta was, set to 0.625mA/V2 and Vto 4V. The remaining parameters were left alone to permit a close comparison with the Chapter 9 solution and because they have less effect, on the response than for a BJT transistor., Again, note the effectiveness of the capacitors to block the dc voltages. In addition, note the small voltage at the gate, indicating that the input impedance to the de-, , Figure 10.42 Loaded self-bias, JFET transistor configuration., , vice is in reality not infinite (although for all practical purposes it is an excellent assumption.) Again, the frequency was set to 10 kHz and an Analysis called for without the Probe option. The sequence Analysis-Examine Output will result in the listing of Fig. 10.43. The Schematics Netlist provides a listing of assigned nodes, and, the OPERATING POINT INFORMATION reveals that the drain current is 3.36, mA, that VGS is 1.71 V, and that gm is 2.94 mS. The AC ANALYSIS reveals that, there is negligible drop across either capacitor at this frequency, and the short-circuit, equivalency can be assumed. The output voltage is 5.597mV resulting in a loaded, gain of 5.597 compared to the unloaded gain of 13.3. Note also that the drop across, Rsig is negligible due to the high input impedance of the device., Using the value of gm hand-calculated earlier, the equation for the loaded gain, will result in a gain of 5.62 as shown below—an excellent comparison with the computer solution., Av gm(RDRL), (2.90 mS)(4.7 k3.3 k), 5.62, The results obtained above have clearly substantiated the analysis and equations, presented in this chapter for a loaded amplifier., 484, , Chapter 10, , Systems Approach—Effects of Rs and RL
Page 496 :
Rs /RL, , Figure 10.43 Output file for, the network of Fig. 10.42.
Page 497 :
Rs /RL, PROBLEMS, , § 10.3 Effect of a Load Impedance (RL), 1. For the fixed-bias configuration of Fig. 10.44:, (a) Determine AvNL, Zi, and Zo., (b) Sketch the two-port model of Fig. 10.2 with the parameters determined in part (a) in place., (c) Calculate the gain Av using the model of part (b) and Eq. (10.3)., (d) Determine the current gain using Eq. (10.6)., (e) Determine Av, Zi, and Zo using the re model and compare with the solutions above., , 18 V, , 3.3 kΩ, 680 kΩ, 1.8 µF, Vi, Ii, , 1.8 µF, , Io, Vo, , β = 100, Zo, , RL, , 4.7 kΩ, , Zi, , Figure 10.44 Problems 1, 2, and 3, , * 2. (a) Draw the dc and ac load lines for the network of Fig. 10.44 on the characteristics of Fig., 10.45., (b) Determine the peak-to-peak value of Ic and Vce from the graph if Vi has a peak value of, 10 mV. Determine the voltage gain Av Vo/Vi and compare with the solution obtained in, Problem 1., , Figure 10.45 Problems 2 and 7, , 486, , Chapter 10, , Systems Approach—Effects of Rs and RL
Page 498 :
Rs /RL, 3. (a) Determine the voltage gain Av for the network of Fig. 10.44 for RL 4.7, 2.2, and 0.5 k., What is the effect of decreasing levels of RL on the voltage gain?, (b) How will Zi, Zo, and AvNL change with decreasing values of RL?, , § 10.4 Effect of a Source Impedance (Rs), * 4. For, (a), (b), (c), (d), (e), (f), (g), (h), , the network of Fig. 10.46:, Determine AvNL, Zi, and Zo., Sketch the two-port model of Fig. 10.2 with the parameters determined in part (a) in place., Determine Av using the results of part (b)., Determine Avs., Determine Avs using the re model and compare the results to that obtained in part (d)., Change Rs to 1 k and determine Av. How does Av change with the level of Rs?, Change Rs to 1 k and determine Avs. How does Avs change with the level of Rs?, Change Rs to 1 k and determine AvNL, Zi, and Zo. How do they change with change in Rs?, 12 V, , 3 kΩ, 1 MΩ, , Rs, , 1 µF, , 1 µF, Vo, , Vi, , β = 180, , 0.6 kΩ, , +, , Zo, , Vs, , Zi, , –, Figure 10.46 Problem 4, , § 10.5 Combined Effect of Rs and RL, * 5. For the network of Fig. 10.47:, (a) Determine AvNL, Zi, and Zo., (b) Sketch the two-port model of Fig. 10.2 with the parameters determined in part (a) in place., (c) Determine Av and Avs., (d) Calculate Ai., (e) Change RL to 5.6 k and calculate Avs. What is the effect of increasing levels of RL on the, gain?, (f) Change Rs to 0.5 k (with RL at 2.7 k) and comment on the effect of reducing Rs on Avs., (g) Change RL to 5.6 k and Rs to 0.5 k and determine the new levels of Zi and Zo. How are, the impedance parameters affected by changing levels of RL and Rs?, 24 V, , 4.3 kΩ, 560 kΩ, Ii, , +, , Rs, , 10 µF, , Io, Vo, , Vi, , β = 80, , 1 kΩ, Zo, , Vs, , –, , 10 µ F, , RL, , 2.7 kΩ, , Zi, , Figure 10.47 Problems 5 and 17, , Problems, , 487
Page 499 :
Rs /RL, § 10.6 BJT CE Networks, 6. For the voltage-divider configuration of Fig. 10.48:, (a) Determine AvNL, Zi, and Zo., (b) Sketch the two-port model of Fig. 10.2 with the parameters determined in part (a) in place., (c) Calculate the gain Av using the model of part (b)., (d) Determine the current gain Ai., (e) Determine Av, Zi, and Zo using the re model and compare solutions., , Figure 10.48 Problems 6, 7, and 8, , * 7. (a) Draw the dc and ac load lines for the network of Fig. 10.48 on the characteristics of Fig., 10.45., (b) Determine the peak-to-peak value of Ic and Vce from the graph if Vi has a peak value of 10, mV. Determine the voltage gain Av Vo /Vi and compare the solution with that obtained in, Problem 6., 8. (a) Determine the voltage gain Av for the network of Fig. 10.48 with RL 4.7, 2.2, and 0.5, k. What is the effect of decreasing levels of RL on the voltage gain?, (b) How will Zi, Zo, and AvNL change with decreasing levels of RL?, 9. For the emitter-stabilized network of Fig. 10.49:, (a) Determine AvNL, Zi, and Zo., (b) Sketch the two-port model of Fig. 10.2 with the values determined in part (a)., (c) Determine Av and Avs., (d) Change Rs to 1 k. What is the effect on AvNL, Zi, and Zo?, (e) Change Rs to 1 k and determine Av and Avs. What is the effect of increasing levels of Rs, on Av and Avs?, , Figure 10.49 Problem 9, , 488, , Chapter 10, , Systems Approach—Effects of Rs and RL
Page 500 :
Rs /RL, § 10.7 BJT Emitter-Follower Networks, * 10. For the network of Fig. 10.50:, (a) Determine AvNL, Zi, and Zo., (b) Sketch the two-port model of Fig. 10.2 with the values determined in part (a)., (c) Determine Av and Avs., (d) Change Rs to 1 k and determine Av and Avs. What is the effect of increasing levels of Rs, on the voltage gains?, (e) Change Rs to 1 k and determine AvNL, Zi, and Zo. What is the effect of increasing levels, of Rs on the parameters?, (f) Change RL to 5.6 k and determine Av and Avs. What is the effect of increasing levels of, RL on the voltage gains? Maintain Rs at its original level of 0.6 k., , Figure 10.50 Problems 10 and 18, , § 10.8 BJT CB Networks, * 11. For the common-base network of Fig. 10.51:, (a) Determine Zi, Zo, and AvNL., (b) Sketch the two-port model of Fig. 10.2 with the parameters of part (a) in place., (c) Determine Av and Avs., (d) Determine Av and Avs using the re model and compare with the results of part (c)., (e) Change Rs to 0.5 k and RL to 2.2 k and calculate Av and Avs. What is the effect of changing levels of Rs and RL on the voltage gains?, (f) Determine Zo if Rs changed to 0.5 k with all other parameters as appearing in Fig. 10.51., How is Zo affected by changing levels of Rs?, (g) Determine Zi if RL is reduced to 2.2 k. What is the effect of changing levels of RL on the, input impedance?, , Figure 10.51 Problems 11 and 19, , Problems, , 489
Page 501 :
Rs /RL, § 10.9 FET Networks, 12. For the self-bias JFET network of Fig. 10.52:, (a) Determine AvNL, Zi, and Zo., (b) Sketch the two-port model of Fig. 10.2 with the parameters determined in part (a) in place., (c) Determine Av and Avs., (d) Change RL to 6.8 k and Rsig to 1 k and calculate the new levels of Av and Avs. How are, the voltage gains affected by changes in Rsig and RL?, (e) For the same changes as part (d), determine Zi and Zo. What was the impact on both impedances?, , 12 V, , 2.7 kΩ, 10 µ F, Vo, Rsig, , Vi, , 0.6 kΩ, , IDSS = 10 mA, VP = − 6 V, , 10 µF, , +, , Zo, , Vs, , 1 MΩ, , Zi, , 0.51 kΩ, , RL, , 4.7 kΩ, , 20 µF, , –, Figure 10.52 Problems 12 and 20, , 13. For the source-follower network of Fig. 10.53:, (a) Determine AvNL, Zi, and Zo., (b) Sketch the two-port model of Fig. 10.2 with the parameters determined in part (a) in place., (c) Determine Av and Avs., (d) Change RL to 4.7 k and calculate Av and Avs. What was the effect of increasing levels of, RL on both voltage gains?, (e) Change Rsig to 1 k (with RL at 2.2 k) and calculate Av and Avs. What was the effect of, increasing levels of Rsig on both voltage gains?, (f) Change RL to 4.7 k and Rsig to 1 k and calculate Zi and Zo. What was the effect on both, parameters?, , 12 V, , 8.2 µF, , Rsig, , +, , IDSS = 6 mA, VP = − 6 V, , Vi, , 0.5 kΩ, , Vo, , Vs, , 2 MΩ, Zi, , 8.2 µF, 3.3 kΩ, , Zo, , –, , Figure 10.53 Problem 13, , 490, , Chapter 10, , Systems Approach—Effects of Rs and RL, , 2.2 kΩ
Page 502 :
Rs /RL, * 14. For the common-gate configuration of Fig. 10.54:, (a) Determine AvNL, Zi, and Zo., (b) Sketch the two-port model of Fig. 10.2 with the parameters determined in part (a) in place., (c) Determine Av and Avs., (d) Change RL to 2.2 k and calculate Av and Avs. What was the effect of changing RL on the, voltage gains?, (e) Change Rsig to 0.5 k (with RL at 4.7 k) and calculate Av and Avs. What was the effect, of changing Rsig on the voltage gains?, (f) Change RL to 2.2 k and Rsig to 0.5 k and calculate Zi and Zo. What was the effect on, both parameters?, , 18 V, , 3.3 kΩ, 5.6 µF, Vo, IDSS = 5 mA, VP = − 4 V, 5.6 µ F, , Rsig, , +, , Zo, , Vi, , 4.7 kΩ, , 1 kΩ, , Vs, , 1.2 kΩ, , Zi, , –, , Figure 10.54 Problem 14, , § 10.11 Cascaded Systems, * 15. For the cascaded system of Fig. 10.55 with two identical stages, determine:, (a) The loaded voltage gain of each stage., (b) The total gain of the system, Av and Avs., (c) The loaded current gain of each stage., (d) The total current gain of the system., (e) How Zi is affected by the second stage and RL., (f) How Zo is affected by the first stage and Rs., (g) The phase relationship between Vo and Vi., , Rs, , +, , 1 µF V, i, , 1 µF, CE amplifier, , 0.6 kΩ, , Vs, Zi, , Vo, , CE amplifier, , Zi = 1 kΩ, , Zi = 1 kΩ, , Zo = 3.3 kΩ, , Zo = 3.3 kΩ, , Aυ NL = – 420, , Aυ NL = – 420, , –, , Zo, , 1, , Zo, , RL, , 2.7 kΩ, , Zi, , 2, , Figure 10.55 Problem 15, , Problems, , 491
Page 503 :
Rs /RL, * 16. For the cascaded system of Fig. 10.56, determine:, (a) The loaded voltage gain of each stage., (b) The total gain of the system, Av and Avs., (c) The loaded current gain of each stage., (d) The total current gain of the system., (e) How Zi is affected by the second stage and RL., (f) How Zo is affected by the first stage and Rs., (g) The phase relationship between Vo and Vi., Rs, , +, , 10 µF, , Vi, Emitter - follower, , 1 kΩ 10 µF, , Vs, Zi, , Vo, , CE amplifier, , Zi = 50 kΩ, , Z i = 1.2 kΩ, , Zo = 20 Ω, Aυ ≅ 1, , Zo = 4.6 kΩ, Aυ NL = – 640, , –, , NL, , Zo, , 1, , RL, , 2.2 kΩ, , Zo, , Zi, , 2, , Figure 10.56 Problem 16, , § 10.12 PSpice Windows, 17. Using PSpice Windows, determine the level of Vo for Vs 1 mV for the network of Fig. 10.47., For the capacitive elements assume a frequency of 1 kHz., 18. Repeat Problem 17 for the network of Fig. 10.50 and compare the results with those of Problem 10., 19. Repeat Problem 17 for the network of Fig. 10.51 and compare with the results of Problem 11., 20. Repeat Problem 17 for the network of Fig. 10.52 and compare with the results of Problem 12., *Please Note: Asterisks indicate more difficult problems., , 492, , Chapter 10, , Systems Approach—Effects of Rs and RL
Page 504 :
f, CHAPTER, , BJT and JFET, Frequency Response, , 11, , 11.1 INTRODUCTION, The analysis thus far has been limited to a particular frequency. For the amplifier, it, was a frequency that normally permitted ignoring the effects of the capacitive elements, reducing the analysis to one that included only resistive elements and sources, of the independent and controlled variety. We will now investigate the frequency, effects introduced by the larger capacitive elements of the network at low frequencies and the smaller capacitive elements of the active device at the high frequencies., Since the analysis will extend through a wide frequency range, the logarithmic scale, will be defined and used throughout the analysis. In addition, since industry typically, uses a decibel scale on its frequency plots, the concept of the decibel is introduced, in some detail. The similarities between the frequency response analyses of both BJTs, and FETs permit a coverage of each in the same chapter., , 11.2 LOGARITHMS, There is no escaping the need to become comfortable with the logarithmic function., The plotting of a variable between wide limits, comparing levels without unwieldy, numbers, and identifying levels of particular importance in the design, review, and, analysis procedures are all positive features of using the logarithmic function., As a first step in clarifying the relationship between the variables of a logarithmic function, consider the following mathematical equations:, a bx,, , x logb a, , (11.1), , The variables a, b, and x are the same in each equation. If a is determined by taking the base b to the x power, the same x will result if the log of a is taken to the base, b. For instance, if b 10 and x 2,, a bx (10)2 100, but, , x logb a log10 100 2, , In other words, if you were asked to find the power of a number that would result in, a particular level such as shown below:, 10,000 10x, , 493
Page 505 :
f, the level of x could be determined using logarithms. That is,, x log10 10,000 4, For the electrical/electronics industry and in fact for the vast majority of scientific research, the base in the logarithmic equation is limited to 10 and the number e , 2.71828. . . ., Logarithms taken to the base 10 are referred to as common logarithms, while, logarithms taken to the base e are referred to as natural logarithms. In summary:, Common logarithm: x log10 a, , (11.2), , Natural logarithm: y loge a, , (11.3), , loge a 2.3 log10 a, , (11.4), , The two are related by, , On today’s scientific calculators, the common logarithm is typically denoted by the, key and the natural logarithm by the, key., , EXAMPLE 11.1, , Using the calculator, determine the logarithm of the following numbers to the base, indicated., (a) log10 106., (b) loge e3., (c) log10 102., (d) loge e1., , Solution, (a) 6, , (b) 3, , (c) 2, , (d) 1, , The results in Example 11.1 clearly reveal that the logarithm of a number taken, to a power is simply the power of the number if the number matches the base of the, logarithm. In the next example, the base and the variable x are not related by an integer power of the base., , EXAMPLE 11.2, , Using the calculator, determine the logarithm of the following numbers., (a) log10 64., (b) loge 64., (c) log10 1600., (d) log10 8000., , Solution, (a) 1.806, , (b) 4.159, , (c) 3.204, , (d) 3.903, , Note in parts (a) and (b) of Example 11.2 that the logarithms log10 a and loge a, are indeed related as defined by Eq. (11.4). In addition, note that the logarithm of a, number does not increase in the same linear fashion as the number. That is, 8000 is, 125 times larger than 64, but the logarithm of 8000 is only about 2.16 times larger, 494, , Chapter 11, , BJT and JFET Frequency Response
Page 506 :
f, than the magnitude of the logarithm of 64, revealing a very nonlinear relationship. In, fact, Table 11.1 clearly shows how the logarithm of a number increases only as the, exponent of the number. If the antilogarithm of a number is desired, the 10x or ex calculator functions are employed., TABLE 11.1, log10 100, log10 10, log10 100, log10 1,000, log10 10,000, log10 100,000, log10 1,000,000, log10 10,000,000, log10 100,000,000, and so on, , 0, 1, 2, 3, 4, 5, 6, 7, 8, , EXAMPLE 11.3, , Using a calculator, determine the antilogarithm of the following expressions:, (a) 1.6 log10 a., (b) 0.04 loge a., , Solution, (a) a 101.6, Calculator keys:, and a 39.81, (b) a e0.04, Calculator keys:, and a 1.0408, , Since the remaining analysis of this chapter employs the common logarithm, let, us now review a few properties of logarithms using solely the common logarithm. In, general, however, the same relationships hold true for logarithms to any base., log10 1 0, , (11.5), , As clearly revealed by Table 11.1, since 100 1,, a, log10 log10 a log10 b, b, , (11.6), , which for the special case of a 1 becomes, 1, log10 log10 b, b, , (11.7), , revealing that for any b greater than 1 the logarithm of a number less than 1 is always negative., log10 ab log10 a log10 b, , (11.8), , In each case, the equations employing natural logarithms will have the same format., 11.2 Logarithms, , 495
Page 507 :
f, EXAMPLE 11.4, , Using a calculator, determine the logarithm of the following numbers:, (a) log10 0.5., 4000, (b) log10 ., 250, (c) log10 (0.6 30)., , Solution, (a) 0.3, (b) log10 4000 log10 250 3.602 2.398 1.204, 4000, Check: log10 log10 16 1.204, 250, (c) log10 0.6 log10 30 0.2218 1.477 1.255, Check: log10 (0.6 30) log10 18 1.255, The use of log scales can significantly expand the range of variation of a particular variable on a graph. Most graph paper available is of the semilog or double-log, (log-log) variety. The term semi (meaning one-half) indicates that only one of the two, scales is a log scale, whereas double-log indicates that both scales are log scales. A, semilog scale appears in Fig. 11.1. Note that the vertical scale is a linear scale with, equal divisions. The spacing between the lines of the log plot is shown on the graph., , Figure 11.1 Semilog graph paper., , 496, , Chapter 11 BJT and JFET Frequency Response
Page 508 :
The log of 2 to the base 10 is approximately 0.3. The distance from 1 (log10 1 0), to 2 is therefore 30% of the span. The log of 3 to the base 10 is 0.4771 or almost, 48% of the span (very close to one-half the distance between power of 10 increments, on the log scale). Since log10 5 0.7, it is marked off at a point 70% of the distance., Note that between any two digits the same compression of the lines appears as you, progress from the left to the right. It is important to note the resulting numerical value, and the spacing, since plots will typically only have the tic marks indicated in Fig., 11.2 due to a lack of space. You must realize that the longer bars for this figure have, the numerical values of 0.3, 3, and 30 associated with them, whereas the next shorter, bars have values of 0.5, 5, and 50 and the shortest bars 0.7, 7, and 70., , (3), , about halfway (0.3), , 0.1, , 0.7, , (5) (7), , (30) (50) (70), , 10, , 1, , f, , 100, , log, , almost three-fourths (0.5), , Figure 11.2, , Identifying the numerical values of the tic marks on a log scale., , Be aware that plotting a function on a log scale can change the general appearance of the waveform as compared to a plot on a linear scale. A straight-line plot on, a linear scale can develop a curve on a log scale, and a nonlinear plot on a linear scale, can take on the appearance of a straight line on a log plot. The important point is that, the results extracted at each level be correctly labeled by developing a familiarity with, the spacing of Figs. 11.1 and 11.2. This is particularly true for some of the log-log, plots that appear later in the book., , 11.3 DECIBELS, The concept of the decibel (dB) and the associated calculations will become increasingly important in the remaining sections of this chapter. The background surrounding the term decibel has its origin in the established fact that power and audio levels, are related on a logarithmic basis. That is, an increase in power level, say 4 to 16 W,, does not result in an audio level increase by a factor of 16/4 4. It will increase by, a factor of 2 as derived from the power of 4 in the following manner: (4)2 16. For, a change of 4 to 64 W, the audio level will increase by a factor of 3 since (4)3 64., In logarithmic form, the relationship can be written as log4 64 3., The term bel was derived from the surname of Alexander Graham Bell. For standardization, the bel (B) was defined by the following equation to relate power levels, P1 and P2:, P2, G log10 , P1, , bel, , (11.9), , 11.3 Decibels, , 497
Page 509 :
f, It was found, however, that the bel was too large a unit of measurement for practical purposes, so the decibel (dB) was defined such that 10 decibels 1 bel., Therefore,, P2, GdB 10 log10 , P1, , dB, , (11.10), , The terminal rating of electronic communication equipment (amplifiers, microphones, etc.) is commonly rated in decibels. Equation (11.10) indicates clearly, however, that the decibel rating is a measure of the difference in magnitude between two, power levels. For a specified terminal (output) power (P2) there must be a reference, power level (P1). The reference level is generally accepted to be 1 mW, although on, occasion, the 6-mW standard of earlier years is applied. The resistance to be associated with the 1-mW power level is 600 , chosen because it is the characteristic impedance of audio transmission lines. When the 1-mW level is employed as the reference level, the decibel symbol frequently appears as dBm. In equation form,, , , , P2, GdBm 10 log10 , 1 mW 600 , , dBm, , (11.11), , There exists a second equation for decibels that is applied frequently. It can be, best described through the system of Fig. 11.3. For Vi equal to some value V1, P1 , V 12/Ri, where Ri , is the input resistance of the system of Fig. 11.3. If Vi should be increased (or decreased) to some other level, V2, then P2 V22/Ri. If we substitute into, Eq. (11.10) to determine the resulting difference in decibels between the power, levels,, P2, V 22/Ri, V2, GdB 10 log10 10 log10 2 10 log10 , P1, V1, V 1/Ri, , , , and, , V2, GdB 20 log10 , V1, , dB, , 2, , (11.12), , Figure 11.3 Configuration employed in the discussion of Eq. (11.12)., , Frequently, the effect of different impedances (R1 R2) is ignored and Eq. (11.12), applied simply to establish a basis of comparison between levels—voltage or current., For situations of this type, the decibel gain should more correctly be referred to as, the voltage or current gain in decibels to differentiate it from the common usage of, decibel as applied to power levels., One of the advantages of the logarithmic relationship is the manner in which it, can be applied to cascaded stages. For example, the magnitude of the overall voltage, gain of a cascaded system is given by, (11.13), Av Av Av Av …Av , T, , 498, , Chapter 11, , 1, , 2, , BJT and JFET Frequency Response, , 3, , n
Page 510 :
f, Applying the proper logarithmic relationship results in, , TABLE 11.2, , Gv 20 log10 AvT 20 log10 Av1 20 log10 Av2, 20 log10 Av3 , , Voltage Gain,, , 20 log10 Avn, , (dB), , (11.14), , In words, the equation states that the decibel gain of a cascaded system is simply the, sum of the decibel gains of each stage, that is,, Gv Gv1 Gv2 Gv3 , , Gvn, , dB, , (11.15), , In an effort to develop some association between dB levels and voltage gains,, Table 11.2 was developed. First note that a gain of 2 results in a dB level of 6 dB, while a drop to 12 results in a 6-dB level. A change in Vo /Vi from 1 to 10, 10 to 100,, or 100 to 1000 results in the same 20-dB change in level. When Vo Vi, Vo /Vi 1, and the dB level is 0. At a very high gain of 1000, the dB level is 60, while at the, much higher gain of 10,000, the dB level is 80 dB, an increase of only 20 dB—a result of the logarithmic relationship. Table 11.2 clearly reveals that voltage gains of, 50 dB or higher should immediately be recognized as being quite high., , Vo /Vi, , dB Level, , 0.5, 0.707, 1, 2, 10, 40, 100, 1000, 10,000, etc., , 6, 3, 0, 6, 20, 32, 40, 60, 80, , EXAMPLE 11.5, , Find the magnitude gain corresponding to a decibel gain of 100., , Solution, By Eq. (11.10),, P2, P2, GdB 10 log10 100 dB → log10 10, P1, P1, so that, P2, 1010 10,000,000,000, P1, This example clearly demonstrates the range of decibel values to be expected from, practical devices. Certainly, a future calculation giving a decibel result in the neighborhood of 100 should be questioned immediately., The input power to a device is 10,000 W at a voltage of 1000 V. The output power, is 500 W, while the output impedance is 20 ., (a) Find the power gain in decibels., (b) Find the voltage gain in decibels., (c) Explain why parts (a) and (b) agree or disagree., , EXAMPLE 11.6, , Solution, Po, 500 W, 1, (a) GdB 10 log10 10 log10 10 log10 10 log10 20, Pi, 10 kW, 20, 10(1.301) 13.01 dB, Vo, P, R, , (5, 00, , W2, )(0), (b) Gv 20 log10 20 log10 20 log10 , Vi, 1000, 1000 V, 100, 1, 20 log10 20 log10 20 log10 10 20 dB, 1000, 10, Vi2, (1 kV)2, 106, (c) Ri 4 100 Ro 20 , Pi, 10 kW, 10, , 11.3 Decibels, , 499
Page 511 :
f, EXAMPLE 11.7, , An amplifier rated at 40-W output is connected to a 10- speaker., (a) Calculate the input power required for full power output if the power gain is, 25 dB., (b) Calculate the input voltage for rated output if the amplifier voltage gain is 40 dB., , Solution, (a) Eq. (11.10):, , (b) Gv 20 log10, , 40 W, 25 10 log10 , Pi, , 40 W, 40 W, Pi , antilog (2.5), 3.16 102, , 40 W, 126.5 mW, 316, Vo, Vo, , 40 20 log10 , Vi, Vi, , Vo, antilog 2 100, Vi, Vo P, R, (4, 0)(, W10), V 20 V, Vo, 20 V, Vi 0.2 V 200 mV, 100, 100, , 11.4 GENERAL FREQUENCY, CONSIDERATIONS, The frequency of the applied signal can have a pronounced effect on the response of, a single-stage or multistage network. The analysis thus far has been for the midfrequency spectrum. At low frequencies, we shall find that the coupling and bypass capacitors can no longer be replaced by the short-circuit approximation because of the, increase in reactance of these elements. The frequency-dependent parameters of the, small-signal equivalent circuits and the stray capacitive elements associated with the, active device and the network will limit the high-frequency response of the system., An increase in the number of stages of a cascaded system will also limit both the, high- and low-frequency responses., The magnitudes of the gain response curves of an RC-coupled, direct-coupled,, and transformer-coupled amplifier system are provided in Fig. 11.4. Note that the horizontal scale is a logarithmic scale to permit a plot extending from the low- to the, high-frequency regions. For each plot, a low-, high-, and mid-frequency region has, been defined. In addition, the primary reasons for the drop in gain at low and high, frequencies have also been indicated within the parentheses. For the RC-coupled amplifier, the drop at low frequencies is due to the increasing reactance of CC, Cs, or CE,, while its upper frequency limit is determined by either the parasitic capacitive elements of the network and frequency dependence of the gain of the active device. An, explanation of the drop in gain for the transformer-coupled system requires a basic, understanding of “transformer action” and the transformer equivalent circuit. For the, moment, let us say that it is simply due to the “shorting effect” (across the input terminals of the transformer) of the magnetizing inductive reactance at low frequencies, (XL 2 fL). The gain must obviously be zero at f 0 since at this point there is no, longer a changing flux established through the core to induce a secondary or output, voltage. As indicated in Fig. 11.4, the high-frequency response is controlled primarily by the stray capacitance between the turns of the primary and secondary wind500, , Chapter 11, , BJT and JFET Frequency Response
Page 512 :
f, , Figure 11.4 Gain versus frequency: (a) RC-coupled amplifiers; (b) transformercoupled amplifiers; (c) direct-coupled amplifiers., , ings. For the direct-coupled amplifier, there are no coupling or bypass capacitors to, cause a drop in gain at low frequencies. As the figure indicates, it is a flat response, to the upper cutoff frequency, which is determined by either the parasitic capacitances, of the circuit or the frequency dependence of the gain of the active device., For each system of Fig. 11.4, there is a band of frequencies in which the magnitude of the gain is either equal or relatively close to the midband value. To fix the, frequency boundaries of relatively high gain, 0.707Avmid was chosen to be the gain at, the cutoff levels. The corresponding frequencies f1 and f2 are generally called the corner, cutoff, band, break, or half-power frequencies. The multiplier 0.707 was chosen, because at this level the output power is half the midband power output, that is, at, midfrequencies,, AvmidVi2, V2o, Pomid , Ro, Ro, and at the half-power frequencies,, 0.707AvmidVi2, AvmidVi2, PoHPF 0.5 , Ro, Ro, 11.4 General Frequency Considerations, , 501
Page 513 :
f, , PoHPF 0.5Pomid, , and, , (11.16), , The bandwidth (or passband) of each system is determined by f1 and f2, that is,, bandwidth (BW) f2 f1, , (11.17), , For applications of a communications nature (audio, video), a decibel plot of the, voltage gain versus frequency is more useful than that appearing in Fig. 11.4. Before, obtaining the logarithmic plot, however, the curve is generally normalized as shown, in Fig. 11.5. In this figure, the gain at each frequency is divided by the midband value., Obviously, the midband value is then 1 as indicated. At the half-power frequencies,, the resulting level is 0.707 1/2. A decibel plot can now be obtained by applying, Eq. (11.12) in the following manner:, Av, Av, dB 20 log10 , Avmid, Avmid, , (11.18), , Aυ, A υmid, 1, 0.707, , f1 100, , 10, , 1000, , 10,000, , 100,000, , f2, , 1 MHz, , 10 MHz, , f (log scale), , Figure 11.5 Normalized gain versus frequency plot., , At midband frequencies, 20 log10 1 0, and at the cutoff frequencies, 20 log10, 1/2 3 dB. Both values are clearly indicated in the resulting decibel plot of Fig., 11.6. The smaller the fraction ratio, the more negative the decibel level., Aυ, Aυ, 10, 0 dB, , mid (dB), , f1, , 100, , 1000, , 10,000, , 100,000, , f2, , 1 MHz, , 10 MHz, , f (log scale), , − 3 dB, − 6 dB, − 9 dB, − 12 dB, , Figure 11.6 Decibel plot of the normalized gain versus frequency plot of Fig. 11.5., , For the greater part of the discussion to follow, a decibel plot will be made only, for the low- and high-frequency regions. Keep Fig. 11.6 in mind, therefore, to permit, a visualization of the broad system response., It should be understood that most amplifiers introduce a 180° phase shift between, input and output signals. This fact must now be expanded to indicate that this is the, case only in the midband region. At low frequencies, there is a phase shift such that, Vo lags Vi by an increased angle. At high frequencies, the phase shift will drop below 180°. Figure 11.7 is a standard phase plot for an RC-coupled amplifier., 502, , Chapter 11, , BJT and JFET Frequency Response
Page 514 :
f, , < (Vo leads Vi ), 360°, 270°, 180°, 90°, 0°, 10, , 1000, , f1 100, , 10,000, , 100,000, , f2, , 1 MHz, , 10 MHz, , f (log scale), , Figure 11.7 Phase plot for an RC-coupled amplifier system., , 11.5 LOW-FREQUENCY ANALYSIS—, BODE PLOT, In the low-frequency region of the single-stage BJT or FET amplifier, it is the R-C, combinations formed by the network capacitors CC, CE, and Cs and the network resistive parameters that determine the cutoff frequencies. In fact, an R-C network similar to Fig. 11.8 can be established for each capacitive element and the frequency at, which the output voltage drops to 0.707 of its maximum value determined. Once the, cutoff frequencies due to each capacitor are determined, they can be compared to establish which will determine the low-cutoff frequency for the system., Our analysis, therefore, will begin with the series R-C combination of Fig. 11.8, and the development of a procedure that will result in a plot of the frequency response, with a minimum of time and effort. At very high frequencies,, , Figure 11.8 R-C combination, that will define a low cutoff frequency., , +, Vi, , –, , 1, XC 0 , 2 fC, and the short-circuit equivalent can be substituted for the capacitor as shown in Fig., 11.9. The result is that Vo Vi at high frequencies. At f 0 Hz,, , +, R, , Vo, , –, , Figure 11.9 R-C circuit of Figure 11.8 at very high frequencies., , 1, 1, XC , 2 fC, 2 (0)C, and the open-circuit approximation can be applied as shown in Fig. 11.10, with the, result that Vo 0 V., Between the two extremes, the ratio Av Vo /Vi will vary as shown in Fig. 11.11., As the frequency increases, the capacitive reactance decreases and more of the input, voltage appears across the output terminals., , Figure 11.10 R-C circuit of, Figure 11.8 at f 0 Hz., , A υ = Vo / Vi, 1, 0.707, , 0, , f1, , f, , Figure 11.11 Low frequency response for the R-C circuit of Figure 11.8., , 11.5 Low-Frequency Analysis—Bode Plot, , 503
Page 515 :
f, The output and input voltages are related by the voltage-divider rule in the following manner:, RVi, Vo , R XC, with the magnitude of Vo determined by, RVi, Vo , 2, R, 2, , X, C, For the special case where XC R,, RVi, RVi, RVi, RVi, 1, , Vi, Vo , 2 2, 2, R, , 2R, , X C, 2, R 2, Vo, 1, Av 0.707XCR, Vi, 2, , and, , (11.19), , the level of which is indicated on Fig. 11.11. In other words, at the frequency of which, XC R, the output will be 70.7% of the input for the network of Fig. 11.8., The frequency at which this occurs is determined from, 1, XC R, 2 f1C, 1, f1 , 2 RC, , and, , (11.20), , In terms of logs,, 1, Gv 20 log10 Av 20 log10 3 dB, , 2, , while at Av Vo /Vi 1 or Vo Vi (the maximum value),, Gv 20 log10 1 20(0) 0 dB, In Fig. 11.6, we recognize that there is a 3-dB drop in gain from the midband, level when f f1. In a moment, we will find that an RC network will determine the, low-frequency cutoff frequency for a BJT transistor and f1 will be determined by, Eq. (11.20)., If the gain equation is written as, Vo, R, 1, 1, 1, Av , Vi, R jXC, 1 j(XC/R), 1 j(1/ CR), 1 j(1/2 fCR), and using the frequency defined above,, 1, Av , 1 j( f1/f ), , (11.21), , Vo, 1, Av 2 tan1( f1/f ), Vi, 1, , , (, f1/f, ), , (11.22), , magnitude of Av, , 504, , Chapter 11, , BJT and JFET Frequency Response, , , , , , , , , , , , , , , , In the magnitude and phase form,, , phase by which, Vo leads Vi
Page 516 :
f, , For the magnitude when f f1,, 1, 1, Av 2 0.707 → 3 dB, 1, 2, (1, ), In the logarithmic form, the gain in dB is, , , , f1, 1, Av(dB) 20 log10 2 20 log10 1 , f, 1, , ( , f1/f, ), , 2 1/2, , , , f1, (12)(20) log10 1 , f, , 2, , , , f1, 10 log10 1 , f, For frequencies where f, by, , f1 or (f1/f)2, , 2, , 1, the equation above can be approximated, , , , f1, Av(dB) 10 log10 , f, and finally,, , 2, , f1, Av(dB) 20 log10 , f, , (11.23), f, , f1, , Ignoring the condition f f1 for a moment, a plot of Eq. (11.23) on a frequency, log scale will yield a result of a very useful nature for future decibel plots., f1, At f f1: 1 and 20 log10 1 0 dB, f, f1, At f 12 f1: 2 and 20 log10 2 6 dB, f, f1, At f 14 f1: 4 and 20 log10 4 12 dB, f, f1, At f 110 f1: 10 and 20 log10 10 20 dB, f, A plot of these points is indicated in Fig. 11.12 from 0.1f1 to f1. Note that this results in a straight line when plotted against a log scale. In the same figure, a straight, Figure 11.12 Bode plot for the, low-frequency region., , 505
Page 517 :
f, line is also drawn for the condition of 0 dB for f f1. As stated earlier, the straightline segments (asymptotes) are only accurate for 0 dB when f f1 and the sloped line, when f1 f. We know, however, that when f f1, there is a 3-dB drop from the midband level. Employing this information in association with the straight-line segments, permits a fairly accurate plot of the frequency response as indicated in the same figure. The piecewise linear plot of the asymptotes and associated breakpoints is called, a Bode plot of the magnitude versus frequency., The calculations above and the curve itself demonstrate clearly that:, A change in frequency by a factor of 2, equivalent to 1 octave, results in a, 6-dB change in the ratio as noted by the change in gain from f1/2 to f1., As noted by the change in gain from f1/2 to f1:, For a 10:1 change in frequency, equivalent to 1 decade, there is a 20-dB, change in the ratio as demonstrated between the frequencies of f1/10 and f1., In the future, therefore, a decibel plot can easily be obtained for a function having the format of Eq. (11.23). First, simply find f1 from the circuit parameters and, then sketch two asymptotes—one along the 0-dB line and the other drawn through f1, sloped at 6 dB/octave or 20 dB/decade. Then, find the 3-dB point corresponding to, f1 and sketch the curve., , EXAMPLE 11.8, , For the network of Fig. 11.13:, (a) Determine the break frequency., (b) Sketch the asymptotes and locate the 3-dB point., (c) Sketch the frequency response curve., , Solution, , Figure 11.13 Example 11.8, , 1, 1, (a) f1 , 3, 2 RC, (6.28)(5 10 )(0.1 106 F), 318.5 Hz, (b) and (c). See Fig. 11.14., , Figure 11.14 Frequency response for the R-C circuit of Figure 11.13., , 506, , Chapter 11, , BJT and JFET Frequency Response
Page 518 :
f, The gain at any frequency can then be determined from the frequency plot in the, following manner:, Vo, Av(dB) 20 log10 , Vi, but, , Av(dB), Vo, log10 , Vi, 20, , and, , , , Vo, 20, Av 10, Vi, Av(dB), , (11.24), , For example, if Av(dB) 3 dB,, Vo, Av 10(3/20) 10(0.15) 0.707, Vi, , as expected, , The quantity 100.15 is determined using the 10x function found on most scientific, calculators., From Fig. 11.14, Av(dB) 1 dB at f 2f1 637 Hz. The gain at this point is, , , , Vo, 20, 10(1/20) 10(0.05) 0.891, Av 10, Vi, Av(dB), , Vo 0.891Vi, , and, , or Vo is 89.1% of Vi at f 637 Hz., The phase angle of is determined from, f1, tan1 , f, from Eq. (11.22)., For frequencies f, , (11.25), , f1,, f1, tan1 → 90°, f, , For instance, if f1 100f,, f1, tan1 tan1(100) 89.4°, f, For f f1,, f1, tan1 tan11 45°, f, For f, , f1,, f1, tan1 → 0°, f, , For instance, if f 100f1,, f1, tan1 tan1 0.01 0.573°, f, 11.5 Low-Frequency Analysis—Bode Plot, , 507
Page 519 :
f, , A plot of tan1(f1/f) is provided in Fig. 11.15. If we add the additional 180°, phase shift introduced by an amplifier, the phase plot of Fig. 11.7 will be obtained., The magnitude and phase response for an R-C combination have now been established. In Section 11.6, each capacitor of importance in the low-frequency region will, be redrawn in an R-C format and the cutoff frequency for each determined to establish the low-frequency response for the BJT amplifier., , Figure 11.15 Phase response for the R-C circuit of Figure 11.8., , 11.6 LOW-FREQUENCY RESPONSE —, BJT AMPLIFIER, The analysis of this section will employ the loaded voltage-divider BJT bias configuration, but the results can be applied to any BJT configuration. It will simply be necessary to find the appropriate equivalent resistance for the R-C combination. For the, network of Fig. 11.16, the capacitors Cs, CC, and CE will determine the low-frequency, response. We will now examine the impact of each independently in the order listed., VCC, , RC, R1, , CC, Vo, , Cs, , +, Rs, , RL, Vi, , +, Vs, , –, , R2, RE, , Zi, , CE, , –, , Figure 11.16 Loaded BJT amplifier with capacitors that affect the low-frequency response., , Cs, Since Cs is normally connected between the applied source and the active device, the, general form of the R-C configuration is established by the network of Fig. 11.17., The total resistance is now Rs Ri, and the cutoff frequency as established in Section 11.5 is, 508, , Chapter 11, , BJT and JFET Frequency Response
Page 520 :
1, fLS , 2 (Rs Ri)Cs, , f, (11.26), , At mid or high frequencies, the reactance of the capacitor will be sufficiently small +, to permit a short-circuit approximation for the element. The voltage Vi will then be Vs, related to Vs by, –, RiVs, Vimid , Ri Rs, , (11.27), , At fLS, the voltage Vi will be 70.7% of the value determined by Eq. (11.27), assuming that Cs is the only capacitive element controlling the low-frequency response., For the network of Fig. 11.16, when we analyze the effects of Cs we must make, the assumption that CE and CC are performing their designed function or the analysis becomes too unwieldy, that is, that the magnitude of the reactances of CE and CC, permits employing a short-circuit equivalent in comparison to the magnitude of the, other series impedances. Using this hypothesis, the ac equivalent network for the input section of Fig. 11.16 will appear as shown in Fig. 11.18., The value of Ri for Eq. (11.26) is determined by, , Cs, , +, , Cs, , Rs, , Vi, , Ri, , System, , –, Figure 11.17 Determining the, effect of Cs on the low frequency, response., , +, , Rs, , +, , Vi, , R2 R2, , hie = βre, , Vs, , Figure 11.18 Localized ac equivalent for Cs., , –, , –, , Ri R1R2re, , (11.28), , The voltage Vi applied to the input of the active device can be calculated using the, voltage-divider rule:, RiVs, Vi , Rs Ri jXCS, , (11.29), , +, , CC, , RL Vo, , System, , CC, , Ro, , Since the coupling capacitor is normally connected between the output of the active, device and the applied load, the R-C configuration that determines the low cutoff frequency due to CC appears in Fig. 11.19. From Fig. 11.19, the total series resistance, is now Ro RL and the cutoff frequency due to CC is determined by, , Figure 11.19 Determining the, effect of CC on the low-frequency, response., , (11.30), , (11.31), , C, , +, ro, , Vc, , –, , Ignoring the effects of Cs and CE, the output voltage Vo will be 70.7% of its midband, value at fLC. For the network of Fig. 11.16, the ac equivalent network for the output, section with Vi 0 V appears in Fig. 11.20. The resulting value for Ro in Eq. (11.30), is then simply, Ro RC ro, , Thévenin, , +, , CC, RL, , RC, Ro, , Figure 11.20 Localized ac, equivalent for CC with Vi 0 V., , 11.6 Low-Frequency Response—BJT Amplifier, , Vo, , –, , 1, fLC , 2 (Ro RL)CC, , –, , 509
Page 521 :
f, CE, System, , CE, , Re, , 1, fLE , 2 ReCE, , Figure 11.21 Determining the, effect of CE on the low-frequency, response., R's, + re, β, , To determine fLE , the network “seen” by CE must be determined as shown in Fig., 11.21. Once the level of Re is established, the cutoff frequency due to CE can be determined using the following equation:, , For the network of Fig. 11.16, the ac equivalent as “seen” by CE appears in Fig. 11.22., The value of Re is therefore determined by, Rs, Re RE re, , , , , E, Re, RE, , CE, , , , RC, Av , re RE, , RC, Vo, Vi, , RE, , Figure 11.23 Network employed, to describe the effect of CE on, the amplifier gain., , The maximum gain is obviously available where RE is zero ohms. At low frequencies, with the bypass capacitor CE in its “open-circuit” equivalent state, all of RE appears in the gain equation above, resulting in the minimum gain. As the frequency increases, the reactance of the capacitor CE will decrease, reducing the parallel, impedance of RE and CE until the resistor RE is effectively “shorted out” by CE. The, result is a maximum or midband gain determined by Av RC/re. At fLE the gain, will be 3 dB below the midband value determined with RE “shorted out.”, Before continuing, keep in mind that Cs, CC, and CE will affect only the lowfrequency response. At the midband frequency level, the short-circuit equivalents for, the capacitors can be inserted. Although each will affect the gain Av Vo/Vi in a similar frequency range, the highest low-frequency cutoff determined by Cs, CC, or CE, will have the greatest impact since it will be the last encountered before the midband, level. If the frequencies are relatively far apart, the highest cutoff frequency will essentially determine the lower cutoff frequency for the entire system. If there are two, or more “high” cutoff frequencies, the effect will be to raise the lower cutoff frequency and reduce the resulting bandwidth of the system. In other words, there is an, interaction between capacitive elements that can affect the resulting low cutoff frequency. However, if the cutoff frequencies established by each capacitor are sufficiently separated, the effect of one on the other can be ignored with a high degree of, accuracy—a fact that will be demonstrated by the printouts to appear in the following example., , (a) Determine the lower cutoff frequency for the network of Fig. 11.16 using the following parameters:, Cs 10 F,, Rs 1 k,, RL 2.2 k, , 100,, , CE 20 F,, R1 40 k,, ro ,, , CC 1 F, R2 10 k,, , VCC 20 V, , (b) Sketch the frequency response using a Bode plot., , 510, , (11.33), , where Rs RsR1R2., The effect of CE on the gain is best described in a quantitative manner by recalling that the gain for the configuration of Fig. 11.23 is given by, , Figure 11.22 Localized ac, equivalent of CE., , EXAMPLE 11.9, , (11.32), , Chapter 11, , BJT and JFET Frequency Response, , RE 2 k,, , RC 4 k,
Page 522 :
f, Solution, (a) Determining re for dc conditions:, , RE (100)(2 k) 200 k, , 10R2 100 k, , The result is:, R2VCC, 10 k(20 V), 200 V, VB 4 V, R2 R1, 10 k 40 k, 50, VE, 4 V 0.7 V, 3.3 V, IE 1.65 mA, 2 k, RE, 2 k, , with, , 26 mV, re 15.76 , 1.65 mA, , so that, , re 100(15.76 ) 1576 1.576 k, , and, Midband Gain, , Vo, RCRL, (4 k) (2.2 k), Av 90, Vi, re, 15.76 , The input impedance, Zi Ri R1R2re, 40 k10 k1.576 k, 1.32 k, and from Fig. 11.24,, RiVs, Vi , Ri Rs, Vi, Ri, 1.32 k, 0.569, 1.32 k 1 k, Vs, Ri Rs, , or, , Vo, Vo Vi, Avs (90)(0.569), Vs, Vi Vs, , so that, , 51.21, Rs, , +, +, Vs, , Ri, , Vi, , –, –, , Figure 11.24 Determining the, effect of Rs on the gain Avs., , Cs, , Ri R1R2re 40 k10 k1.576 k 1.32 k, 1, 1, fLS , 2 (Rs Ri)Cs, (6.28)(1 k 1.32 k)(10 F), fLS 6.86 Hz, 11.6 Low-Frequency Response—BJT Amplifier, , 511
Page 523 :
f, The results just obtained will now be verified using PSpice Windows. The network with its various capacitors appears in Fig. 11.25. The Model Editor was used, to set Is to 2E-15A and beta to 100. The remaining parameters were removed from, the listing to idealize the response to the degree possible. Under Analysis Setup-AC, Sweep, the frequency was set to 10 kHz to establish a frequency in the midband region. A simulation of the network resulted in the dc levels of Fig. 11.25. Note that, VB is 3.9 V versus the calculated level of 4 V and that VE is 3.2 V versus the calculated level of 3.3 V. Very close when you consider that the approximate model was, used. VBE is very close to the 0.7 V at 0.71 V. The output file reveals that the ac voltage across the load at a frequency of 10 kHz is 49.67 mV, resulting in a gain of 49.67,, which is very close to the calculated level of 51.21., , Figure 11.25 Network of Figure 11.16 with assigned values., , A plot of the gain versus frequency will now be obtained with only CS as a determining factor. The other capacitors, CC and CE, will be set to very high values so, they are essentially short circuits at any of the frequencies of interest. Setting CC and, CE to 1 F will remove any affect they will have on the response on the low-frequency, region. Here, one must be careful as the program does not recognize 1F as one Farad., It must be entered as 1E6uF. Since the pattern desired is gain versus frequency, we, must use the sequence Analysis-Setup-Analysis Setup-Enable AC Sweep-AC Sweep, to obtain the AC Sweep and Noise Analysis dialog box. Since our interest will be in, the low-frequency range, we will choose a range of 1 Hz (0 Hz is an invalid entry), to 100 Hz. If you want a frequency range starting close to 0 Hz, you would have to, choose a frequency such as 0.001 Hz or something small enough not to be noticeable, on the plot. The Total Pts.: will be set at 1000 for a good continuous plot, the Start, Freq.: at 1 Hz, and the End Freq.: at 100 Hz. The AC Sweep Type will be left on, Linear. A simulation followed by Trace-Add-V(RL:1) will result in the desired plot., However, the computer has selected a log scale for the horizontal axis that extends, from 1 Hz to 1 kHz even though we requested a linear scale. If we choose Plot-XAxis Settings-Linear-OK, we will get a linear plot to 120 Hz, but the curve of interest is all in the low end—the log axis obviously provided a better plot for our region of interest. Returning to Plot-X-Axis Settings and choosing Log, we return to, the original plot. Our interest only lies in the region of 1 to 100 Hz, so the remaining frequencies to 1 kHz should be removed with Plot-X-Axis Settings-User Defined-1Hz to 100Hz-OK. The vertical axis also goes to 60 mV, and we want to limit, to 50 mV for this frequency range. This is accomplished with Plot-Y-Axis SettingsUser Defined-0V to 50mV-OK, after which the pattern of Fig. 11.26 will be obtained., 512, , Chapter 11, , BJT and JFET Frequency Response
Page 524 :
f, , Figure 11.26 Low-frequency, response due to CS., , Note how closely the curve approaches 50 mV in this range. The cutoff level is, determined by 0.707(49.67 mV) 35.12 mV, which can be found by clicking the, Toggle cursor icon and moving the intersection up the graph until the 35.177-mV, level is reached for A1. At this point, the frequency of the horizontal axis can be read, as 6.74 Hz, comparing very well to the predicted value of 6.86 Hz. Note that A2 remains at the lowest level of the plot, at 1 Hz., CC, , 1, fLC , 2 (RC RL)CC, 1, , (6.28)(4 k 2.2 k)(1 F), 25.68 Hz, To investigate the effects of CC on the lower cutoff frequency, both CS and CE must, be set to 1 Farad as described above. Following the procedure outlined above will result in the plot of Fig. 11.27, with a cutoff frequency of 25.58 Hz, providing a close, match with the calculated level of 25.68 Hz., Figure 11.27 Low-frequency, response due to CC., , 513
Page 525 :
f, CE, , Rs RsR1R2 1 k40 k10 k 0.889 k, Re RE, , Rs, , 15.76 , r 2 k10, 0, 0.889 k, , e, , 2 k(8.89 15.76 ) 2 k24.65 24.35 , 1, 106, 1, fLE 327 Hz, 2 ReCE, 3058.36, (6.28)(24.35 )(20 F), The effect of CE can be examined using PSpice Windows by setting both CS and, CC to 1 Farad. In addition, since the frequency range is greater, the start frequency, has to be changed to 10 Hz and the final frequency to 1 kHz. The result is the plot, of Fig. 11.28, with a cutoff frequency of 321.17 Hz, providing a close match with the, calculated value of 327 Hz., , Figure 11.28 Low-frequency response due to CE., , The fact that fLE is significantly higher than fLS or fLC suggests that it will be the, predominant factor in determining the low-frequency response for the complete system. To test the accuracy of our hypothesis, the network is simulated with all the initial values of capacitance level to obtain the results of Fig. 11.29. Note the strong similarity with the waveform of Fig. 11.28, with the only visible difference being the, higher gain at lower frequencies on Fig. 11.28. Without question, the plot supports, the fact that the highest of the low cutoff frequencies will have the most impact on, the low cutoff frequency for the system., (b) It was mentioned earlier that dB plots are usually normalized by dividing the voltage gain Av by the magnitude of the midband gain. For Fig. 11.16, the magnitude, of the midband gain is 51.21, and naturally the ratio Av /Avmid will be 1 in the, midband region. The result is a 0-dB asymptote in the midband region as shown, in Fig. 11.30. Defining fLE as our lower cutoff frequency f1, an asymptote at 6, dB/octave can be drawn as shown in Fig. 11.30 to form the Bode plot and our, 514, , Chapter 11, , BJT and JFET Frequency Response
Page 526 :
f, , Figure 11.29 Low-frequency response due to CS, CE, and CC., , envelope for the actual response. At f1, the actual curve is 3 dB down from the, midband level as defined by the 0.707AVmid level, permitting a sketch of the actual frequency response curve as shown in Fig. 11.30. A 6-dB/octave asymptote was drawn at each frequency defined in the analysis above to demonstrate, clearly that it is fLE for this network that will determine the 3-dB point. It is not, until about 24 dB that fLC begins to affect the shape of the envelope. The magnitude plot shows that the slope of the resultant asymptote is the sum of the asymptotes having the same sloping direction in the same frequency interval. Note, in Fig. 11.30 that the slope has dropped to 12 dB/octave for frequencies less, , Figure 11.30 Low-frequency plot for the network of, Example 11.9., , 11.6 Low-Frequency Response—BJT Amplifier, , 515
Page 527 :
f, fL, C, , -6dB/octave, -20dB/decade, , -12dB/octave, -20dB/decade, , Figure 11.31 dB plot of the low-frequency response of the BJT amplifier of Fig. 11.25., , than fLC and could drop to 18 dB/octave if the three defined cutoff frequencies, of Fig. 11.30 were closer together., Using PROBE, a plot of 20 log10Av /Avmid Av /AvmiddB can be obtained by, recalling that if Vs 1 mV, the magnitude of Av /Avmid is the same as Vo /Avmid, since Vo will have the same numerical value as Av. The required Trace Expression, which is entered on the bottom of the Add Traces dialog box, appears on, the horizontal axis of Fig. 11.31. The plot clearly reveals the change in slope of, the asymptote at fLC and how the actual curve follows the envelope created by the, Bode plot. In addition, note the 3-dB drop at f1., , Keep in mind as we proceed to the next section that the analysis of this section, is not limited to the network of Fig. 11.16. For any transistor configuration it is simply necessary to isolate each R-C combination formed by a capacitive element and, determine the break frequencies. The resulting frequencies will then determine, whether there is a strong interaction between capacitive elements in determining the, overall response and which element will have the greatest impact on establishing the, lower cutoff frequency. In fact, the analysis of the next section will parallel this section as we determine the low cutoff frequencies for the FET amplifier., , 11.7 LOW-FREQUENCY RESPONSE — FET, AMPLIFIER, The analysis of the FET amplifier in the low-frequency region will be quite similar, to that of the BJT amplifier of Section 11.6. There are again three capacitors of primary concern as appearing in the network of Fig. 11.32: CG, CC, and CS. Although, Fig. 11.32 will be used to establish the fundamental equations, the procedure and conclusions can be applied to most FET configurations., 516, , Chapter 11, , BJT and JFET Frequency Response
Page 528 :
f, , Figure 11.32 Capacitive elements that affect the low-frequency response of a JFET amplifier., , CG, For the coupling capacitor between the source and the active device, the ac equivalent network will appear as shown in Fig. 11.33. The cutoff frequency determined by, CG will then be, 1, fLG , 2 (Rsig Ri)CG, , (11.34), , which is an exact match of Eq. (11.26). For the network of Fig. 11.32,, Ri RG, , +, Vs, , –, , Rsig, , (11.35), , CG, System, Ri, , Figure 11.33 Determining the, effect of CG on the low-frequency, response., , Typically, RG Rsig, and the lower cutoff frequency will be determined primarily by, RG and CG. The fact that RG is so large permits a relatively low level of CG while, maintaining a low cutoff frequency level for fLG., , CC, For the coupling capacitor between the active device and the load the network of Fig., 11.34 will result, which is also an exact match of Fig. 11.19. The resulting cutoff, frequency is, 1, fLC , 2 (Ro RL)CC, , (11.36), , Ro RDrd, , (11.37), , For the network of Fig. 11.32,, , 11.7 Low-Frequency Response—FET Amplifier, , 517
Page 529 :
f, CC, RL, , System, Ro, , System, Reg, , Figure 11.34 Determining the effect of CC on, the low-frequency response., , CS, , Figure 11.35 Determining the effect of CS, on the low-frequency response., , CS, For the source capacitor CS, the resistance level of importance is defined by Fig. 11.35., The cutoff frequency will be defined by, 1, fLS , 2 ReqCS, , (11.38), , For Fig. 11.32, the resulting value of Req:, RS, Req , 1 RS(1 gmrd)/(rd RDRL), , (11.39), , which for rd becomes, 1, Req RS, gm, , EXAMPLE 11.10, , (11.40), , (a) Determine the lower cutoff frequency for the network of Fig. 11.32 using the following parameters:, CG 0.01 F,, , CC 0.5 F,, , CS 2 F, , Rsig 10 k,, , RG 1 M,, , RD 4.7 k,, , IDSS 8mA,, , VP 4 V, , rd ,, , RS 1 k,, , RL 2.2 k, , VDD 20 V, , (b) Sketch the frequency response using a Bode plot., , Solution, (a) DC Analysis: Plotting the transfer curve of ID IDSS(1 VGS/VP)2 and superimposing the curve defined by VGS IDRS will result in an intersection at VGSQ 2, V and IDQ 2 mA. In addition,, 2IDSS, 2(8 mA), gm0 4 mS, VP, 4V, VGSQ, 2 V, gm gm0 1 4 mS 1 2 mS, VP, 4 V, , , , , , , , , , CG, , Eq. (11.34):, 518, , Chapter 11, , 1, fLG 15.8 Hz, 2 (10 k 1 M)(0.01 F), , BJT and JFET Frequency Response
Page 530 :
f, CC, , Eq. (11.36):, , 1, fLC 46.13 Hz, 2 (4.7 k 2.2 k)(0.5 F), , CS, , 1, 1, Req RS 1 k 1 k0.5 k 333.33 , gm, 2 mS, Eq. (11.38):, , 1, fLS 238.73 Hz, 2 (333.33 )(2 F), , Since fLS is the largest of the three cutoff frequencies, it defines the low cutoff frequency for the network of Fig. 11.32., (b) The midband gain of the system is determined by, Vo, Avmid gm(RDRL) (2 mS)(4.7 k2.2 k), Vi, (2 mS)(1.499 k), 3, Using the midband gain to normalize the response for the network of Fig. 11.32 will, result in the frequency plot of Fig. 11.36., , Figure 11.36 Low-frequency, response for the JFET configuration of Example 11.10., , Using PSpice Windows, the network will appear as shown in Fig. 11.37, with the, JFET parameters Beta set at 0.5mA/V2 and Vto at 4 V (all others set to zero) and, the frequency of interest at a midband value of 10 kHz. The resulting dc levels confirm that VGS is 2 V and place VD at 10.60 V, which should be right in the middle, of the linear active region since VGS 1/2(VD 4 V) and VDS 1/2(VDD 20 V)., The 0-V levels clearly reveal that the capacitors have isolated the transistor for the dc, biasing. The ac response results in an ac level of 2.993 mV across the load for a gain, of 2.993, which is essentially equal to the calculated gain of 3., 11.7 Low-Frequency Response—FET Amplifier, , 519
Page 531 :
f, , Figure 11.37 Schematic network for Example 11.10., , Returning to Analysis and choosing Automatically run Probe after simulation, followed by Setup-AC Sweep-Decade-Pts/Decade 1000, Start Freq.: 10Hz, and, End Freq.: 10 kHz will setup Simulation-Trace-Add-Trace Expression: DB, (V(RL:1)/2.993mV)-OK, which will result in the plot of Fig. 11.38, with a low cutoff frequency of 227.5 Hz primarily determined by the source capacitance., , Figure 11.38 dB response for, the low-frequency region in the, network of Example 11.10., , 11.8 MILLER EFFECT CAPACITANCE, In the high-frequency region, the capacitive elements of importance are the interelectrode (between terminals) capacitances internal to the active device and the wiring, capacitance between leads of the network. The large capacitors of the network that, controlled the low-frequency response have all been replaced by their short-circuit, equivalent due to their very low reactance levels., 520, , Chapter 11, , BJT and JFET Frequency Response
Page 532 :
f, For inverting amplifiers (phase shift of 180° between input and output resulting, in a negative value for Av), the input and output capacitance is increased by a capacitance level sensitive to the interelectrode capacitance between the input and output, terminals of the device and the gain of the amplifier. In Fig. 11.39, this “feedback”, capacitance is defined by Cf., , Figure 11.39 Network employed in, the derivation of an equation for the, Miller input capacitance., , Applying Kirchhoff’s current law gives, Ii I1 I2, Using Ohm’s law yields, Vi, Ii ,, Zi, , Vi, I1 , Ri, , Vi Vo, Vi AvVi, (1 Av)Vi, I2 , XCf, XCf, XCf, , and, , Substituting, we obtain, (1 Av)Vi, Vi, Vi, , XCf, Zi, Ri, 1, 1, 1, , Zi, Ri, XCf /(1 Av), , but, , XCf, 1, XCM, (1 Av)Cf, 1 Av, , , , , , , , , and, , CM, 1, 1, 1, , Zi, Ri, XCM, , and, , establishing the equivalent network of Fig. 11.40. The result is an equivalent input, impedance to the amplifier of Fig. 11.39 that includes the same Ri that we have dealt, with in previous chapters, with the addition of a feedback capacitor magnified by the, Ii, , +, Vi, , –, , Zi, , Ri, , CM = (1 − Aυ ) Cf, , Figure 11.40 Demonstrating, the impact of the Miller effect, capacitance., , 11.8 Miller Effect Capacitance, , 521
Page 533 :
f, gain of the amplifier. Any interelectrode capacitance at the input terminals to the amplifier will simply be added in parallel with the elements of Fig. 11.40., In general, therefore, the Miller effect input capacitance is defined by, CMi (1 Av)Cf, , (11.41), , This shows us that:, For any inverting amplifier, the input capacitance will be increased by a, Miller effect capacitance sensitive to the gain of the amplifier and the interelectrode capacitance connected between the input and output terminals of the, active device., The dilemma of an equation such as Eq. (11.41) is that at high frequencies the, gain Av will be a function of the level of CMi. However, since the maximum gain is, the midband value, using the midband value will result in the highest level of CMi and, the worst-case scenario. In general, therefore, the midband value is typically employed, for Av in Eq. (11.41)., The reason for the constraint that the amplifier be of the inverting variety is now, more apparent when one examines Eq. (11.41). A positive value for Av would result, in a negative capacitance (for Av 1)., The Miller effect will also increase the level of output capacitance, which must, also be considered when the high-frequency cutoff is determined. In Fig. 11.41, the, parameters of importance to determine the output Miller effect are in place. Applying Kirchhoff’s current law will result in, Io I1 I2, with, , Vo, I1 , Ro, , and, , Vo Vi, I2 , XCf, , The resistance Ro is usually sufficiently large to permit ignoring the first term of the, equation compared to the second term and assuming that, Vo Vi, Io , XCf, Substituting Vi Vo /Av from Av Vo /Vi will result in, Vo Vo/Av, Vo(1 1/Av), Io , XCf, XCf, and, , 1 1/Av, Io, , XCf, Vo, , Figure 11.41 Network employed in, the derivation of an equation for the, Miller output capacitance., , 522, , Chapter 11, , BJT and JFET Frequency Response
Page 534 :
or, , f, , XCf, Vo, 1, 1, , Io, 1 1/Av, Cf (1 1/Av), CMo, , resulting in the following equation for the Miller output capacitance:, , , , , , 1, CMo 1 Cf, Av, For the usual situation where Av, , (11.42a), , 1, Eq. (11.42a) reduces to, , CMo Cf, , Av, , (11.42b), 1, , Examples in the use of Eq. (11.42) will appear in the next two sections as we investigate the high-frequency responses of BJT and FET amplifiers., , 11.9 HIGH-FREQUENCY RESPONSE — BJT, AMPLIFIER, At the high-frequency end, there are two factors that will define the 3-dB point: the, network capacitance (parasitic and introduced) and the frequency dependence of, hfe()., , Network Parameters, In the high-frequency region, the RC network of concern has the configuration appearing in Fig. 11.42. At increasing frequencies, the reactance XC will decrease in, magnitude, resulting in a shorting effect across the output and a decrease in gain. The, derivation leading to the corner frequency for this RC configuration follows along, similar lines to that encountered for the low-frequency region. The most significant, difference is in the general form of Av appearing below:, 1, Av , 1 j( f/f2), , (11.43), , which results in a magnitude plot such as shown in Fig. 11.43 that drops off at, 6 dB/octave with increasing frequency. Note that f2 is in the denominator of the, frequency ratio rather than the numerator as occurred for f1 in Eq. (11.21)., In Fig. 11.44, the various parasitic capacitances (Cbe, Cbc, Cce) of the transistor, , Figure 11.42 R-C combination, that will define a high cutoff frequency., , Figure 11.43 Asymptotic plot, as defined by Eq. (11.43)., , have been included with the wiring capacitances (CWi, CWo) introduced during construction. The high-frequency equivalent model for the network of Fig. 11.44 appears, in Fig. 11.45. Note the absence of the capacitors Cs, CC, and CE, which are all assumed to be in the short-circuit state at these frequencies. The capacitance Ci includes, 11.9 High-Frequency Response—BJT Amplifier, , 523
Page 536 :
f, with, , RTh1 RsR1R2Ri, , (11.45), , and, , Ci CWi Cbe CMi CWi Cbe (1 Av)Cbc, , (11.46), , At very high frequencies, the effect of Ci is to reduce the total impedance of the parallel combination of R1, R2, Ri, and Ci in Fig. 11.45. The result is a reduced level of, voltage across Ci, a reduction in Ib, and a gain for the system., For the output network,, 1, fHo , 2 RTh2Co, , (11.47), , with, , RTh2 RCRLro, , (11.48), , and, , Co CWo Cce CMo, , (11.49), , At very high frequencies, the capacitive reactance of Co will decrease and consequently reduce the total impedance of the output parallel branches of Fig. 11.45. The, net result is that Vo will also decline toward zero as the reactance XC becomes smaller., The frequencies fHi and fHo will each define a 6-dB/octave asymptote such as depicted in Fig. 11.43. If the parasitic capacitors were the only elements to determine, the high cutoff frequency, the lowest frequency would be the determining factor. However, the decrease in hfe (or ) with frequency must also be considered as to whether, its break frequency is lower than fHi or fHo., , hfe (or ) Variation, The variation of hfe (or ) with frequency will approach, with some degree of accuracy, the following relationship:, hfemid, hfe , 1 j(f/f), , (11.50), , The use of hfe rather than in some of this descriptive material is due primarily, to the fact that manufacturers typically use the hybrid parameters when covering this, issue in their specification sheets, and so on., The only undefined quantity, f, is determined by a set of parameters employed, in the hybrid or Giacoletto model frequently applied to best represent the transistor in the high-frequency region. It appears in Fig. 11.47. The various parameters warrant a moment of explanation. The resistance rbb includes the base contact, base bulk,, and base spreading resistance. The first is due to the actual connection to the base., The second includes the resistance from the external terminal to the active region of, , rb'c, b', , B, Ib, , rbb', 1, rb'e = g, b'e, , E, , C, Cb'c, , I'b, Cb'e, , rce =, , 1, hoe, , gm Vb'e = gm rb'e I'b ≅ hfe, , I', mid b, , E, , 11.9 High-Frequency Response—BJT Amplifier, , Figure 11.47 Giacoletto (or, hybrid ) high-frequency transistor, small-signal ac equivalent circuit., , 525
Page 537 :
f, the transistors, while the last is the actual resistance within the active base region. The, resistances rbe, rce, and rbc are the resistances between the indicated terminals when, the device is in the active region. The same is true for the capacitances Cbc and Cbe,, although the former is a transition capacitance while the latter is a diffusion capacitance. A more detailed explanation of the frequency dependence of each can be found, in a number of readily available texts., In terms of these parameters,, gbe, f (sometimes appearing as fhfe ) , 2 (Cbe Cbc), , (11.51), , or since the hybrid parameter hfe is related to gbe through gm hfemid gbe,, gm, 1, f , hfemid 2 (Cbe Cbc), , (11.52), , Taking it a step further,, hfemid, mid, 1, 1, gm hfemid gbe hfemid , hie, rbe, midre, re, and using the approximations, Cbe Cbe, , Cbc Cbc, , and, , will result in the following form for Eq. (11.50):, 1, f , 2 midre(Cbe Cbc), , (11.53), , Equation (11.53) clearly reveals that since re is a function of the network design:, f is a function of the bias conditions., The basic format of Eq. (11.50) is exactly the same as Eq. (11.43) if we extract, the multiplying factor hfemid, revealing that hfe will drop off from its midband value, with a 6-dB/octave slope as shown in Fig. 11.48. The same figure has a plot of h f b, (or ) versus frequency. Note the small change in h f b for the chosen frequency range,, revealing that the common-base configuration displays improved high-frequency characteristics over the common-emitter configuration. Recall also the absence of the, Miller effect capacitance due to the noninverting characteristics of the common-base, configuration. For this very reason, common-base high-frequency parameters rather, than common-emitter parameters are often specified for a transistor—especially those, designed specifically to operate in the high-frequency regions., The following equation permits a direct conversion for determining f if f and , are specified., f f(1 ), , (11.54), , A quantity called the gain–bandwidth product is defined for the transistor by the, condition, hfemid, 1, 1 j( f/f), , , , 526, , Chapter 11, , BJT and JFET Frequency Response, ,
Page 539 :
f, EXAMPLE 11.11, , For the network of Fig. 11.44 with the same parameters as in Example 11.9, that is,, Rs 1 k, R1 40 k, R2 10 k, RE 2 k, RC 4 k, RL 2.2 k, Cs 10 F, CC 1 F, CE 20 F, , 100, ro , VCC 20 V, with the addition of, Cbe 36 pF, Cbc 4 pF, Cce 1 pF, CWi 6 pF, CWo 8 pF, (a) Determine fHi and fHo., (b) Find f and fT., (c) Sketch the frequency response for the low- and high-frequency regions using the, results of Example 11.9 and the results of parts (a) and (b)., (d) Obtain a PROBE response for the full frequency spectrum and compare with the, results of part (c)., , Solution, (a) From Example 11.9:, Ri 1.32 k,, , Avmid(amplifier) 90, , RTh1 RsR1R2Ri 1 k40 k10 k1.32 k, , and, , 0.531 k, Ci CWi Cbe (1 Av)Cbe, , with, , 6 pF 36 pF [1 (90)]4 pF, 406 pF, 1, 1, fHi , 2 RTh1Ci, 2 (0.531 k)(406 pF), 738.24 kHz, RTh2 RCRL 4 k2.2 k 1.419 k, , , , , , 1, Co CWo Cce CMo 8 pF 1 pF 1 4 pF, 90, 13.04 pF, 1, 1, fHo , 2 RTh2Co, 2 (1.419 k)(13.04 pF), 8.6 MHz, (b) Applying Eq. (11.53) gives, 1, f , 2 midre(Cbe Cbc), 1, 1, , 2 (100)(15.76 )(36 pF 4 pF), 2 (100)(15.76 )(40 pF), 2.52 MHz, fT mid f (100)(2.52 MHz), 252 MHz, 528, , Chapter 11, , BJT and JFET Frequency Response
Page 540 :
f, (c) See Fig. 11.49. Both f and fHo will lower the upper cutoff frequency below the, level determined by fHi. f is closer to fHi and therefore will have a greater impact, than fHo. In any event, the bandwidth will be less than that defined solely by fHi., In fact, for the parameters of this network the upper cutoff frequency will be relatively close to 600 kHz., Aυ, Aυ, , 1, , mid dB, , fL 10, s, , fL, , C, , 100, , fL, , E, , 1 kHz, , 10 kHz, , 100 kHz, , fHi, , 1 MHz, , 0, –3, , fβ, 10 MHz, , 100 MHz, f (log scale), , fHo, f2, , f1, , –5, , BW, −6 dB/octave, , –10, , –15, +20 dB/decade, –20, , −12 dB/octave, , Figure 11.49 Full frequency, response for the network of, Fig. 11.44., , –25, , In general, therefore, the lowest of the upper-cutoff frequencies defines a maximum possible bandwidth for a system., (d) In order to obtain a PSpice analysis for the full frequency range, the parasitic capacitances have to be added to the network as shown in Fig. 11.50., , Figure 11.50 Network of Figure 11.25 with parasitic capacitances in place., , 11.9 High-Frequency Response—BJT Amplifier, , 529
Page 541 :
f, An Analysis will result in the plot of Fig. 11.51 using the Trace Expression appearing at the bottom of the plot. The vertical scale was changed from 60 to 0 dB, to 30 to 0 dB to highlight the area of interest using the Y-Axis Settings. The low, cutoff frequency of 324 Hz is as determined primarily by fLE, and the high cutoff frequency is near 667kHz. Even though fHo is more than a decade higher than fHi, it will, have an impact on the high cutoff frequency. In total, however, the PSpice analysis, has been a welcome verification of the hand-written approach., , Figure 11.51 Full frequency response for the network of Fig. 11.50., , 11.10 HIGH-FREQUENCY RESPONSE —, FET AMPLIFIER, The analysis of the high-frequency response of the FET amplifier will proceed in a, very similar manner to that encountered for the BJT amplifier. As shown in Fig. 11.52,, there are interelectrode and wiring capacitances that will determine the high-frequency, characteristics of the amplifier. The capacitors Cgs and Cgd typically vary from 1, to 10 pF, while the capacitance Cds is usually quite a bit smaller, ranging from 0.1 to, 1 pF., Since the network of Fig. 11.52 is an inverting amplifier, a Miller effect capacitance will appear in the high-frequency ac equivalent network appearing in Fig. 11.53., At high frequencies, Ci will approach a short-circuit equivalent and Vgs will drop in, value and reduce the overall gain. At frequencies where Co approaches its shortcircuit equivalent, the parallel output voltage Vo will drop in magnitude., The cutoff frequencies defined by the input and output circuits can be obtained, by first finding the Thévenin equivalent circuits for each section as shown in Fig., 11.54. For the input circuit,, 530, , Chapter 11, , BJT and JFET Frequency Response
Page 543 :
f, , EXAMPLE 11.12, , with, , RTh2 RDRLrd, , and, , Co CWo Cds CMo, , and, , 1, CMo 1 Cgd, Av, , , , (11.64), , , , (11.65), , (a) Determine the high cutoff frequencies for the network of Fig. 11.52 using the, same parameters as Example 11.10:, CG 0.01 F,, Rsig 10 k,, , RG 1 M,, , IDSS 8 mA,, , CC 0.5 F,, RD 4.7 k,, , VP 4 V,, , CS 2 F, RS 1 k,, , rd ,, , RL 2.2 k, , VDD 20 V, , with the addition of, Cgd 2 pF,, , Cgs 4 pF,, , Cds 0.5 pF,, , CWi 5 pF,, , CWo 6 pF, , (b) Review a PROBE response for the full frequency range and note whether it supports the conclusions of Example 11.10 and the calculations above., , Solution, (a) RTh1 RsigRG 10 k1 M 9.9 k, From Example 11.10, Av 3., Ci CWi Cgs (1 Av)Cgd, 5 pF 4 pF (1 3)2 pF, 9 pF 8 pF, 17 pF, 1, fHi , 2 RTh1Ci, 1, 945.67 kHz, 2 (9.9 k)(17 pF), RTh2 RD RL, 4.7 k 2.2 k, 1.5 k, , , , , , 1, Co CWo Cds CMo 6 pF 0.5 pF 1 2 pF 9.17 pF, 3, 1, fHo 11.57 MHz, 2 (1.5 k)(9.17 pF), The results above clearly indicate that the input capacitance with its Miller effect capacitance will determine the upper cutoff frequency. This is typically the case due to, the smaller value of Cds and the resistance levels encountered in the output circuit., (b) Using PSpice Windows, the schematic for the network will appear as shown in, Fig. 11.55., , 532, , Chapter 11, , BJT and JFET Frequency Response
Page 544 :
f, , Figure 11.55 Network of Figure 11.52 with assigned values., , Under Analysis, the AC Sweep is set to Decade with Pts/Decade at 1000, Start, Freq.: at 10 Hz, and End Freq.: at 10 MHz. Under the Add Traces dialog box, the, Trace Expression is entered as DB(V(RL:1)/2.993mV), and the plot of Fig. 11.56, is obtained. Just for a moment, consider how much time it must have taken to obtain, a plot such as in Fig. 11.56 without computer methods for a network as complicated, as Fig. 11.55. Often, we forget how computer systems have helped us through some, painstaking, lengthy, and boring series of calculations., , Figure 11.56 Frequency response for the network of Example 11.12., , Using the cursor, we find the lower and upper cutoff frequencies to be 225 Hz, and 921 kHz, respectively, providing a nice match with the calculated values., , 11.10 High-Frequency Response—FET amplifier, , 533
Page 545 :
f, Even though the analysis of the past few sections has been limited to two configurations, the exposure to the general procedure for determining the cutoff frequencies should support the analysis of any other transistor configuration. Keep in, mind that the Miller capacitance is limited to inverting amplifiers and that f is significantly greater than f if the common-base configuration is encountered. There is, a great deal more literature on the analysis of single-stage amplifiers that goes beyond the coverage of this chapter. However, the content of this chapter should provide a firm foundation for any future analysis of frequency effects., , 11.11 MULTISTAGE FREQUENCY EFFECTS, For a second transistor stage connected directly to the output of a first stage, there, will be a significant change in the overall frequency response. In the high-frequency, region, the output capacitance Co must now include the wiring capacitance (CW1), parasitic capacitance (Cbe), and Miller capacitance (CMi) of the following stage. Further,, there will be additional low-frequency cutoff levels due to the second stage that will, further reduce the overall gain of the system in this region. For each additional stage,, the upper cutoff frequency will be determined primarily by that stage having the lowest cutoff frequency. The low-frequency cutoff is primarily determined by that stage, having the highest low-frequency cutoff frequency. Obviously, therefore, one poorly, designed stage can offset an otherwise well-designed cascaded system., The effect of increasing the number of identical stages can be clearly demonstrated by considering the situations indicated in Fig. 11.57. In each case, the upper, and lower cutoff frequencies of each of the cascaded stages are identical. For a single stage, the cutoff frequencies are f1 and f2 as indicated. For two identical stages in, cascade, the drop-off rate in the high- and low-frequency regions has increased to, 12 dB/octave or 40 dB/decade. At f1 and f2, therefore, the decibel drop is now, 6 dB rather than the defined band frequency gain level of 3 dB. The 3-dB, point has shifted to f1 and f2 as indicated, with a resulting drop in the bandwidth., A 18-dB/octave or 60-dB/decade slope will result for a three-stage system of identical stages with the indicated reduction in bandwidth (f 1 and f 2)., Assuming identical stages, an equation for each band frequency as a function of, the number of stages (n) can be determined in the following manner: For the lowfrequency region,, Avlow, (overall) Av1 Av2 Av3, low, , low, , low, , Avn, , low, , Figure 11.57 Effect of an increased number of stages on the cutoff frequencies, and the bandwidth., , 534, , Chapter 11, , BJT and JFET Frequency Response
Page 546 :
f, , but since each stage is identical, Av1 Av2 etc. and, low, , low, , Avlow, (overall) (Av1 )n, low, , or, , Avlow, Av1, (overall) , Avmid, Avmid, , , , low, , , , n, , 1, n, (1 jf1/f ), , Setting the magnitude of this result equal to 1/2 (3 dB level) results in, 1, 1, , , 2 n , 1, f, ( /f, )], 2, 1, 1, or, , , , f1, 1 , f 1, , 2 1/2 n, , , , f1, 1 , f 1, , , , 2 n 1/2, , , , 2, , , , 21/n, , so that, , f1, 1 , f 1, , and, , f1, 1 , f 1, , with the result that, , f1, f 1 , , 2 n, , 2, , (2)1/2, , (11.66), , In a similar manner, it can be shown that for the high-frequency region,, 1/, n, ), 1f2, f2 (2, , (11.67), , Note the presence of the same factor 21/, n, 1 in each equation. The magnitude of, this factor for various values of n is listed below., n, , 21/, n, , 1, , 2, 3, 4, 5, , 0.64, 0.51, 0.43, 0.39, , For n 2, consider that the upper cutoff frequency f2 0.64f2 or 64% of the value, obtained for a single stage, while f1 (1/0.64)f1 1.56f1. For n 3, f 2 0.51f2 or, approximately 12 the value of a single stage with f1 (1/0.51)f1 1.96f1 or approximately twice the single-stage value., For the RC-coupled transistor amplifier, if f2 f, or if they are close enough in, magnitude for both to affect the upper 3-dB frequency, the number of stages must be, increased by a factor of 2 when determining f2 due to the increased number of factors 1/(1 jf/fx)., A decrease in bandwidth is not always associated with an increase in the number, of stages if the midband gain can remain fixed and independent of the number of, stages. For instance, if a single-stage amplifier produces a gain of 100 with a bandwidth of 10,000 Hz, the resulting gain–bandwidth product is 102104 106. For a, two-stage system the same gain can be obtained by having two stages with a gain of, 10 since (10 10 100). The bandwidth of each stage would then increase by a factor of 10 to 100,000 due to the lower gain requirement and fixed gain–bandwidth, product of 106. Of course, the design must be such as to permit the increased bandwidth and establish the lower gain level., 11.11 Multistage Frequency Effects, , 535
Page 547 :
f, 11.12 SQUARE-WAVE TESTING, A sense for the frequency response of an amplifier can be determined experimentally, by applying a square-wave signal to the amplifier and noting the output response., The shape of the output waveform will reveal whether the high or low frequencies, are being properly amplified. The use of square-wave testing is significantly less, time-consuming than applying a series of sinusoidal signals at different frequencies, and magnitudes to test the frequency response of the amplifier., The reason for choosing a square-wave signal for the testing process is best described by examining the Fourier series expansion of a square wave composed of a, series of sinusoidal components of different magnitudes and frequencies. The summation of the terms of the series will result in the original waveform. In other words,, even though a waveform may not be sinusoidal, it can be reproduced by a series of, sinusoidal terms of different frequencies and magnitudes., The Fourier series expansion for the square wave of Fig. 11.58 is, 4, 1, 1, 1, v Vm sin 2 fst sin 2 (3fs)t sin 2 (5fs)t sin 2 (7fs)t, 3, 5, 7, , , , 1, sin 2 (9fs)t , 9, , Figure 11.58 Square wave., , (11.68), , The first term of the series is called the fundamental term and in this case has the, same frequency, fs, as the square wave. The next term has a frequency equal to three, times the fundamental and is referred to as the third harmonic. Its magnitude is onethird the magnitude of the fundamental term. The frequencies of the succeeding terms, are odd multiples of the fundamental term, and the magnitude decreases with each, higher harmonic. Figure 11.59 demonstrates how the summation of terms of a Fourier, series can result in a nonsinusoidal waveform. The generation of the square wave of, Fig. 11.58 would require an infinite number of terms. However, the summation of just, the fundamental term and the third harmonic in Fig. 11.59a clearly results in a waveform that is beginning to take on the appearance of a square wave. Including the fifth, and seventh harmonics as in Fig. 11.59b takes us a step closer to the waveform of, Fig. 11.58., Since the ninth harmonic has a magnitude greater than 10% of the fundamental, term [19(100%) 11.1%], the fundamental term through the ninth harmonic are the, major contributors to the Fourier series expansion of the square-wave function. It is, therefore reasonable to assume that if the application of a square wave of a particular frequency results in a nice clean square wave at the output, then the fundamental, , Figure 11.59 Harmonic content, of a square wave., , 536, , , , 1, sin 2 (nfs)t), n, , Chapter 11, , BJT and JFET Frequency Response
Page 548 :
f, through the ninth harmonic are being amplified without visual distortion by the amplifier. For instance, if an audio amplifier with a bandwidth of 20 kHz (audio range, is from 20 Hz to 20 kHz) is to be tested, the frequency of the applied signal should, be at least 20 kHz/9 2.22 kHz., If the response of an amplifier to an applied square wave is an undistorted replica, of the input, the frequency response (or BW) of the amplifier is obviously sufficient, for the applied frequency. If the response is as shown in Fig. 11.60a and b, the low, frequencies are not being amplified properly and the low cutoff frequency has to be, investigated. If the waveform has the appearance of Fig. 11.60c, the high-frequency, components are not receiving sufficient amplification and the high cutoff frequency, (or BW) has to be reviewed., v, , v, , T, 2, , 0, , T, , 3T, 2, , 2T, , t, , T, 2, , 0, , (a), , 3T, 2, , 2T, , t, , 3T, 2, , 2T, , t, , (b), , v, , 0, , T, , v, , T, 2, , T, , (c), , 3T, 2, , 2T, , t, , 0, , T, 2, , T, , (d), , Figure 11.60 (a) Poor low frequency, response; (b) very poor low-frequency, response; (c) poor high-frequency, response; (d) very poor high-frequency, response., , The actual high cutoff frequency (or BW) can be determined from the output, waveform by carefully measuring the rise time defined between 10% and 90% of the, peak value, as shown in Fig. 11.61. Substituting into the following equation will provide the upper cutoff frequency, and since BW fHi fLo fHi, the equation also, provides an indication of the BW of the amplifier., , Figure 11.61 Defining the rise, time and tilt of a square wave, response., , 11.12 Square-Wave Testing, , 537
Page 549 :
f, 0.35, BW fHi , tr, , (11.69), , The low cutoff frequency can be determined from the output response by carefully measuring the tilt of Fig. 11.61 and substituting into one of the following equations:, V V, (11.70), % tilt P% 100%, V, V V, tilt P , V, , (decimal form), , (11.71), , The low cutoff frequency is then determined from, P, fLo fs, , EXAMPLE 11.13, , (11.72), , The application of a 1-mV, 5-kHz square wave to an amplifier resulted in the output, waveform of Fig. 11.62., (a) Write the Fourier series expansion for the square wave through the ninth harmonic., (b) Determine the bandwidth of the amplifier., (c) Calculate the low cutoff frequency., , Solution, , , , 4 mV, (a) vi sin 2, , 1, 1, (5 103)t sin 2 (15 103)t sin 2 (25 103)t, 3, 5, 1, 1, sin 2 (35103)t sin 2 (45 103)t, 7, 9, , Figure 11.62 Example 11.13, , (b) tr 18 s 2 s 16 s, 0.35, 0.35, BW 21,875 Hz 4.4fs, 16 s, tr, V V, 50 mV 40 mV, (c) P 0.2, V, 50 mV, , , , P, 0.2, fLo fs (5 kHz) 318.31 Hz, , 11.13 PSPICE WINDOWS, The computer analysis of this chapter was integrated into the chapter for emphasis, and a clear demonstration of the power of the PSpice software package. The complete frequency response of a single-stage or multistage system can be determined in, a relatively short period of time to verify theoretical calculations or provide an immediate indication of the low and high cutoff frequencies of the system. The exercises in the chapter will provide an opportunity to apply the PSpice software package to a variety of networks., , 538, , Chapter 11, , BJT and JFET Frequency Response
Page 550 :
f, § 11.2 Logarithms, 1., , (a) Determine the common logarithm of the following numbers: 103, 50, and 0.707., , PROBLEMS, , (b) Determine the natural logarithm of the same numbers appearing in part (a)., (c) Compare the solutions of parts (a) and (b)., 2., , (a) Determine the common logarithm of the number 2.2 103., (b) Determine the natural logarithm of the number of part (a) using Eq. (11.4)., (c) Determine the natural logarithm of the number of part (a) using natural logarithms and, compare with the solution of part (b)., , 3., , Determine:, (a) 20 log10 480 using Eq. (11.6) and compare with 20 log10 5., (b) 10 log10 210 using Eq. (11.7) and compare with 10 log10 0.05., (c) log10(40)(0.125) using Eq. (11.8) and compare with log10 5., , 4., , Calculate the power gain in decibels for each of the following cases., (a) Po 100 W, Pi 5 W., (b) Po 100 mW, Pi 5 mW., (c) Po 100 W, Pi 20 W., 5. Determine GdBm for an output power level of 25 W., 6., , Two voltage measurements made across the same resistance are V1 25 V and V2 100 V., Calculate the power gain in decibels of the second reading over the first reading., , 7., , Input and output voltage measurements of Vi 10 mV and Vo 25 V are made. What is the, voltage gain in decibels?, , *, , 8., , (a) The total decibel gain of a three-stage system is 120 dB. Determine the decibel gain of, each stage if the second stage has twice the decibel gain of the first and the third has 2.7, times the decibel gain of the first., (b) Determine the voltage gain of each stage., , *, , 9. If the applied ac power to a system is 5 W at 100 mV and the output power is 48 W, determine:, (a) The power gain in decibels., (b) The voltage gain in decibels if the output impedance is 40 k., (c) The input impedance., (d) The output voltage., , § 11.4 General Frequency Considerations, 10., , Given the characteristics of Fig. 11.63, sketch:, (a) The normalized gain., (b) The normalized dB gain (and determine the bandwidth and cutoff frequencies)., , Figure 11.63 Problem 10, , Problems, , 539
Page 551 :
f, § 11.5 Low-Frequency Analysis—Bode Plot, 0.068 µ F, , +, Vi, , –, , 11., , For the network of Fig. 11.64:, (a) Determine the mathematical expression for the magnitude of the ratio Vo /Vi., (b) Using the results of part (a), determine Vo /Vi at 100 Hz, 1 kHz, 2 kHz, 5 kHz, and, 10 kHz, and plot the resulting curve for the frequency range of 100 Hz to 10 kHz. Use, a log scale., (c) Determine the break frequency., (d) Sketch the asymptotes and locate the 3-dB point., (e) Sketch the frequency response for Vo /Vi and compare to the results of part (b)., , 12., , For the network of Fig. 11.64:, (a) Determine the mathematical expression for the angle by which Vo leads Vi., (b) Determine the phase angle at f 100 Hz, 1 kHz, 2 kHz, 5 kHz, and 10 kHz, and plot, the resulting curve for the frequency range of 100 Hz to 10 kHz., (c) Determine the break frequency., (d) Sketch the frequency response of for the same frequency spectrum of part (b) and compare results., , 13., , (a), (b), (c), (d), , +, 1.2 kΩ, , Vo, , –, , Figure 11.64 Problems 11, 12,, and 32, , What frequency is 1 octave above 5 kHz?, What frequency is 1 decade below 10 kHz?, What frequency is 2 octaves below 20 kHz?, What frequency is 2 decades above 1 kHz?, , § 11.6 Low-Frequency Response — BJT Amplifier, 14., , Repeat the analysis of Example 11.9 with ro 40 k. What is the effect on Avmid , fLS , fLC ,, fLE, and the resulting cutoff frequency?, , 15., , For, (a), (b), (c), (d), (e), (f), (g), (h), , the network of Fig. 11.65:, Determine re., Find Avmid Vo /Vi., Calculate Zi., Find AvSmid Vo /Vs., Determine fLS, fLC, and fLE., Determine the low cutoff frequency., Sketch the asymptotes of the Bode plot defined by the cutoff frequencies of part (e)., Sketch the low-frequency response for the amplifier using the results of part (f)., , Figure 11.65 Problems 15, 22, and 33, , 540, , Chapter 11, , BJT and JFET Frequency Response
Page 552 :
f, *, , 16. Repeat Problem 15 for the emitter-stabilized network of Fig. 11.66., , Figure 11.66 Problems 16 and 23, , *, , 17. Repeat Problem 15 for the emitter-follower network of Fig. 11.67., 14 V, , 120 kΩ, Vi, , 1 kΩ, , +, Vs, , Cbc = 20 pF, Cbe = 30 pF, Cce = 12 pF, , β = 100, 0.1 µ F, , 0.1 µF, Zi, , CW = 8 pF, i, CWo = 10 pF, , 30 kΩ, 2.2 kΩ, , 8.2 kΩ, , –, Figure 11.67 Problems 17 and 24, , *, , 18. Repeat Problem 15 for the common-base configuration of Fig. 11.68. Keep in mind that the, common-base configuration is a noninverting network when you consider the Miller effect., , Figure 11.68 Problems 18, 25, and 34, , Problems, , 541
Page 553 :
f, § 11.7 Low-Frequency Response — FET Amplifier, 19., , For the network of Fig. 11.69:, (a) Determine VGSQ and IDQ., (b) Find gm0 and gm., (c) Calculate the midband gain of Av Vo /Vi., (d) Determine Zi., (e) Calculate Avs Vo /Vs., (f) Determine fLG, fLC, and fLS., (g) Determine the low cutoff frequency., (h) Sketch the asymptotes of the Bode plot defined by part (f)., (i) Sketch the low-frequency response for the amplifier using the results of part (f)., , Figure 11.69 Problems 19, 20,, 26, and 35, *, , 20. Repeat the analysis of Problem 19 with rd 100 k. Does it have an impact of any consequence on the results? If so, which elements?, , *, , 21. Repeat the analysis of Problem 19 for the network of Fig. 11.70. What effect did the, voltage-divider configuration have on the input impedance and the gain Avs compared to the, biasing arrangement of Fig. 11.69?, , Figure 11.70 Problems 21, and 27, , § 11.9 High-Frequency Response — BJT Amplifier, 22., , 542, , For, (a), (b), (c), , the network of Fig. 11.65:, Determine fHi and fHo., Assuming that Cbe Cbe and Cbc Cbc, find f and fT., Sketch the frequency response for the high-frequency region using a Bode plot and determine the cutoff frequency., , Chapter 11, , BJT and JFET Frequency Response
Page 554 :
f, *, , 23. Repeat the analysis of Problem 22 for the network of Fig. 11.66., , *, , 24. Repeat the analysis of Problem 22 for the network of Fig. 11.67., , *, , 25. Repeat the analysis of Problem 22 for the network of Fig. 11.68., , § 11.10 High-Frequency Response — FET Amplifier, 26. For, (a), (b), (c), (d), *, , the network of Fig. 11.69:, Determine gm0 and gm., Find Av and Avs in the mid-frequency range., Determine fHi and fHo., Sketch the frequency response for the high-frequency region using a Bode plot and determine the cutoff frequency., , 27. Repeat the analysis of Problem 26 for the network of Fig. 11.70., , § 11.11 Multistage Frequency Effects, 28. Calculate the overall voltage gain of four identical stages of an amplifier, each having a gain, of 20., 29. Calculate the overall upper 3-dB frequency for a four-stage amplifier having an individual, stage value of f2 2.5 MHz., 30. A four-stage amplifier has a lower 3-dB frequency for an individual stage of f1 40 Hz. What, is the value of f 1 for this full amplifier?, , § 11.12 Square-Wave Testing, *, , 31. The application of a 10-mV, 100-kHz square wave to an amplifier resulted in the output waveform of Fig. 11.71., (a) Write the Fourier series expansion for the square wave through the ninth harmonic., (b) Determine the bandwidth of the amplifier to the accuracy available by the waveform of, Fig. 11.71., (c) Calculate the low cutoff frequency., , Vo (mV), 100, 90, 80, 70, 60, 50, 40, 30, 20, 10, 0, , 1, , 2, , 3, , 4, , 5, , 6, , t ( µ s), , Figure 11.71 Problem 31, , § 11.13 PSpice Windows, 32. Using PSpice Windows, determine the frequency response of Vo /Vi for the high-pass filter of, Fig. 11.64., 33. Using PSpice Windows, determine the frequency response of Vo /Vs for the BJT amplifier of, Fig. 11.65., 34. Repeat Problem 33 for the network of Fig. 11.68., 35. Repeat Problem 33 for the JFET configuration of Fig. 11.69., *Please Note: Asterisks indicate more difficult problems., , Problems, , 543
Page 555 :
CHAPTER, , Linear-Digital ICs, , 17, , 17.1 INTRODUCTION, While there are many ICs containing only digital circuits and many that contain only, linear circuits, there are a number of units that contain both linear and digital circuits., Among the linear/digital ICs are comparator circuits, digital/analog converters, interface circuits, timer circuits, voltage-controlled oscillator (VCO) circuits, and phaselocked loops (PLLs)., The comparator circuit is one to which a linear input voltage is compared to another reference voltage, the output being a digital condition representing whether the, input voltage exceeded the reference voltage., Circuits that convert digital signals into an analog or linear voltage, and those that, convert a linear voltage into a digital value, are popular in aerospace equipment, automotive equipment, and compact disk (CD) players, among many others., Interface circuits are used to enable connecting signals of different digital voltage, levels, from different types of output devices, or from different impedances so that, both the driver stage and the receiver stage operate properly., Timer ICs provide linear and digital circuits to use in various timing operations,, as in a car alarm, a home timer to turn lights on or off, and a circuit in electromechanical equipment to provide proper timing to match the intended unit operation., The 555 timer has long been a popular IC unit. A voltage-controlled oscillator provides an output clock signal whose frequency can be varied or adjusted by an input, voltage. One popular application of a VCO is in a phase-locked loop unit, as used in, various communication transmitters and receivers., , 17.2 COMPARATOR UNIT OPERATION, A comparator circuit accepts input of linear voltages and provides a digital output, that indicates when one input is less than or greater than the second. A basic comparator circuit can be represented as in Fig. 17.1a. The output is a digital signal that, stays at a high voltage level when the noninverting () input is greater than the voltage at the inverting () input and switches to a lower voltage level when the noninverting input voltage goes below the inverting input voltage., Figure 17.1b shows a typical connection with one input (the inverting input in this, example) connected to a reference voltage, the other connected to the input signal, voltage. As long as Vin is less than the reference voltage level of 2 V, the output remains at a low voltage level (near 10 V). When the input rises just above 2 V, the, 721
Page 556 :
+V, −Input, , +V (+10 V), , –, Output, , +Input, , Vref, (+2 V), , –, , Vin, , +, , +, , −V (−10 V), , −V, , Figure 17.1 Comparator unit:, (a) basic unit; (b) typical, application., , Output, , (a), , (b), , output quickly switches to a high-voltage level (near 10 V). Thus the high output, indicates that the input signal is greater than 2 V., Since the internal circuit used to build a comparator contains essentially an opamp circuit with very high voltage gain, we can examine the operation of a comparator using a 741 op-amp, as shown in Fig. 17.2. With reference input (at pin 2) set, to 0 V, a sinusoidal signal applied to the noninverting input (pin 3) will cause the output to switch between its two output states, as shown in Fig. 17.2b. The input Vi going even a fraction of a millivolt above the 0-V reference level will be amplified by, the very high voltage gain (typically over 100,000) so that the output rises to its positive output saturation level and remains there while the input stays above Vref 0 V., When the input drops just below the 0-V reference level, the output is driven to its, lower saturation level and stays there while the input remains below Vref 0 V. Figure 17.2b clearly shows that the input signal is linear while the output is digital., , Figure 17.2 Operation of 741, op-amp as comparator., , In general use, the reference level need not be 0 V but can be any desired positive or negative voltage. Also, the reference voltage may be connected to either plus, or minus input and the input signal then applied to the other input., , Use of Op-Amp as Comparator, Figure 17.3a shows a circuit operating with a positive reference voltage connected to, the minus input and the output connected to an indicator LED. The reference voltage, level is set at, 10 k, Vref (12 V) 6 V, 10 k 10 k, 722, , Chapter 17, , Linear-Digital ICs
Page 557 :
+12 V, , 10 kΩ, , –, 741, 10 kΩ, , Vi, , Vo, , +, , 470 Ω, , −12 V, , LED, , LED on when, Vi goes above, Vref (= +6 V), , LED, , LED on when, Vi goes below, Vref (= +6 V), , (a), +12 V, , 10 kΩ, , Vi, , –, 741, , +, 10 kΩ, , Vo, 470 Ω, , −12 V, , (b), , Figure 17.3 A 741 op-amp, used as a comparator., , Since the reference voltage is connected to the inverting input, the output will switch, to its positive saturation level when the input, Vi, goes more positive than the 6-V, reference voltage level. The output, Vo, then drives the LED on as an indication that, the input is more positive than the reference level., As an alternative connection, the reference voltage could be connected to the noninverting input as shown in Fig. 17.3b. With this connection, the input signal going, below the reference level would cause the output to drive the LED on. The LED can, thus be made to go on when the input signal goes above or below the reference level,, depending on which input is connected as signal input and which as reference input., , Using Comparator IC Units, While op-amps can be used as comparator circuits, separate IC comparator units are, more suitable. Some of the improvements built into a comparator IC are faster switching between the two output levels, built-in noise immunity to prevent the output from, oscillating when the input passes by the reference level, and outputs capable of directly driving a variety of loads. A few popular IC comparators are covered next, describing their pin connections and how they may be used., 311 COMPARATOR, The 311 voltage comparator shown in Fig. 17.4 contains a comparator circuit that, can operate as well from dual power supplies of 15 V as from a single 5-V supply (as used in digital logic circuits). The output can provide a voltage at one of two, distinct levels or can be used to drive a lamp or a relay. Notice that the output is taken, 17.2 Comparator Unit Operation, , 723
Page 558 :
Figure 17.4, , A 311 comparator (eight-pin DIP unit)., , from a bipolar transistor to allow driving a variety of loads. The unit also has balance, and strobe inputs, the strobe input allowing gating of the output. A few examples will, show how this comparator unit can be used in some common applications., A zero-crossing detector that senses (detects) the input voltage crossing through, 0 V is shown using the 311 IC in Fig. 17.5. The inverting input is connected to ground, (the reference voltage). The input signal going positive drives the output transistor on,, with the output then going low (10 V in this case). The input signal going negative, (below 0 V) will drive the output transistor off, the output then going high (to 10, V). The output is thus an indication of whether the input is above or below 0 V. When, the input is any positive voltage, the output is low, while any negative voltage will, result in the output going to a high voltage level., , Figure 17.5, , Zero-crossing detector using a 311 IC., , Figure 17.6 shows how a 311 comparator can be used with strobing. In this example, the output will go high when the input goes above the reference level—but, only if the TTL strobe input is off (or 0 V). If the TTL strobe input goes high, it, drives the 311 strobe input at pin 6 low, causing the output to remain in the off state, (with output high) regardless of the input signal. In effect, the output remains high, 724, , Chapter 17, , Linear-Digital ICs
Page 559 :
Figure 17.6 Operation of a 311, comparator with strobe input., , unless strobed. If strobed, the output then acts normally, switching from high to low, depending on the input signal level. In operation, the comparator output will respond, to the input signal only during the time the strobe signal allows such operation., Figure 17.7 shows the comparator output driving a relay. When the input goes below 0 V, driving the output low, the relay is activated, closing the normally open (N.O.), contacts at that time. These contacts can then be connected to operate a large variety, of devices. For example, a buzzer or bell wired to the contacts can be driven on whenever the input voltage drops below 0 V. As long as the voltage is present at the input, terminal, the buzzer will remain off., , Figure 17.7, , Operation of a 311 comparator with relay output., , 339 COMPARATOR, The 339 IC is a quad comparator containing four independent voltage comparator circuits connected to external pins as shown in Fig. 17.8. Each comparator has inverting and noninverting inputs and a single output. The supply voltage applied to a, pair of pins powers all four comparators. Even if one wishes to use one comparator,, all four will be drawing power., 17.2 Comparator Unit Operation, , 725
Page 560 :
Figure 17.8, IC (339)., , Quad comparator, , To see how these comparator circuits can be used, Fig. 17.9 shows one of the 339, comparator circuits connected as a zero-crossing detector. Whenever the input signal, goes above 0 V, the output switches to V. The input switches to V only when the, input goes below 0 V., A reference level other than 0 V can also be used, and either input terminal could, be used as the reference, the other terminal then being connected to the input signal., The operation of one of the comparator circuits is described next., V + (5 V), , Vi, , 3, , 5, , 5.1 kΩ, , +, , Input, Vi, , Time, , 2, Output, Vo, , 339, 4, Vref = 0 V, , –, , 12, V − (−5 V), , Vo, V+, , (a), Time, , V−, , 726, , Figure 17.9, , Operation of one 339 comparator circuit as a zero-crossing detector., , Chapter 17, , Linear-Digital ICs
Page 561 :
The differential input voltage (difference voltage across input terminals) going, positive drives the output transistor off (open circuit), while a negative differential input voltage drives the output transistor on—the output then at the supply low level., If the negative input is set at a reference level Vref, the positive input goes above, Vref and results in a positive differential input with output driven to the open-circuit, state. When the noninverting input goes below Vref, resulting in a negative differential input, the output will be driven to V., If the positive input is set at the reference level, the inverting input going below, Vref results in the output open circuit while the inverting input going above Vref results in the output at V. This operation is summarized in Fig. 17.10., V+, V+, Vref, , +, , Input, , +, Input < Vref ← output open circuit, , Input > Vref ← output open circuit, 339, Vref, , 339, , Input < Vref ← output =V −, , –, , Input, V−, , ← output, , =V−, , –, V−, , (a), , Figure 17.10, input., , Input > Vref, , (b), , Operation of a 339 comparator circuit with reference input: (a) minus input; (b) plus, , Since the output of one of these comparator circuits is from an open-circuit collector, applications in which the outputs from more than one circuit can be wire-ORed, are possible. Figure 17.11 shows two comparator circuits connected with common, output and also with common input. Comparator 1 has a 5-V reference voltage in+9 V, , 4, , –, , 5.1 kΩ, , 3, 2, , 7.5 kΩ, , Output, , 1, 5, , +, 9.1 kΩ, Vref1 ≅ +5 V, +9 V, 8.2 kΩ, Vref2 ≅ +1 V, , +5 V, , 6, , –, , Output high, , 1, , 1 kΩ, , 2, , +1 V, , 7, , +, , Output low, , Output low, , 12, , Figure 17.11 Operation of two, 339 comparator circuits as a, window detector., , Input, , 17.2 Comparator Unit Operation, , 727
Page 562 :
put connected to the noninverting input. The output will be driven low by comparator 1 when the input signal goes above 5 V. Comparator 2 has a reference voltage, of 1 V connected to the inverting input. The output of comparator 2 will be driven, low when the input signal goes below 1 V. In total, the output will go low whenever the input is below 1 V or above 5 V, as shown in Fig. 17.11, the overall operation being that of a voltage window detector. The high output indicates that the input is within a voltage window of 1 to 5 V (these values being set by the reference, voltage levels used)., , 17.3 DIGITAL–ANALOG CONVERTERS, Many voltages and currents in electronics vary continuously over some range of values. In digital circuitry the signals are at either one of two levels, representing the binary values of 1 or zero. An analog–digital converter (ADC) obtains a digital value, representing an input analog voltage, while a digital–analog converter (DAC) changes, a digital value back into an analog voltage., , Digital-to-Analog Conversion, LADDER NETWORK CONVERSION, Digital-to-analog conversion can be achieved using a number of different methods. One popular scheme uses a network of resistors, called a ladder network. A ladder network accepts inputs of binary values at, typically, 0 V or Vref and provides an, output voltage proportional to the binary input value. Figure 17.12a shows a ladder, network with four input voltages, representing 4 bits of digital data and a dc voltage, output. The output voltage is proportional to the digital input value as given by the, relation, D0 20 D1 21 D2 22 D3 23, Vref, Vo , 24, , Figure 17.12 Four-stage ladder network used as a DAC: (a) basic circuit;, (b) circuit example with 0110 input., , 728, , Chapter 17, , Linear-Digital ICs, , (17.1)
Page 563 :
In the example shown in Fig. 17.12b, the output voltage resulting should be, 01121408, Vo (16 V) 6 V, 16, Therefore, 01102, digital, converts to 6 V, analog., The function of the ladder network is to convert the 16 possible binary values, from 0000 to 1111 into one of 16 voltage levels in steps of Vref/16. Using more sections of ladder allows having more binary inputs and greater quantization for each, step. For example, a 10-stage ladder network could extend the number of voltage steps, or the voltage resolution to Vref/210 or Vref/1024. A reference voltage of Vref 10 V, would then provide output voltage steps of 10 V/1024 or approximately 10 mV. More, ladder stages provide greater voltage resolution. In general, the voltage resolution for, n ladder stages is, V ef, r, 2n, , (17.2), , Figure 17.13 shows a block diagram of a typical DAC using a ladder network., The ladder network, referred in the diagram as an R-2R ladder, is sandwiched between the reference current supply and current switches connected to each binary input, the resulting output current proportional to the input binary value. The binary input turns on selected legs of the ladder, the output current being a weighted summing, of the reference current. Connecting the output current through a resistor will produce an analog voltage, if desired., , Digital inputs, , Current switches, , Io, , R-2 R ladder, , Vref, , Reference, current, , Figure 17.13 DAC IC using, R-2R ladder network., , Analog-to-Digital Conversion, DUAL-SLOPE CONVERSION, A popular method for converting an analog voltage into a digital value is the dualslope method. Figure 17.14a shows a block diagram of the basic dual-slope converter., The analog voltage to be converted is applied through an electronic switch to an integrator or ramp-generator circuit (essentially a constant current charging a capacitor, to produce a linear ramp voltage). The digital output is obtained from a counter operated during both positive and negative slope intervals of the integrator., The method of conversion proceeds as follows. For a fixed time interval (usually, the full count range of the counter), the analog voltage connected to the integrator, raises the voltage at the comparator input to some positive level. Figure 17.14b shows, that at the end of the fixed time interval the voltage from the integrator is greater for, the larger input voltage. At the end of the fixed count interval, the count is set to zero, and the electronic switch connects the integrator to a reference or fixed input voltage., 17.3, , Digital-Analog Converters, , 729
Page 564 :
Analog input, , Digital input, , Integrator, Comparator, , Reference, input, , Count, pulses, , Stop, count, , Control, logic, , Digital, counter, , Clear, pulse, , Vref, , Count over, Clock, , Linear, , Digital, , Linear/Digital, (a), , L, , ar, , r, ge, , in, , pu, , ut, Inp, , o, tv, , lta, , ge, , Fixed, discharge, rate, , e, , tag, , vol, , e, , put voltag, , Smaller in, , Smaller, digital, count, , Digital, count, , Larger, digital, count, , Fixed time, interval, Count interval, (b), , Figure 17.14 Analog-to-digital conversion using dual-slope method: (a) logic diagram;, (b) waveform., , The integrator output (or capacitor input) then decreases at a fixed rate. The counter, advances during this time, while the integrator’s output decreases at a fixed rate until it drops below the comparator reference voltage, at which time the control logic, receives a signal (the comparator output) to stop the count. The digital value stored, in the counter is then the digital output of the converter., Using the same clock and integrator to perform the conversion during positive and, negative slope intervals tends to compensate for clock frequency drift and integrator, accuracy limitations. Setting the reference input value and clock rate can scale the, counter output as desired. The counter can be a binary, BCD, or other form of digital counter, if desired., LADDER-NETWORK CONVERSION, Another popular method of analog-to-digital conversion uses a ladder network, along with counter and comparator circuits (see Fig. 17.15). A digital counter advances from a zero count while a ladder network driven by the counter outputs a staircase voltage, as shown in Fig. 17.15b, which increases one voltage increment for each, count step. A comparator circuit, receiving both staircase voltage and analog input, 730, , Chapter 17, , Linear-Digital ICs
Page 565 :
Figure 17.15 Analog-to-digital conversion using ladder network: (a) logic diagram; (b) waveform., , voltage, provides a signal to stop the count when the staircase voltage rises above the, input voltage. The counter value at that time is the digital output., The amount of voltage change stepped by the staircase signal depends on the number of count bits used. A 12-stage counter operating a 12-stage ladder network using, a reference voltage of 10 V would step each count by a voltage of, V f, 10 V, 1re, 2 2.4 mV, 2, 4096, This would result in a conversion resolution of 2.4 mV. The clock rate of the counter, would affect the time required to carry out a conversion. A clock rate of 1 MHz operating a 12-stage counter would need a maximum conversion time of, 4096 1 s 4096 s 4.1 ms, The minimum number of conversions that could be carried out each second would, then be, number of conversions 1/4.1 ms 244 conversions/second, Since on the average, with some conversions requiring little count time and others, near maximum count time, a conversion time of 4.1 ms/2 2.05 ms would be needed,, and the average number of conversions would be 2 244 488 conversions/second., A slower clock rate would result in fewer conversions per second. A converter using, fewer count stages (and less conversion resolution) would carry out more conversions, per second. The conversion accuracy depends on the accuracy of the comparator., 17.3, , Digital-Analog Converters, , 731
Page 566 :
17.4 TIMER IC UNIT OPERATION, Another popular analog–digital integrated circuit is the versatile 555 timer. The IC is, made of a combination of linear comparators and digital flip-flops as described in, Fig. 17.16. The entire circuit is usually housed in an 8-pin package as specified in, Fig. 17.16. A series connection of three resistors sets the reference voltage levels to, the two comparators at 2VCC/3 and VCC/3, the output of these comparators setting or, resetting the flip-flop unit. The output of the flip-flop circuit is then brought out, through an output amplifier stage. The flip-flop circuit also operates a transistor inside the IC, the transistor collector usually being driven low to discharge a timing capacitor., VCC, , Threshold, 6, , 8, R, Control, voltage, , +, ( 23 VCC), , 5, R, , –, , 1, Output, stage, , F/F, ( 13 VCC), , Discharge, , –, , R, , Figure 17.16, timer IC., , Details of 555, , Output, 7, , +, 2, , 1, , 3, , 2, Trigger, input, , 4, Reset, , Vref, , Astable Operation, One popular application of the 555 timer IC is as an astable multivibrator or clock, circuit. The following analysis of the operation of the 555 as an astable circuit includes details of the different parts of the unit and how the various inputs and outputs are utilized. Figure 17.17 shows an astable circuit built using an external resistor and capacitor to set the timing interval of the output signal., Figure 17.17 Astable, multivibrator using 555 IC., , 732
Page 567 :
Capacitor C charges toward VCC through external resistors RA and RB. Referring, to Fig. 17.17, the capacitor voltage rises until it goes above 2VCC/3. This voltage is, the threshold voltage at pin 6, which drives comparator 1 to trigger the flip-flop so, that the output at pin 3 goes low. In addition, the discharge transistor is driven on,, causing the output at pin 7 to discharge the capacitor through resistor RB. The capacitor voltage then decreases until it drops below the trigger level (VCC/3). The flipflop is triggered so that the output goes back high and the discharge transistor is turned, off, so that the capacitor can again charge through resistors RA and RB toward VCC., Figure 17.18a shows the capacitor and output waveforms resulting from the astable, circuit. Calculation of the time intervals during which the output is high and low can, be made using the relations, Thigh 0.7(RA RB)C, , (17.3), , Tlow 0.7RBC, , (17.4), , T period Thigh Tlow, , (17.5), , The total period is, , The frequency of the astable circuit is then calculated using*, 1, 1.44, f , T, (RA 2RB)C, , Figure 17.18, , (17.6), , Astable multivibrator for Example 17.1: (a) circuit; (b) waveforms., , *The period can be directly calculated from, T 0.693(RA 2RB)C 0.7(RA 2RB)C, and the frequency from, 1.44, f , (RA 2RB)C, , 17.4, , Timer IC Unit Operation, , 733
Page 568 :
EXAMPLE 17.1, , Determine the frequency and draw the output waveform for the circuit of Fig. 17.18a., , Solution, Using Eqs. (17.3) through (17.6) yields, Thigh 0.7(RA RB)C 0.7(7.5 103 7.5 103)(0.1 106), 1.05 ms, Tlow 0.7RBC 0.7(7.5 103)(0.1 106) 0.525 ms, T Thigh Tlow 1.05 ms 0.525 ms 1.575 ms, 1, 1, f , 635 Hz, T, 1.575 103, The waveforms are drawn in Fig. 17.18b., , Monostable Operation, The 555 timer can also be used as a one-shot or monostable multivibrator circuit, as, shown in Fig. 17.19. When the trigger input signal goes negative, it triggers the oneshot, with output at pin 3 then going high for a time period, Thigh 1.1RAC, , (17.7), , Referring back to Fig. 17.16, the negative edge of the trigger input causes comparator 2 to trigger the flip-flop, with the output at pin 3 going high. Capacitor C charges, toward VCC through resistor RA. During the charge interval, the output remains high., When the voltage across the capacitor reaches the threshold level of 2VCC/3, comparator 1 triggers the flip-flop, with output going low. The discharge transistor also, goes low, causing the capacitor to remain at near 0 V until triggered again., Figure 17.19b shows the input trigger signal and the resulting output waveform, for the 555 timer operated as a one-shot. Time periods for this circuit can range from, microseconds to many seconds, making this IC useful for a range of applications., , Figure 17.19, , 734, , Chapter 17, , Operation of 555 timer as one-shot: (a) circuit; (b) waveforms., , Linear-Digital ICs
Page 569 :
Determine the period of the output waveform for the circuit of Fig. 17.20 when triggered by a negative pulse., , EXAMPLE 17.2, , Figure 17.20 Monostable circuit for Example 17.2., , Solution, Using Eq. (17.7), we obtain, Thigh 1.1RAC 1.1(7.5 103)(0.1 106) 0.825 ms, , 17.5 VOLTAGE-CONTROLLED, OSCILLATOR, A voltage-controlled oscillator (VCO) is a circuit that provides a varying output signal (typically of square-wave or triangular-wave form) whose frequency can be adjusted over a range controlled by a dc voltage. An example of a VCO is the 566 IC, unit, which contains circuitry to generate both square-wave and triangular-wave signals whose frequency is set by an external resistor and capacitor and then varied by, an applied dc voltage. Figure 17.21a shows that the 566 contains current sources to, charge and discharge an external capacitor C1 at a rate set by external resistor R1 and, the modulating dc input voltage. A Schmitt trigger circuit is used to switch the current sources between charging and discharging the capacitor, and the triangular voltage developed across the capacitor and square wave from the Schmitt trigger are provided as outputs through buffer amplifiers., Figure 17.21b shows the pin connection of the 566 unit and a summary of formula and value limitations. The oscillator can be programmed over a 10-to-1 frequency range by proper selection of an external resistor and capacitor, and then modulated over a 10-to-1 frequency range by a control voltage, VC., A free-running or center-operating frequency, fo, can be calculated from, 2, V VC, fo , , R1C1, V, , , , , , (17.8), , with the following practical circuit value restrictions:, 1. R1 should be within the range 2 k R1 20 k., 2. VC should be within range 34V VC V., 17.5, , Voltage-Controlled Oscillator, , 735
Page 570 :
Figure 17.21 A 566 function, generator: (a) block diagram;, (b) pin configuration and summary, of operating data., , 3. fo should be below 1 MHz., 4. V should range between 10 V and 24 V., Figure 17.22 shows an example in which the 566 function generator is used to, provide both square-wave and triangular-wave signals at a fixed frequency set by R1,, C1, and VC. A resistor divider R2 and R3 sets the dc modulating voltage at a fixed, value, , Figure 17.22 Connection of, 566 VCO unit., , 736, , Chapter 17, , Linear-Digital ICs
Page 571 :
R3, 10 k, VC , V (12 V) 10.4 V, R2 R3, 1.5 k 10 k, (which falls properly in the voltage range 0.75V 9 V and V 12 V). Using Eq., (17.8) yields, 12 10.4, 2, 32.5 kHz, fo , (10 103)(820 1012), 12, , , , , , The circuit of Fig. 17.23 shows how the output square-wave frequency can be adjusted using the input voltage, VC, to vary the signal frequency. Potentiometer R3 allows varying VC from about 9 V to near 12 V, over the full 10-to-1 frequency range., With the potentiometer wiper set at the top, the control voltage is, 5 k 18 k, R3 R4, (V) (12 V) 11.74 V, VC , 510, , 5 k 18 k, R2 R3 R4, resulting in a lower output frequency of, 2, 12 11.74, 19.7 kHz, fo , (10 103)(220 1012), 12, , , , , , Figure 17.23 Connection of, 566 as a VCO unit., , With the wiper arm of R3 set at the bottom, the control voltage is, 18 k, R4, , ) (12 V) 9.19 V, VC (V, 510 5 k 18 k, R2 R3 R4, resulting in an upper frequency of, 2, 12 9.19, 212.9 kHz, fo , (10 103)(220 1012), 12, , , , , , The frequency of the output square wave can then be varied using potentiometer R3, over a frequency range of at least 10 to 1., Rather than varying a potentiometer setting to change the value of VC, an input, modulating voltage, Vin, can be applied as shown in Fig. 17.24. The voltage divider, sets VC at about 10.4 V. An input ac voltage of about 1.4 V peak can drive VC around, the bias point between voltages of 9 and 11.8 V, causing the output frequency to vary, over about a 10-to-1 range. The input signal Vin thus frequency-modulates the output, voltage around the center frequency set by the bias value of VC 10.4 V ( fo , 121.2 kHz)., 17.5, , Voltage-Controlled Oscillator, , 737
Page 572 :
Figure 17.24 Operation of, VCO with frequency-modulating, input., , 17.6 PHASE-LOCKED LOOP, A phase-locked loop (PLL) is an electronic circuit that consists of a phase detector,, a low-pass filter, and a voltage-controlled oscillator connected as shown in Fig. 17.25., Common applications of a PLL include: (1) frequency synthesizers that provide multiples of a reference signal frequency [e.g., the carrier frequency for the multiple channels of a citizens’ band (CB) unit or marine-radio-band unit can be generated using, a single-crystal-controlled frequency and its multiples generated using a PLL]; (2), FM demodulation networks for FM operation with excellent linearity between the input signal frequency and the PLL output voltage; (3) demodulation of the two data, transmission or carrier frequencies in digital-data transmission used in frequency-shift, keying (FSK) operation; and (4) a wide variety of areas including modems, telemetry receivers and transmitters, tone decoders, AM detectors, and tracking filters., An input signal, Vi, and that from a VCO, Vo, are compared by a phase comparator, (refer to Fig. 17.25) providing an output voltage, Ve, that represents the phase difference between the two signals. This voltage is then fed to a low-pass filter that pro-, , Figure 17.25, , 738, , Chapter 17, , Block diagram of basic phase-locked loop (PLL)., , Linear-Digital ICs
Page 573 :
vides an output voltage (amplified if necessary) that can be taken as the output voltage from the PLL and is used internally as the voltage to modulate the VCO’s frequency. The closed-loop operation of the circuit is to maintain the VCO frequency, locked to that of the input signal frequency., , Basic PLL Operation, The basic operation of a PLL circuit can be explained using the circuit of Fig. 17.25, as reference. We will first consider the operation of the various circuits in the phaselocked loop when the loop is operating in lock (the input signal frequency and the, VCO frequency are the same). When the input signal frequency is the same as that, from the VCO to the comparator, the voltage, Vd, taken as output is the value needed, to hold the VCO in lock with the input signal. The VCO then provides output of a, fixed-amplitude square-wave signal at the frequency of the input. Best operation is, obtained if the VCO center frequency, fo, is set with the dc bias voltage midway in, its linear operating range. The amplifier allows this adjustment in dc voltage from that, obtained as output of the filter circuit. When the loop is in lock, the two signals to, the comparator are of the same frequency, although not necessarily in phase. A fixed, phase difference between the two signals to the comparator results in a fixed dc voltage to the VCO. Changes in the input signal frequency then result in change in the, dc voltage to the VCO. Within a capture-and-lock frequency range, the dc voltage, will drive the VCO frequency to match that of the input., While the loop is trying to achieve lock, the output of the phase comparator contains frequency components at the sum and difference of the signals compared. A lowpass filter passes only the lower-frequency component of the signal so that the loop, can obtain lock between input and VCO signals., Owing to the limited operating range of the VCO and the feedback connection of, the PLL circuit, there are two important frequency bands specified for a PLL. The, capture range of a PLL is the frequency range centered about the VCO free-running, frequency, fo, over which the loop can acquire lock with the input signal. Once the, PLL has achieved capture, it can maintain lock with the input signal over a somewhat, wider frequency range called the lock range., , Applications, The PLL can be used in a wide variety of applications, including (1) frequency demodulation, (2) frequency synthesis, and (3) FSK decoders. Examples of each of these, follow., FREQUENCY DEMODULATION, FM demodulation or detection can be directly achieved using the PLL circuit. If, the PLL center frequency is selected or designed at the FM carrier frequency, the filtered or output voltage of the circuit of Fig. 17.25 is the desired demodulated voltage, varying in value proportional to the variation of the signal frequency. The PLL, circuit thus operates as a complete intermediate-frequency (IF) strip, limiter, and demodulator as used in FM receivers., One popular PLL unit is the 565, shown in Fig. 17.26a. The 565 contains a phase, detector, amplifier, and voltage-controlled oscillator, which are only partially connected internally. An external resistor and capacitor, R1 and C1, are used to set the, free-running or center frequency of the VCO. Another external capacitor, C2, is used, to set the low-pass filter passband, and the VCO output must be connected back as, input to the phase detector to close the PLL loop. The 565 typically uses two power, supplies, V and V., 17.6, , Phase-Locked Loop, , 739
Page 574 :
V+, 10, , 565, , C2, , 2, Input, , 3.6 kΩ, , Phase, detector, , 3, , Amp., , 5, 4, , 7, , Demodulated, output, , 6, , Reference, output, , VCO, , Output, , 9, , 8, R1, , 1, V−, , C1, , (a), , +6 V, 10, C2, 330 pF, Demodulated, output, , 2, , FM signal, input, , 3.6 kΩ, , Phase, detector, , 3, , Amp., , 7, , 5, , Reference, output, , 6, 4, , VCO, , Output, 8, R1, 10 kΩ, , V7, , +6 V, , +5.3 V, , 9, , C1, 220 pF, , 1, fo =, , 0.3, R1 C1, , −6 V, (b), , +5 V, +4.7 V, , Frequency, fo, fL, fL, (= 136.36 kHz) fo +, 2, 2, (= 45.45 kHz), (= 227.27 kHz), ± fL, (± 181.82 kHz), fo −, , Figure 17.26 Phase-locked loop, (PLL): (a) basic block diagram:, (b) PLL connected as a frequency, demodulator: (c) output voltage, vs. frequency plot., , (c), , Figure 17.26b shows the PLL connected to work as an FM demodulator. Resistor R1 and capacitor C1 set the free-running frequency, fo,, 0.3, fo , R1C1, , (17.9), , 0.3, , 136.36 kHz, 3, (10 10 )(220 1012), with limitation 2 k, , R1, , 20 k. The lock range is, 8f, fL o, V, 8(136.36 103), 181.8 kHz, 6, , 740, , Chapter 17, , Linear-Digital ICs
Page 575 :
for supply voltages V 6 V. The capture range is, , , 2 (181.8 10 ), 1, 156.1 kHz, (3.6 10 )(330 10 ), 2 , 1, 2 fL, fC , 2, R2C2, 3, , 12, , 3, , The signal at pin 4 is a 136.36-kHz square wave. An input within the lock range of, 181.8 kHz will result in the output at pin 7 varying around its dc voltage level set, with input signal at fo. Figure 17.26c shows the output at pin 7 as a function of the, input signal frequency. The dc voltage at pin 7 is linearly related to the input signal, frequency within the frequency range fL 181.8 kHz around the center frequency, 136.36 kHz. The output voltage is the demodulated signal that varies with frequency, within the operating range specified., FREQUENCY SYNTHESIS, A frequency synthesizer can be built around a PLL as shown in Fig. 17.27. A frequency divider is inserted between the VCO output and the phase comparator so that, the loop signal to the comparator is at frequency fo while the VCO output is Nfo. This, output is a multiple of the input frequency as long as the loop is in lock. The input, signal can be stabilized at f1 with the resulting VCO output at Nf1 if the loop is set, , Input, f1, , Phase, comparator, , Low-pass, filter, , Amp., , fo, , ÷N, , VCO, Output, Nfo, (a), +5 V, , C2, 330 pF, R1, 10 kΩ, , 5.1 kΩ, 8, , 7, , 10, 4, , 2, , 14, , Nfo, , 565, Vi, f1, , Input A, , 10 kΩ, , 5, , 5, , 3, 9, , 9, , 1, , 7490, , C1, 220 pF, −5 V, , 1 12, , 8, , QA ÷ 2, QB ÷ 4, QC ÷ 8, , QD ÷ 16, 10, 11, 3, 6, 2, 7, R0 (1) R0 (2) R 9 (1) R 9 (2), fo, , (b), , Figure 17.27, , Frequency synthesizer: (a) block diagram; (b) implementation using 565 PLL unit., , 17.6, , Phase-Locked Loop, , 741
Page 576 :
up to lock at the fundamental frequency (when fo f1). Figure 17.27b shows an example using a 565 PLL as frequency multiplier and a 7490 as divider. The input Vi, at frequency f1 is compared to the input (frequency fo) at pin 5. An output at Nfo (4fo, in the present example) is connected through an inverter circuit to provide an input, at pin 14 of the 7490, which varies between 0 and 5 V. Using the output at pin 9,, which is divided by 4 from that at the input to the 7490, the signal at pin 4 of the, PLL is four times the input frequency as long as the loop remains in lock. Since the, VCO can vary over only a limited range from its center frequency, it may be necessary to change the VCO frequency whenever the divider value is changed. As long as, the PLL circuit is in lock, the VCO output frequency will be exactly N times the input frequency. It is only necessary to readjust fo to be within the capture-and-lock, range, the closed loop then resulting in the VCO output becoming exactly Nf1 at lock., FSK DECODERS, An FSK (frequency-shift keyed) signal decoder can be built as shown in Fig. 17.28., The decoder receives a signal at one of two distinct carrier frequencies, 1270 Hz or, 1070 Hz, representing the RS-232C logic levels or mark (5 V) or space (14 V),, respectively. As the signal appears at the input, the loop locks to the input frequency, and tracks it between two possible frequencies with a corresponding dc shift at the, output., , Figure 17.28 Connection of, 565 as FSK decoder., , The RC ladder filter (three sections of C 0.02 F and R 10 k) is used to, remove the sum frequency component. The free-running frequency is adjusted with, R1 so that the dc voltage level at the output (pin 7) is the same as that at pin 6. Then, an input at frequency 1070 Hz will drive the decoder output voltage to a more positive voltage level, driving the digital output to the high level (space or 14 V). An, input at 1270 Hz will correspondingly drive the 565 dc output less positive with the, digital output, which then drops to the low level (mark or 5 V)., , 17.7 INTERFACING CIRCUITRY, Connecting different types of circuits, either in digital or analog circuits, may require, some sort of interfacing circuit. An interface circuit may be used to drive a load or to, obtain a signal as a receiver circuit. A driver circuit provides the output signal at a, 742, , Chapter 17, , Linear-Digital ICs
Page 577 :
voltage or current level suitable to operate a number of loads, or to operate such devices as relays, displays, or power units. A receiver circuit essentially accepts an input signal, providing high input impedance to minimize loading of the input signal., Furthermore, the interface circuits may include strobing, which provides connecting, the interface signals during specific time intervals established by the strobe., Figure 17.29a shows a dual-line driver, each driver accepting input of TTL signals, providing output capable of driving TTL or MOS device circuits. This type of, interface circuit comes in various forms, some as inverting and others as noninverting units. The circuit of Fig. 17.29b shows a dual-line receiver having both inverting, and noninverting inputs so that either operating condition can be selected. As an example, connection of an input signal to the inverting input would result in an inverted, output from the receiver unit. Connecting the input to the noninverting input would, provide the same interfacing except that the output obtained would have the same polarity as the received signal. The driver-receiver unit of Fig. 17.29 provides an output, when the strobe signal is present (high in this case)., , Figure 17.29 Interface units: (a) dual-line drivers (SN75150); (b) dual-line, receivers (SN75152)., , Another type of interface circuit is that used to connect various digital input and, output units, signals with devices such as keyboards, video terminals, and printers., One of the EIA electronic industry standards is referred to as RS-232C. This standard, states that a digital signal represents a mark (logic-1) and a space (logic-0). The definitions of mark and space vary with the type of circuit used (although a full reading, of the standard will spell out the acceptable limits of mark and space signals)., 17.7 Interfacing Circuitry, , 743
Page 578 :
RS-232C-to-TTL Converter, For TTL circuits, 5 V is a mark and 0 V is a space. For RS-232C, a mark could be, 12 V and a space 12 V. Figure 17.30a provides a tabulation of some mark and, space definitions. For a unit having outputs defined by RS-232C that is to operate, into another unit operating with a TTL signal level, an interface circuit as shown in, Fig. 17.30b could be used. A mark output from the driver (at 12 V) would be clipped, by the diode so that the input to the inverter circuit is near 0 V, resulting in an output of 5 V (TTL mark). A space output at 12 V would drive the inverter output, low for a 0-V output (a space)., , Figure 17.30, , Interfacing signal standards and converter circuits., , Another example of an interface circuit converts the signals from a TTY current, loop into TTL levels as shown in Fig. 17.30c. An input mark results when 20 mA of, current is drawn from the source through the output line of the teletype (TTY). This, current then goes through the diode element of an opto-isolator, driving the output, transistor on. The input to the inverter going low results in a 5-V signal from the, 7407 inverter output so that a mark from the teletype results in a mark to the TTL, input. A space from the teletype current loop provides no current, with the optoisolator transistor remaining off and the inverter output then 0 V, which is a TTL, space signal., Another means of interfacing digital signals is made using open-collector output, or tri-state output. When a signal is output from a transistor collector (see Fig. 17.31), that is not connected to any other electronic component, the output is open-collector., This permits connecting a number of signals to the same wire or bus. Any transistor, going on then provides a low output voltage, while all transistors remaining off provide a high output voltage., 744, , Chapter 17, , Linear-Digital ICs
Page 579 :
Figure 17.31, , Connections to data lines: (a) open-collector output; (b) tri-state output., , 17.8 PSPICE WINDOWS, Many of the practical op-amp applications covered in this chapter can be analyzed, using PSpice. Analysis of various problems can display the resulting dc bias, or one, can use PROBE to display resulting waveforms., , Program 17.1—Comparator Circuit Used to Drive an LED, Using Design Center, draw the circuit of a comparator circuit with output driving an, LED indicator as shown in Fig. 17.32. To be able to view the magnitude of the dc, output voltage, place a VPRINT1 component at Vo with DC and MAG selected. To, view the dc current through the LED, place an IPRINT component in series with the, LED current meter as shown in Fig. 17.32. The Analysis Setup provides for a dc, sweep as shown in Fig. 17.33. The DC Sweep is set, as shown, for Vi from 4 to 8 V, in 1-V steps. After running the simultation, some of the resulting analysis output obtained is shown in Fig. 17.34., , Figure 17.32, , Comparator circuit used to drive an LED., , 17.8, , PSpice Windows, , 745
Page 580 :
Figure 17.33, , Analysis Setup for a dc sweep of the circuit of Fig. 17.32., , The circuit of Fig. 17.32 shows a voltage divider which provides 6 V to the minus input so that any input (Vi) below 6 V will result in the output at the minus saturation voltage (near 10 V). Any input above 6 V results in the output going to, the positive saturation level (near 10 V). The LED will therefore be driven on by, any input above the reference level of 6 V and left off by any input below 6 V., The listing of Fig. 17.34 shows a table of the output voltage and a table of the LED, current for inputs from 4 to 8 V. The table shows that the LED current is nearly 0 for, inputs up to 6 V and that a current of about 20 mA lights the LED for inputs at 6, V or above., , Program 17.2—Comparator Operation, , Figure 17.34 Analysis output, (edited) for circuit of Fig. 17.32., , The operation of a comparator IC can be demonstrated using a 741 op-amp as shown, in Fig. 17.35. The input is a 5 V, peak sinusoidal signa. The Analysis Setup provides, for Transient analysis with Print Step of 20 ns and Final Time of 3 ms. Since the, input signal is applied to the noninverting input, the output is in-phase with the input. When the input goes above 0 V, the output goes to the positive saturation level,, , 746, , Chapter 17, , Linear-Digital ICs
Page 581 :
Figure 17.35, comparator., , Schematic for a, , near 5 V. When the input goes below 0 V, the output goes to the negative saturation level—this being 0 V since the minus voltage input is set to that value. Figure, 17.36 shows a PROBE output of input and output voltages., , Figure 17.36, , Probe output for the comparator of Fig. 17.35., , Program 17.3—Operation of 555 Timer as Oscillator, Figure 17.37 shows a 555 timer connected as an oscillator. Equations (17.3) and (17.4), can be used to calculate the charge and discharge times as follows:, Thigh 0.7(RA RB)C 0.7(7.5 k 7.15 k)(0.1 F) 1.05 ms, Tlow 0.7RBC 0.7(7.5 k)(0.1 F) 0.525 ms, , Figure 17.37, , Schematic of a 555 timer oscillator., , 17.8, , PSpice Windows, , 747
Page 582 :
Figure 17.38, , Probe output for the 555 oscillator of Fig. 17.37., , The resulting trigger and output waveforms are shown in Fig. 17.38. When the trigger charges to the upper trigger level, the output goes to the low output level of 0 V., The output stays low until the trigger input discharges to the low trigger level, at which, time the output goes to the high level of 5 V., , PROBLEMS, , § 17.2 Comparator Unit Operation, 1. Draw the diagram of a 741 op-amp operated from 15-V supplies with Vi() 0 V and, Vi() 5 V. Include terminal pin connections., 2. Sketch the output waveform for the circuit of Fig. 17.39., 3. Draw a circuit diagram of a 311 op-amp showing an input of 10 V rms applied to the inverting input and the plus input to ground. Identify all pin numbers., 4. Draw the resulting output waveform for the circuit of Fig. 17.40., , Figure 17.39, , Problem 2, , Figure 17.40, , Problem 4, , 5. Draw the circuit diagram of a zero-crossing detector using a 339 comparator stage with 12-V, supplies., , 748, , Chapter 17, , Linear-Digital ICs
Page 583 :
6. Sketch the output waveform for the circuit of Fig. 17.41., , Figure 17.41, *, , Problem 6, , 7. Describe the operation of the circuit in Fig. 17.42., , Figure 17.42, , Problem 7, , § 17.3 Digital–Analog Converters, 8. Sketch a five-stage ladder network using 15-k and 30-k resistors., 9. For a reference voltage of 16 V, calculate the output voltage for an input of 11010 to the circuit of Problem 8., 10. What voltage resolution is possible using a 12-stage ladder network with a 10-V reference voltage?, Problems, , 749
Page 584 :
11. For a dual-slope converter, describe what occurs during the fixed time interval and the count, interval., 12. How many count steps occur using a 12-stage digital counter at the output of an ADC?, 13. What is the maximum count interval using a 12-stage counter operated at a clock rate of, 20 MHz?, , § 17.4 Timer IC Unit Operation, 14. Sketch the circuit of a 555 timer connected as an astable multivibrator for operation at, 350 kHz. Determine the value of capacitor, C, needed using RA RB 7.5 k., 15. Draw the circuit of a one-shot using a 555 timer to provide one time period of 20 s. If RA , 7.5 k, what value of C is needed?, 16. Sketch the input and output waveforms for a one-shot using a 555 timer triggered by a 10-kHz, clock for RA 5.1 k and C 5 nF., , § 17.5 Voltage-Controlled Oscillator, 17. Calculate the center frequency of a VCO using a 566 IC as in Fig. 17.22 for R1 4.7 k,, R2 1.8 k, R3 11 k, and C1 0.001 F., *, , 18. What frequency range results in the circuit of Fig. 17.23 for C1 0.001 F?, 19. Determine the capacitor needed in the circuit of Fig. 17.22 to obtain a 200-kHz output., , § 17.6 Phase-Locked Loop, 20. Calculate the VCO free-running frequency for the circuit of Fig. 17.26b with R1 4.7 k and, C1 0.001 F., 21. What value of capacitor, C1, is required in the circuit of Fig. 17.26b to obtain a center frequency of 100 kHz?, 22. What is the lock range of the PLL circuit in Fig. 17.26b for R1 4.7 k and C1 0.001 F?, , § 17.7 Interfacing Circuitry, 23. Describe the signal conditions for current-loop and RS-232C interfaces., 24. What is a data bus?, 25. What is the difference between open-collector and tri-state output?, , § 17.8 PSpice Windows, *, , 26. Use Design Center to draw a schematic circuit as in Fig. 17.32, using an LM111 with Vi 5 V, rms applied to minus () input and 5 V rms applied to plus () input. Use Probe to view, the output waveform., , *, , 27. Use Design Center to draw a schematic circuit as in Fig. 17.35. Examine the output listing for, the results., , *, , 28. Use Design Center to draw a 555 oscillator with resulting output with tlow 2 ms, thigh , 5 ms., *Please note: Asterisks indicate more difficult problems., , 750, , Chapter 17, , Linear-Digital ICs
Page 585 :
13, Sinusoidal Alternating, Waveforms, , 13.1, , INTRODUCTION, , The analysis thus far has been limited to dc networks, networks in, which the currents or voltages are fixed in magnitude except for transient effects. We will now turn our attention to the analysis of networks, in which the magnitude of the source varies in a set manner. Of particular interest is the time-varying voltage that is commercially available, in large quantities and is commonly called the ac voltage. (The letters, ac are an abbreviation for alternating current.) To be absolutely rigorous, the terminology ac voltage or ac current is not sufficient to, describe the type of signal we will be analyzing. Each waveform of Fig., 13.1 is an alternating waveform available from commercial supplies., The term alternating indicates only that the waveform alternates, between two prescribed levels in a set time sequence (Fig. 13.1). To be, v, , v, , 0, , t, Sinusoidal, , 0, , v, , t 0, Square wave, , t, Triangular wave, , FIG. 13.1, Alternating waveforms., , absolutely correct, the term sinusoidal, square wave, or triangular must, also be applied. The pattern of particular interest is the sinusoidal ac, waveform for voltage of Fig. 13.1. Since this type of signal is encountered in the vast majority of instances, the abbreviated phrases ac voltage and ac current are commonly applied without confusion. For the, other patterns of Fig. 13.1, the descriptive term is always present, but, frequently the ac abbreviation is dropped, resulting in the designation, square-wave or triangular waveforms.
Page 586 :
510, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , One of the important reasons for concentrating on the sinusoidal ac, voltage is that it is the voltage generated by utilities throughout the, world. Other reasons include its application throughout electrical, electronic, communication, and industrial systems. In addition, the chapters, to follow will reveal that the waveform itself has a number of characteristics that will result in a unique response when it is applied to the, basic electrical elements. The wide range of theorems and methods, introduced for dc networks will also be applied to sinusoidal ac systems. Although the application of sinusoidal signals will raise the, required math level, once the notation given in Chapter 14 is understood, most of the concepts introduced in the dc chapters can be applied, to ac networks with a minimum of added difficulty., The increasing number of computer systems used in the industrial, community requires, at the very least, a brief introduction to the terminology employed with pulse waveforms and the response of some fundamental configurations to the application of such signals. Chapter 22, will serve such a purpose., , 13.2 SINUSOIDAL ac VOLTAGE, CHARACTERISTICS AND DEFINITIONS, Generation, Sinusoidal ac voltages are available from a variety of sources. The, most common source is the typical home outlet, which provides an ac, voltage that originates at a power plant; such a power plant is most, commonly fueled by water power, oil, gas, or nuclear fusion. In each, case an ac generator (also called an alternator), as shown in Fig., 13.2(a), is the primary component in the energy-conversion process., , Inverter, , (a), , (b), , (c), , (d), , (e), , FIG. 13.2, Various sources of ac power: (a) generating plant; (b) portable ac generator;, (c) wind-power station; (d) solar panel; (e) function generator., , The power to the shaft developed by one of the energy sources listed, will turn a rotor (constructed of alternating magnetic poles) inside a, set of windings housed in the stator (the stationary part of the, dynamo) and will induce a voltage across the windings of the stator,, as defined by Faraday’s law,
Page 587 :
SINUSOIDAL ac VOLTAGE CHARACTERISTICS AND DEFINITIONS, , df, eN , dt, Through proper design of the generator, a sinusoidal ac voltage is, developed that can be transformed to higher levels for distribution, through the power lines to the consumer. For isolated locations where, power lines have not been installed, portable ac generators [Fig., 13.2(b)] are available that run on gasoline. As in the larger power, plants, however, an ac generator is an integral part of the design., In an effort to conserve our natural resources, wind power and solar, energy are receiving increasing interest from various districts of the world, that have such energy sources available in level and duration that make the, conversion process viable. The turning propellers of the wind-power station [Fig. 13.2(c)] are connected directly to the shaft of an ac generator to, provide the ac voltage described above. Through light energy absorbed in, the form of photons, solar cells [Fig. 13.2(d)] can generate dc voltages., Through an electronic package called an inverter, the dc voltage can be, converted to one of a sinusoidal nature. Boats, recreational vehicles (RVs),, etc., make frequent use of the inversion process in isolated areas., Sinusoidal ac voltages with characteristics that can be controlled by, the user are available from function generators, such as the one in Fig., 13.2(e). By setting the various switches and controlling the position of, the knobs on the face of the instrument, one can make available sinusoidal voltages of different peak values and different repetition rates., The function generator plays an integral role in the investigation of the, variety of theorems, methods of analysis, and topics to be introduced in, the chapters that follow., , Definitions, The sinusoidal waveform of Fig. 13.3 with its additional notation will now, be used as a model in defining a few basic terms. These terms can, howe, T1, , T2, , Max, , e1, 0, , Em, , t2, , t1, , Ep –p, , e2, , Em, , Max, , t, , T3, , FIG. 13.3, Important parameters for a sinusoidal voltage., , ever, be applied to any alternating waveform. It is important to remember, as you proceed through the various definitions that the vertical scaling is, in volts or amperes and the horizontal scaling is always in units of time., Waveform: The path traced by a quantity, such as the voltage in, Fig. 13.3, plotted as a function of some variable such as time (as, above), position, degrees, radians, temperature, and so on., , , , 511
Page 588 :
512, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , Instantaneous value: The magnitude of a waveform at any instant, of time; denoted by lowercase letters (e1, e2)., Peak amplitude: The maximum value of a waveform as measured, from its average, or mean, value, denoted by uppercase letters (such, as Em for sources of voltage and Vm for the voltage drop across a, load). For the waveform of Fig. 13.3, the average value is zero volts, and Em is as defined by the figure., Peak value: The maximum instantaneous value of a function as, measured from the zero-volt level. For the waveform of Fig. 13.3,, the peak amplitude and peak value are the same, since the average, value of the function is zero volts., Peak-to-peak value: Denoted by Ep-p or Vp-p, the full voltage, between positive and negative peaks of the waveform, that is, the, sum of the magnitude of the positive and negative peaks., Periodic waveform: A waveform that continually repeats itself, after the same time interval. The waveform of Fig. 13.3 is a periodic, waveform., Period (T ): The time interval between successive repetitions of a, periodic waveform (the period T1 T2 T3 in Fig. 13.3), as long as, successive similar points of the periodic waveform are used in determining T., Cycle: The portion of a waveform contained in one period of time., The cycles within T1, T2, and T3 of Fig. 13.3 may appear different in, Fig. 13.4, but they are all bounded by one period of time and therefore satisfy the definition of a cycle., , FIG. 13.4, Defining the cycle and period of a sinusoidal waveform., , Frequency ( f ): The number of cycles that occur in 1 s. The frequency of the waveform of Fig. 13.5(a) is 1 cycle per second, and, for Fig. 13.5(b), 21⁄2 cycles per second. If a waveform of similar, shape had a period of 0.5 s [Fig. 13.5(c)], the frequency would be 2, cycles per second., , FIG. 13.5, Demonstrating the effect of a changing frequency on the period of a sinusoidal, waveform.
Page 589 :
SINUSOIDAL ac VOLTAGE CHARACTERISTICS AND DEFINITIONS, , , , 513, , The unit of measure for frequency is the hertz (Hz), where, 1 hertz (Hz) 1 cycle per second (c/s), , (13.1), , The unit hertz is derived from the surname of Heinrich Rudolph Hertz, (Fig. 13.6), who did original research in the area of alternating currents, and voltages and their effect on the basic R, L, and C elements. The frequency standard for North America is 60 Hz, whereas for Europe it is, predominantly 50 Hz., As with all standards, any variation from the norm will cause difficulties. In 1993, Berlin, Germany, received all its power from eastern plants, whose output frequency was varying between 50.03 and, 51 Hz. The result was that clocks were gaining as much as 4 minutes a day. Alarms went off too soon, VCRs clicked off before the, end of the program, etc., requiring that clocks be continually reset. In, 1994, however, when power was linked with the rest of Europe, the, precise standard of 50 Hz was reestablished and everyone was on, time again., Using a log scale (described in detail in Chapter 21), a frequency, spectrum from 1 GHz to 1000 GHz can be scaled off on the same, axis, as shown in Fig. 13.7. A number of terms in the various spectrums are probably familiar to the reader from everyday experiences., Note that the audio range (human ear) extends from only 15 Hz to 20, kHz, but the transmission of radio signals can occur between 3 kHz, and 300 GHz. The uniform process of defining the intervals of the, radio-frequency spectrum from VLF to EHF is quite evident from the, length of the bars in the figure (although keep in mind that it is a log, scale, so the frequencies encompassed within each segment are quite, different). Other frequencies of particular interest (TV, CB, microwave, etc.) are also included for reference purposes. Although it is, numerically easy to talk about frequencies in the megahertz and gigahertz range, keep in mind that a frequency of 100 MHz, for instance,, represents a sinusoidal waveform that passes through 100,000,000, cycles in only 1 s—an incredible number when we compare it to the, 60 Hz of our conventional power sources The new Pentium II chip, manufactured by Intel can run at speeds up to 450 MHz. Imagine a, product able to handle 450,000,000 instructions per second—an, incredible achievement., Since the frequency is inversely related to the period—that is, as one, increases, the other decreases by an equal amount—the two can be, related by the following equation:, 1, f , T, , or, , f Hz, T seconds (s), 1, T , f, , (13.2), , (13.3), , German (Hamburg,, Berlin, Karlsruhe), (1857–94), Physicist, Professor of Physics,, Karlsruhe, Polytechnic and, University of Bonn, , Courtesy of the, Smithsonian Institution, Photo No. 66,606, , Spurred on by the earlier predictions of the English, physicist James Clerk Maxwell, Heinrich Hertz produced electromagnetic waves in his laboratory at the, Karlsruhe Polytechnic while in his early 30s. The, rudimentary transmitter and receiver were in essence the first to broadcast and receive radio waves., He was able to measure the wavelength of the, electromagnetic waves and confirmed that the velocity of propagation is in the same order of magnitude as light. In addition, he demonstrated that the, reflective and refractive properties of electromagnetic waves are the same as those for heat and light, waves. It was indeed unfortunate that such an ingenious, industrious individual should pass away at the, very early age of 37 due to a bone disease., , FIG. 13.6, Heinrich Rudolph Hertz.
Page 590 :
514, , , , SINUSOIDAL ALTERNATING WAVEFORMS, Microwave, Microwave, oven, EHF, SHF, , 30 GHz – 300 GHz, (Extremely High Freq.), 3 GHz – 30 GHz (Super-High Freq.), , UHF, VHF, HF, MF, LF, VLF, , 300 MHz – 3 GHz (Ultrahigh Freq.), , 30 MHz – 300 MHz (Very High Freq.), , 3 MHz – 30 MHz (High Freq.), , 300 kHz – 3 MHz (Medium Freq.), , 30 kHz – 300 kHz (Low Freq.), , 3 kHz – 30 kHz (Very Low Freq.), Radio frequencies (spectrum), Infrared, , 3 kHz – 300 GHz, Audio frequencies, 15 Hz – 20 kHz, 1 Hz, , 10 Hz, , 100 Hz, , 1 kHz, , 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz 1 GHz 10 GHz 100 GHz 1000 GHz f (log scale), FM, 88 MHz – 108 MHz, TV channels (2 – 6), 54 MHz – 88 MHz, TV channels (7 – 13), 174 MHz – 216 MHz, TV channels (14 – 83), 470 MHz – 890 MHz, CB, , Countertop microwave oven, , 26.9 MHz – 27.4 MHz, , 2.45 GHz, , Shortwave, 1.5 MHz – 30 MHz, Cordless telephones, 46 MHz – 49 MHz, Pagers VHF, 30 MHz – 50 MHz, Pagers UHF, 405 MHz – 512 MHz, , FIG. 13.7, Areas of application for specific frequency bands.
Page 591 :
SINUSOIDAL ac VOLTAGE CHARACTERISTICS AND DEFINITIONS, , , , 515, , EXAMPLE 13.1 Find the period of a periodic waveform with a frequency of, a. 60 Hz., b. 1000 Hz., Solutions:, 1, 1, a. T 0.01667 s or 16.67 ms, f, 60 Hz, (a recurring value since 60 Hz is so prevalent), , e, 10 V, , 1, 1, b. T 103 s 1 ms, f, 1000 Hz, 0, , 5, , 15, , 35, , 25, , t (ms), , EXAMPLE 13.2 Determine the frequency of the waveform of Fig., 13.8., Solution:, , From the figure, T (25 ms 5 ms) 20 ms, and, , FIG. 13.8, Example 13.2., , 1, 1, f , 50 Hz, T, 20 103 s, EXAMPLE 13.3 The oscilloscope is an instrument that will display, alternating waveforms such as those described above. A sinusoidal pattern, appears on the oscilloscope of Fig. 13.9 with the indicated vertical and, horizontal sensitivities. The vertical sensitivity defines the voltage associated with each vertical division of the display. Virtually all oscilloscope, screens are cut into a crosshatch pattern of lines separated by 1 cm in the, vertical and horizontal directions. The horizontal sensitivity defines the, time period associated with each horizontal division of the display., For the pattern of Fig. 13.9 and the indicated sensitivities, determine, the period, frequency, and peak value of the waveform., Solution:, , Vertical sensitivity = 0.1 V/div., Horizontal sensitivity = 50 , s/div., , FIG. 13.9, Example 13.3., , One cycle spans 4 divisions. The period is therefore, 50 ms, T 4 div. 200 ms, div., , , , , , and the frequency is, 1, 1, f , 5 kHz, 200 106 s, T, The vertical height above the horizontal axis encompasses 2 divisions., Therefore,, , , , , , 0.1 V, Vm 2 div. 0.2 V, div., e, , Defined Polarities and Direction, In the following analysis, we will find it necessary to establish a set of, polarities for the sinusoidal ac voltage and a direction for the sinusoidal, ac current. In each case, the polarity and current direction will be for an, instant of time in the positive portion of the sinusoidal waveform. This, is shown in Fig. 13.10 with the symbols for the sinusoidal ac voltage, and current. A lowercase letter is employed for each to indicate that the, quantity is time dependent; that is, its magnitude will change with time., , i, , +, , t, , t, e, , i, , –, (a), , (b), , FIG. 13.10, (a) Sinusoidal ac voltage sources;, (b) sinusoidal current sources.
Page 592 :
516, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , The need for defining polarities and current direction will become quite, obvious when we consider multisource ac networks. Note in the last, sentence the absence of the term sinusoidal before the phrase ac networks. This phrase will be used to an increasing degree as we progress;, sinusoidal is to be understood unless otherwise indicated., , i, , t, , +, R, L, or C, , 13.3, , v, , t, , –, FIG. 13.11, The sine wave is the only alternating, waveform whose shape is not altered by the, response characteristics of a pure resistor,, inductor, or capacitor., , THE SINE WAVE, , The terms defined in the previous section can be applied to any type of, periodic waveform, whether smooth or discontinuous. The sinusoidal, waveform is of particular importance, however, since it lends itself, readily to the mathematics and the physical phenomena associated with, electric circuits. Consider the power of the following statement:, The sine wave is the only alternating waveform whose shape is, unaffected by the response characteristics of R, L, and C elements., In other words, if the voltage across (or current through) a resistor,, coil, or capacitor is sinusoidal in nature, the resulting current (or voltage, respectively) for each will also have sinusoidal characteristics, as, shown in Fig. 13.11. If a square wave or a triangular wave were, applied, such would not be the case. It must be pointed out that the, above statement is also applicable to the cosine wave, since the waves, differ only by a 90° shift on the horizontal axis, as shown in Fig. 13.12., The unit of measurement for the horizontal axis of Fig. 13.12 is the, degree. A second unit of measurement frequently used is the radian, (rad). It is defined by a quadrant of a circle such as in Fig. 13.13 where, the distance subtended on the circumference equals the radius of the, circle., If we define x as the number of intervals of r (the radius) around the, circumference of the circle, then, C 2pr x ⋅ r, and we find, x 2p, Therefore, there are 2p rad around a 360° circle, as shown in Fig., 13.14, and, , FIG. 13.12, Sine wave and cosine wave with the, horizontal axis in degrees., , 2p rad 360°, , r, 1 radian, 57.296°, r, , FIG. 13.13, Defining the radian., , FIG. 13.14, There are 2p radians in one full circle of 360°., , (13.4)
Page 593 :
THE SINE WAVE, , 1 rad 57.296° 57.3°, , with, , , , 517, , (13.5), , A number of electrical formulas contain a multiplier of p. For this, reason, it is sometimes preferable to measure angles in radians rather, than in degrees., The quantity p is the ratio of the circumference of a circle to its, diameter., p has been determined to an extended number of places primarily in, an attempt to see if a repetitive sequence of numbers appears. It does, not. A sampling of the effort appears below:, p 3.14159 26535 89793 23846 26433 . . ., Although the approximation p 3.14 is often applied, all the calculations in this text will use the p function as provided on all scientific calculators., For 180° and 360°, the two units of measurement are related as, shown in Fig. 13.14. The conversion equations between the two are the, following:, , , , , , (13.6), , , , , , (13.7), , p, Radians (degrees), 180°, , 180°, Degrees (radians), p, Applying these equations, we find, p, p, 90°: Radians (90°) rad, 2, 180°, p, p, 30°: Radians (30°) rad, 6, 180°, p, rad:, 3, 3p, rad:, 2, , 180°, Degrees , p, 180°, Degrees , p, , 3 60°, 3p, 2 270°, p, , Using the radian as the unit of measurement for the abscissa, we would, obtain a sine wave, as shown in Fig. 13.15., It is of particular interest that the sinusoidal waveform can be, derived from the length of the vertical projection of a radius vector, rotating in a uniform circular motion about a fixed point. Starting as, shown in Fig. 13.16(a) and plotting the amplitude (above and below, zero) on the coordinates drawn to the right [Figs. 13.16(b) through (i)],, we will trace a complete sinusoidal waveform after the radius vector, has completed a 360° rotation about the center., The velocity with which the radius vector rotates about the center,, called the angular velocity, can be determined from the following, equation:, distance (degrees or radians), Angular velocity , time (seconds), , (13.8), , v, i, etc., Sine wave, , 0, , , 4, , , 2, , 3, 4, , 5 3 7, 4, 2 4 2, (rad), , FIG. 13.15, Plotting a sine wave versus radians.
Page 594 :
518, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , (a), , , , = 0° 0°, Note equality., , (b), , = 45°, 0° 45°, , (c), , (d), , = 90°, 0°, , , , 90°, , = 135°, , , 0° 45° 90° 135°, , (e), , = 180°, 0°, , , , 180°, , = 225°, 225°, , (f), , , , 0°, , = 270°, 270°, , (g), , , , 0°, , = 315°, (h), , 315°, , , 0°, , Sine wave, = 360°, (i), , 225° 270° 315° 360°, 0° 45° 90° 135° 180°, , , , T (period), , FIG. 13.16, Generating a sinusoidal waveform through the vertical projection of a, rotating vector.
Page 595 :
THE SINE WAVE, , , , Substituting into Eq. (13.8) and assigning the Greek letter omega (q), to the angular velocity, we have, , and, , a, q , t, , (13.9), , a qt, , (13.10), , Since q is typically provided in radians per second, the angle a, obtained using Eq. (13.10) is usually in radians. If a is required in, degrees, Equation (13.7) must be applied. The importance of remembering the above will become obvious in the examples to follow., In Fig. 13.16, the time required to complete one revolution is equal, to the period (T) of the sinusoidal waveform of Fig. 13.16(i). The radians subtended in this time interval are 2p. Substituting, we have, 2p, q , T, , (rad/s), , (13.11), , In words, this equation states that the smaller the period of the, sinusoidal waveform of Fig. 13.16(i), or the smaller the time interval, before one complete cycle is generated, the greater must be the angular velocity of the rotating radius vector. Certainly this statement, agrees with what we have learned thus far. We can now go one step, further and apply the fact that the frequency of the generated waveform is inversely related to the period of the waveform; that is, f , 1/T. Thus,, q 2pf, , (rad/s), , (13.12), , This equation states that the higher the frequency of the generated, sinusoidal waveform, the higher must be the angular velocity. Equations, (13.11) and (13.12) are verified somewhat by Fig. 13.17, where for the, same radius vector, q 100 rad/s and 500 rad/s., EXAMPLE 13.4 Determine the angular velocity of a sine wave having a frequency of 60 Hz., Solution:, q 2pf (2p)(60 Hz) 377 rad/s, (a recurring value due to 60-Hz predominance), EXAMPLE 13.5 Determine the frequency and period of the sine wave, of Fig. 13.17(b)., Solution:, , Since q 2p/T,, 2p, 2p rad, 2p rad, T 12.57 ms, 500 rad/s, 500 rad/s, q, , and, , 1, 1, f , 79.58 Hz, T, 12.57 103 s, , FIG. 13.17, Demonstrating the effect of q on the, frequency and period., , 519
Page 596 :
520, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , EXAMPLE 13.6 Given q 200 rad/s, determine how long it will take, the sinusoidal waveform to pass through an angle of 90°., Solution:, , Eq. (13.10): a qt, and, a, t, q, , However, a must be substituted as p/2 ( 90°) since q is in radians per, second:, p, a, p/2 rad, t 7.85 ms, 200 rad/s, 400 s, q, EXAMPLE 13.7 Find the angle through which a sinusoidal waveform, of 60 Hz will pass in a period of 5 ms., Solution:, , Eq. (13.11): a qt, or, a 2pft (2p)(60 Hz)(5 103 s) 1.885 rad, , If not careful, one might be tempted to interpret the answer as, 1.885°. However,, 180°, a (°) (1.885 rad) 108°, p rad, , 13.4 GENERAL FORMAT FOR THE SINUSOIDAL, VOLTAGE OR CURRENT, The basic mathematical format for the sinusoidal waveform is, Am sin a, , (13.13), , where Am is the peak value of the waveform and a is the unit of measure for the horizontal axis, as shown in Fig. 13.18., , FIG. 13.18, Basic sinusoidal function., , The equation a qt states that the angle a through which the rotating vector of Fig. 13.16 will pass is determined by the angular velocity, of the rotating vector and the length of time the vector rotates. For, example, for a particular angular velocity (fixed q), the longer the, radius vector is permitted to rotate (that is, the greater the value of t),, the greater will be the number of degrees or radians through which the, vector will pass. Relating this statement to the sinusoidal waveform, for, a particular angular velocity, the longer the time, the greater the num-
Page 597 :
GENERAL FORMAT FOR THE SINUSOIDAL VOLTAGE OR CURRENT, , ber of cycles shown. For a fixed time interval, the greater the angular, velocity, the greater the number of cycles generated., Due to Eq. (13.10), the general format of a sine wave can also be, written, Am sin qt, , (13.14), , with qt as the horizontal unit of measure., For electrical quantities such as current and voltage, the general format is, i Im sin qt Im sin a, e Em sin qt Em sin a, where the capital letters with the subscript m represent the amplitude,, and the lowercase letters i and e represent the instantaneous value of, current or voltage, respectively, at any time t. This format is particularly, important since it presents the sinusoidal voltage or current as a function of time, which is the horizontal scale for the oscilloscope. Recall, that the horizontal sensitivity of a scope is in time per division and not, degrees per centimeter., EXAMPLE 13.8 Given e 5 sin a, determine e at a 40° and a , 0.8p ., Solution:, , For a 40°,, e 5 sin 40° 5(0.6428) 3.214 V, , For a 0.8p,, 180°, a (°) (0.8p) 144°, p, and, , e 5 sin 144° 5(0.5878) 2.939 V, , The conversion to degrees will not be required for most modern-day, scientific calculators since they can perform the function directly. First, be, sure that the calculator is in the RAD mode. Then simply enter the radian, measure and use the appropriate trigonometric key (sin, cos, tan, etc.)., The angle at which a particular voltage level is attained can be, determined by rearranging the equation, e Em sin a, in the following manner:, e, sin a , Em, which can be written, e, a sin1 , Em, , (13.15), , Similarly, for a particular current level,, i, a sin1 , Im, The function sin1 is available on all scientific calculators., , (13.16), , , , 521
Page 598 :
522, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , EXAMPLE 13.9, a. Determine the angle at which the magnitude of the sinusoidal function v 10 sin 377t is 4 V., b. Determine the time at which the magnitude is attained., Solutions:, a. Eq. (13.15):, v, 4V, a1 sin1 sin1 sin1 0.4 23.578°, Em, 10 V, However, Figure 13.19 reveals that the magnitude of 4 V (positive) will be attained at two points between 0° and 180°. The second, intersection is determined by, , v (V), , a2 180° 23.578° 156.422°, 10, , 4, , 0, , 1, t1, , 90°, , 2 180°, t2, , , , In general, therefore, keep in mind that Equations (13.15) and, (13.16) will provide an angle with a magnitude between 0° and 90°., b. Eq. (13.10): a qt, and so t a/q. However, a must be in radians., Thus,, p, a (rad) (23.578°) 0.411 rad, 180°, , FIG. 13.19, Example 13.9., , and, , 0.411 rad, a, t1 1.09 ms, 377 rad/s, q, , For the second intersection,, p, a (rad) (156.422°) 2.73 rad, 180°, 2.73 rad, a, t2 7.24 ms, 377 rad/s, q, , FIG. 13.20, Example 13.10, horizontal axis in degrees., , The sine wave can also be plotted against time on the horizontal, axis. The time period for each interval can be determined from t a/q,, but the most direct route is simply to find the period T from T 1/f and, break it up into the required intervals. This latter technique will be, demonstrated in Example 13.10., Before reviewing the example, take special note of the relative simplicity of the mathematical equation that can represent a sinusoidal, waveform. Any alternating waveform whose characteristics differ from, those of the sine wave cannot be represented by a single term, but may, require two, four, six, or perhaps an infinite number of terms to be represented accurately. Additional description of nonsinusoidal waveforms, can be found in Chapter 24., EXAMPLE 13.10 Sketch e 10 sin 314t with the abscissa, a. angle (a) in degrees., b. angle (a) in radians., c. time (t) in seconds., , FIG. 13.21, Example 13.10, horizontal axis in radians., , Solutions:, a. See Fig 13.20. (Note that no calculations are required.), b. See Fig. 13.21. (Once the relationship between degrees and radians, is understood, there is again no need for calculations.)
Page 599 :
PHASE RELATIONS, , , , 523, , 2p, 2p, c. 360°: T 20 ms, 314, q, T, 20 ms, 180°: 10 ms, 2, 2, T, 20 ms, 90°: 5 ms, 4, 4, T, 20 ms, 30°: 1.67 ms, 12, 12, FIG. 13.22, Example 13.10, horizontal axis in, milliseconds., , See Fig. 13.22., EXAMPLE 13.11 Given i 6 103 sin 1000t, determine i at t , 2 ms., Solution:, a qt 1000t (1000 rad/s)(2 103 s) 2 rad, 180°, a (°) (2 rad) 114.59°, p rad, i (6 103)(sin 114.59°), (6 mA)(0.9093) 5.46 mA, , Am, ( – ), , Am sin , , , , , , 13.5, , (2 – ), , PHASE RELATIONS, , Thus far, we have considered only sine waves that have maxima at p/2, and 3p/2, with a zero value at 0, p, and 2p, as shown in Fig. 13.21. If the, waveform is shifted to the right or left of 0°, the expression becomes, Am sin(qt v), , (13.17), , where v is the angle in degrees or radians that the waveform has been, shifted., If the waveform passes through the horizontal axis with a positivegoing (increasing with time) slope before 0°, as shown in Fig. 13.23,, the expression is, Am sin(qt v), , (13.18), , At qt a 0°, the magnitude is determined by Am sin v. If the waveform passes through the horizontal axis with a positive-going slope, after 0°, as shown in Fig. 13.24, the expression is, Am sin(qt v), , Am, (p + v), , v, , (2p + v), , , – Am sin v, , FIG. 13.24, Defining the phase shift for a sinusoidal, function that crosses the horizontal axis with, a positive slope after 0°., , (13.19), , And at qt a 0°, the magnitude is Am sin(v), which, by a trigonometric identity, is Am sin v., If the waveform crosses the horizontal axis with a positive-going slope, 90° (p/2) sooner, as shown in Fig. 13.25, it is called a cosine wave; that is,, , , , FIG. 13.23, Defining the phase shift for a sinusoidal, function that crosses the horizontal axis with, a positive slope before 0°., , , , p, sin(qt 90°) sin qt cos qt, 2, , (13.20), , cos , , Am, , p, 2, , –p, 2, 90°, , 0, , sin , p, , 3p, 2, , 2p, , , FIG. 13.25, Phase relationship between a sine wave and a, cosine wave.
Page 600 :
524, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , , , p, sin qt cos(qt 90°) cos qt , 2, , or, , + cos α, – sin α, , + sin α, – cos α, , , , (13.21), , The terms lead and lag are used to indicate the relationship, between two sinusoidal waveforms of the same frequency plotted on, the same set of axes. In Fig. 13.25, the cosine curve is said to lead, the sine curve by 90°, and the sine curve is said to lag the cosine, curve by 90°. The 90° is referred to as the phase angle between the, two waveforms. In language commonly applied, the waveforms are, out of phase by 90°. Note that the phase angle between the two, waveforms is measured between those two points on the horizontal, axis through which each passes with the same slope. If both waveforms cross the axis at the same point with the same slope, they are, in phase., The geometric relationship between various forms of the sine and, cosine functions can be derived from Fig. 13.26. For instance, starting, at the sin a position, we find that cos a is an additional 90° in the counterclockwise direction. Therefore, cos a sin(a 90°). For sin a, we must travel 180° in the counterclockwise (or clockwise) direction so, that sin a sin(a 180°), and so on, as listed below:, , FIG. 13.26, Graphic tool for finding the relationship, between specific sine and cosine functions., , cos a sin(a 90°), sin a cos(a 90°), sin a sin(a 180°), cos a sin(a 270°) sin(a 90°), etc., , (13.22), , In addition, one should be aware that, sin(a) sin a, cos(a) cos a, , (13.23), , If a sinusoidal expression should appear as, e Em sin qt, the negative sign is associated with the sine portion of the expression,, not the peak value Em. In other words, the expression, if not for convenience, would be written, e Em(sin qt), Since, sin qt sin(qt 180°), the expression can also be written, e Em sin(qt 180°), revealing that a negative sign can be replaced by a 180° change in, phase angle ( or ); that is,, e Em sin qt Em sin(qt 180°), Em sin(qt 180°), A plot of each will clearly show their equivalence. There are, therefore, two correct mathematical representations for the functions.
Page 601 :
PHASE RELATIONS, , The phase relationship between two waveforms indicates which, one leads or lags, and by how many degrees or radians., , EXAMPLE 13.12 What is the phase relationship between the sinusoidal waveforms of each of the following sets?, a. v 10 sin(qt 30°), i 5 sin(qt 70°), b. i 15 sin(qt 60°), v 10 sin(qt 20°), c. i 2 cos(qt 10°), v 3 sin(qt 10°), d. i sin(qt 30°), v 2 sin(qt 10°), e. i 2 cos(qt 60°), v 3 sin(qt 150°), Solutions:, a. See Fig. 13.27., i leads v by 40°, or v lags i by 40°., , v, 10, 5, 40° 30°, , 0, , 3, 2, , , , 2, , 2, , t, , 70°, i, , FIG. 13.27, Example 13.12; i leads v by 40°., , b. See Fig. 13.28., i leads v by 80°, or v lags i by 80°., , i, v, 10 15, , –, 2, , 0, 60°, , , 2, , , , 3, , 2, , 20°, 80°, , FIG. 13.28, Example 13.12; i leads v by 80°., , 2, , t, , , , 525
Page 602 :
526, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , c. See Fig. 13.29., i 2 cos(qt 10°) 2 sin(qt 10° 90°), 2 sin(qt 100°), i leads v by 110°, or v lags i by 110°., i, , 2, , –, , 3, , v, , 100°, 0, , 2, , , 10° 2, , , , 3, , 2, , 2, , t, , 110°, , FIG. 13.29, Example 13.12; i leads v by 110°., , d. See Fig. 13.30., , Note, , sin(qt 30°) sin(qt 30° 180°), sin(qt 150°), v leads i by 160°, or i lags v by 160°., v, i, 2, , –, , , 2, , , , 0, , 2, 10°, , 5, , 2, , 1, 3, , 2, , 150°, 160°, , 3, , 2, , t, , 200°, 360°, , FIG. 13.30, Example 13.12; v leads i by 160°., , Or using, Note, , sin(qt 30°) sin(qt 30° 180°), sin(qt 210°), i leads v by 200°, or v lags i by 200°., e. See Fig. 13.31., By choice, , i 2 cos(qt 60°) 2 cos(qt 60° 180°), 2 cos(qt 240°), v, , 2, , –, 2, , 0, , , 2, 150°, , 3, , i, , , , 3, , 2, , 2, , 5, , 2, , FIG. 13.31, Example 13.12; v and i are in phase., , 3, , t
Page 603 :
AVERAGE VALUE, , , , 527, , cos a sin(a 90°), , However,, , 2 cos(qt 240°) 2 sin(qt 240° 90°), 2 sin(qt 150°), v and i are in phase., so that, , Phase Measurements, The hookup procedure for using an oscilloscope to measure phase, angles is covered in detail in Section 15.13. However, the equation for, determining the phase angle can be introduced using Fig. 13.32. First,, note that each sinusoidal function has the same frequency, permitting, the use of either waveform to determine the period. For the waveform, chosen in Fig. 13.32, the period encompasses 5 divisions at 0.2 ms/div., The phase shift between the waveforms (irrespective of which is leading or lagging) is 2 divisions. Since the full period represents a cycle of, 360°, the following ratio [from which Equation (13.24) can be derived], can be formed:, , phase shift (no. of div.), v 360°, T (no. of div.), , i, , θ, T, , 360°, v, , T (no. of div.), phase shift (no. of div.), , and, , e, , Vertical sensitivity = 2 V/div., Horizontal sensitivity = 0.2 ms/div., , (13.24), , FIG. 13.32, Finding the phase angle between waveforms, using a dual-trace oscilloscope., , Substituting into Eq. (13.24) will result in, (2 div.), v 360° 144°, (5 div.), and e leads i by 144°., , 13.6, , AVERAGE VALUE, , Even though the concept of the average value is an important one in, most technical fields, its true meaning is often misunderstood. In Fig., 13.33(a), for example, the average height of the sand may be required, to determine the volume of sand available. The average height of the, sand is that height obtained if the distance from one end to the other, is maintained while the sand is leveled off, as shown in Fig. 13.33(b)., The area under the mound of Fig. 13.33(a) will then equal the area, under the rectangular shape of Fig. 13.33(b) as determined by A , b h. Of course, the depth (into the page) of the sand must be the, same for Fig. 13.33(a) and (b) for the preceding conclusions to have, any meaning., In Fig. 13.33 the distance was measured from one end to the other., In Fig. 13.34(a) the distance extends beyond the end of the original pile, of Fig. 13.33. The situation could be one where a landscaper would like, to know the average height of the sand if spread out over a distance, such as defined in Fig. 13.34(a). The result of an increased distance is, as shown in Fig. 13.34(b). The average height has decreased compared, to Fig. 13.33. Quite obviously, therefore, the longer the distance, the, lower is the average value., , Height, , Sand, Distance, (a), Height, , Average height, Sand, Same, distance, (b), , FIG. 13.33, Defining average value.
Page 604 :
528, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , If the distance parameter includes a depression, as shown in Fig., 13.35(a), some of the sand will be used to fill the depression, resulting, in an even lower average value for the landscaper, as shown in Fig., 13.35(b). For a sinusoidal waveform, the depression would have the, same shape as the mound of sand (over one full cycle), resulting in an, average value at ground level (or zero volts for a sinusoidal voltage over, one full period)., After traveling a considerable distance by car, some drivers like to, calculate their average speed for the entire trip. This is usually done by, dividing the miles traveled by the hours required to drive that distance., For example, if a person traveled 225 mi in 5 h, the average speed was, 225 mi/5 h, or 45 mi/h. This same distance may have been traveled at, various speeds for various intervals of time, as shown in Fig. 13.36., By finding the total area under the curve for the 5 h and then dividing the area by 5 h (the total time for the trip), we obtain the same result, of 45 mi/h; that is,, , Height, , Sand, Distance, (a), , Height, , Average height, Sand, Same, distance, (b), , area under curve, Average speed , length of curve, , FIG. 13.34, Effect of distance (length) on average value., , (13.25), , A1 A2, Average speed , 5h, (60 mi/h)(2 h) (50 mi/h)(2.5 h), , 5h, 225, mi/h, 5, , Height, , Sand, Ground level, Distance, , 45 mi/h, , (a), , Equation (13.25) can be extended to include any variable quantity, such, as current or voltage, if we let G denote the average value, as follows:, , Height, , algebraic sum of areas, G (average value) , length of curve, , Average height, Sand, Same, distance, (b), , FIG. 13.35, Effect of depressions (negative excursions) on, average value., , (13.26), , Speed (mi/h), 70, 60, 50, 40, 30, 20, 10, 0, , Average speed, A1, , 1, , A2, 2, 3, Lunch break, , 4, , 5, , 6, , t (h), , FIG. 13.36, Plotting speed versus time for an automobile excursion., , The algebraic sum of the areas must be determined, since some area, contributions will be from below the horizontal axis. Areas above the, axis will be assigned a positive sign, and those below, a negative sign., A positive average value will then be above the axis, and a negative, value, below., The average value of any current or voltage is the value indicated on, a dc meter. In other words, over a complete cycle, the average value is
Page 605 :
AVERAGE VALUE, , , , 529, , the equivalent dc value. In the analysis of electronic circuits to be considered in a later course, both dc and ac sources of voltage will be, applied to the same network. It will then be necessary to know or determine the dc (or average value) and ac components of the voltage or current in various parts of the system., , EXAMPLE 13.13 Determine the average value of the waveforms of, Fig. 13.37., v2, , v1, , (Square wave), , 14 V, , 10 V, , 0, , 1, , 2, , 3, , 4, , t (ms), , 0, , 1, , 2, , 3, , 4, , t (ms), , –6 V, , –10 V, , (b), , (a), FIG. 13.37, Example 13.13., , Solutions:, a. By inspection, the area above the axis equals the area below over, one cycle, resulting in an average value of zero volts. Using Eq., (13.26):, (10 V)(1 ms) (10 V)(1 ms), G , 2 ms, 0, 0V, 2 ms, b. Using Eq. (13.26):, (14 V)(1 ms) (6 V)(1 ms), G , 2 ms, 8V, 14 V 6 V, 4 V, 2, 2, , 14 V, 4V, 0, , v2 v1 4 V, EXAMPLE 13.14 Find the average values of the following waveforms, over one full cycle:, a. Fig. 13.39., b. Fig. 13.40., , 1, , 2, , 3, , 4, , t (ms), , –6 V, , as shown in Fig. 13.38., In reality, the waveform of Fig. 13.37(b) is simply the square wave, of Fig. 13.37(a) with a dc shift of 4 V; that is,, , FIG. 13.38, Defining the average value for the waveform, of Fig. 13.37(b)., v (V), 1 cycle, 3, 0, , 4, , 8, t (ms), , –1, FIG. 13.39, Example 13.14, part (a).
Page 606 :
530, , , , SINUSOIDAL ALTERNATING WAVEFORMS, i (A), 1 cycle, 4, 6, , 0, 2, , –2, , 8, , 4, , 10, , t (ms), , –10, , FIG. 13.40, Example 13.14, part (b)., vav (V), 0 1V, , 1, , 8 t (ms), dc voltmeter (between 0 and 8 ms), , FIG. 13.41, The response of a dc meter to the waveform of, Fig. 13.39., iav (A), 0, –1.6, , 10, t (ms), , – –1.6 +, , dc ammeter (between 0 and 10 ms), , FIG. 13.42, The response of a dc meter to the waveform of, Fig. 13.40., , Solutions:, (3 V)(4 ms) (1 V)(4 ms), 12 V 4 V, a. G 1 V, 8 ms, 8, Note Fig. 13.41., (10 V)(2 ms) (4 V)(2 ms) (2 V)(2 ms), b. G , 10 ms, 16 V, 20 V 8 V 4 V, 1.6 V, 10, 10, Note Fig. 13.42., We found the areas under the curves in the preceding example by, using a simple geometric formula. If we should encounter a sine wave, or any other unusual shape, however, we must find the area by some, other means. We can obtain a good approximation of the area by, attempting to reproduce the original wave shape using a number of, small rectangles or other familiar shapes, the area of which we already, know through simple geometric formulas. For example,, the area of the positive (or negative) pulse of a sine wave is 2Am., Approximating this waveform by two triangles (Fig. 13.43), we obtain, (using area 1/2 base height for the area of a triangle) a rough idea, of the actual area:, b, , h, , , , , , , , , FIG. 13.43, Approximating the shape of the positive pulse, of a sinusoidal waveform with two right, triangles., , , , 1, 1 p, p, Area shaded 2 bh 2 (Am) Am, 2, 2 2, 2, 1.58Am, A closer approximation might be a rectangle with two similar triangles (Fig. 13.44):, , , , , , 2, 1, p, p, p, Area Am 2 bh Am Am pAm, 2, 3, 3, 3, 3, 2.094Am, , FIG. 13.44, A better approximation for the shape of the, positive pulse of a sinusoidal waveform., , which is certainly close to the actual area. If an infinite number of, forms were used, an exact answer of 2Am could be obtained. For irregular waveforms, this method can be especially useful if data such as the, average value are desired., The procedure of calculus that gives the exact solution 2Am is, known as integration. Integration is presented here only to make the
Page 607 :
AVERAGE VALUE, , , , 531, , method recognizable to the reader; it is not necessary to be proficient in, its use to continue with this text. It is a useful mathematical tool, however, and should be learned. Finding the area under the positive pulse of, a sine wave using integration, we have, Area , , , , p, , Am sin a da, , 0, , where ∫ is the sign of integration, 0 and p are the limits of integration,, Am sin a is the function to be integrated, and da indicates that we are, integrating with respect to a., Integrating, we obtain, Area Am[cos a]p0, Am(cos p cos 0°), Am[1 (1)] Am(2), , Am, , Area 2Am, , (13.27), , p, , 0, , Since we know the area under the positive (or negative) pulse, we, can easily determine the average value of the positive (or negative), region of a sine wave pulse by applying Eq. (13.26):, 2Am, G, p, , and, , G, , G 0.637Am, 0, , Am, , (13.28), , p, , For the waveform of Fig. 13.45,, 2Am, (2Am /2), G, p, p/2, , FIG. 13.45, Finding the average value of one-half the, positive pulse of a sinusoidal waveform., , (average the same, as for a full pulse), , 1 cycle, , EXAMPLE 13.15 Determine the average value of the sinusoidal, waveform of Fig. 13.46., , Am, , π, , 0, , Solution:, , By inspection it is fairly obvious that, , the average value of a pure sinusoidal waveform over one full cycle is, zero., , Am, , 2π, , α, , FIG. 13.46, Example 13.15., , Eq. (13.26):, 2Am 2Am, G 0 V, 2p, , v, , +2 mV, , EXAMPLE 13.16 Determine the average value of the waveform of, Fig. 13.47., Solution: The peak-to-peak value of the sinusoidal function is, 16 mV 2 mV 18 mV. The peak amplitude of the sinusoidal waveform is, therefore, 18 mV/2 9 mV. Counting down 9 mV from 2 mV, (or 9 mV up from 16 mV) results in an average or dc level of 7 mV,, as noted by the dashed line of Fig. 13.47., , t, , 0, , – 16 mV, , FIG. 13.47, Example 13.16.
Page 608 :
, , 532, , SINUSOIDAL ALTERNATING WAVEFORMS, , v (V), , EXAMPLE 13.17 Determine the average value of the waveform of, Fig. 13.48., , 1 cycle, 10, Sine wave, p, , 0, , Solution:, 2p, , 1, , FIG. 13.48, Example 13.17., , 2(10 V), 2Am 0, G 3.18 V, 2p, 2p, , EXAMPLE 13.18 For the waveform of Fig. 13.49, determine whether, the average value is positive or negative, and determine its approximate, value., Solution: From the appearance of the waveform, the average value, is positive and in the vicinity of 2 mV. Occasionally, judgments of this, type will have to be made., , v (mV), 10 mV, , t, , 0, , Instrumentation, The dc level or average value of any waveform can be found using a, digital multimeter (DMM) or an oscilloscope. For purely dc circuits,, simply set the DMM on dc, and read the voltage or current levels., Oscilloscopes are limited to voltage levels using the sequence of steps, listed below:, , FIG. 13.49, Example 13.18., , 1. First choose GND from the DC-GND-AC option list associated, with each vertical channel. The GND option blocks any signal to, which the oscilloscope probe may be connected from entering the, oscilloscope and responds with just a horizontal line. Set the, resulting line in the middle of the vertical axis on the horizontal, axis, as shown in Fig. 13.50(a)., , Shift = 2.5 div., , (a), , Vertical sensitivity = 50 mV/div., (b), , FIG. 13.50, Using the oscilloscope to measure dc voltages: (a) setting the GND condition;, (b) the vertical shift resulting from a dc voltage when shifted to the DC option., , 2. Apply the oscilloscope probe to the voltage to be measured (if, not already connected), and switch to the DC option. If a dc voltage is present, the horizontal line will shift up or down, as, demonstrated in Fig. 13.50(b). Multiplying the shift by the vertical sensitivity will result in the dc voltage. An upward shift is a, positive voltage (higher potential at the red or positive lead of the, oscilloscope), while a downward shift is a negative voltage, (lower potential at the red or positive lead of the oscilloscope).
Page 609 :
AVERAGE VALUE, , In general,, Vdc (vertical shift in div.) (vertical sensitivity in V/div.), , (13.29), , For the waveform of Fig. 13.50(b),, Vdc (2.5 div.)(50 mV/div.) 125 mV, The oscilloscope can also be used to measure the dc or average level, of any waveform using the following sequence:, 1. Using the GND option, reset the horizontal line to the middle of, the screen., 2. Switch to AC (all dc components of the signal to which the probe, is connected will be blocked from entering the oscilloscope—, only the alternating, or changing, components will be displayed)., Note the location of some definitive point on the waveform, such, as the bottom of the half-wave rectified waveform of Fig., 13.51(a); that is, note its position on the vertical scale. For the, future, whenever you use the AC option, keep in mind that the, computer will distribute the waveform above and below the horizontal axis such that the average value is zero; that is, the area, above the axis will equal the area below., 3. Then switch to DC (to permit both the dc and the ac components, of the waveform to enter the oscilloscope), and note the shift in, the chosen level of part 2, as shown in Fig. 13.51(b). Equation, (13.29) can then be used to determine the dc or average value of, the waveform. For the waveform of Fig. 13.51(b), the average, value is about, Vav Vdc (0.9 div.)(5 V/div.) 4.5 V, , Reference, level, , (a), , Shift = 0.9 div., , (b), , FIG. 13.51, Determining the average value of a nonsinusoidal waveform using the, oscilloscope: (a) vertical channel on the ac mode; (b) vertical channel on the, dc mode., , The procedure outlined above can be applied to any alternating, waveform such as the one in Fig. 13.49. In some cases the average, value may require moving the starting position of the waveform under, the AC option to a different region of the screen or choosing a higher, voltage scale. DMMs can read the average or dc level of any waveform, by simply choosing the appropriate scale., , , , 533
Page 610 :
534, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , 13.7 EFFECTIVE VALUES, This section will begin to relate dc and ac quantities with respect to, the power delivered to a load. It will help us determine the amplitude, of a sinusoidal ac current required to deliver the same power as a, particular dc current. The question frequently arises, How is it possible for a sinusoidal ac quantity to deliver a net power if, over a full, cycle, the net current in any one direction is zero (average value , 0)? It would almost appear that the power delivered during the positive portion of the sinusoidal waveform is withdrawn during the negative portion, and since the two are equal in magnitude, the net, power delivered is zero. However, understand that irrespective of, direction, current of any magnitude through a resistor will deliver, power to that resistor. In other words, during the positive or negative, portions of a sinusoidal ac current, power is being delivered at each, instant of time to the resistor. The power delivered at each instant, will, of course, vary with the magnitude of the sinusoidal ac current,, but there will be a net flow during either the positive or the negative, pulses with a net flow over the full cycle. The net power flow will, equal twice that delivered by either the positive or the negative, regions of sinusoidal quantity., A fixed relationship between ac and dc voltages and currents can be, derived from the experimental setup shown in Fig. 13.52. A resistor in, a water bath is connected by switches to a dc and an ac supply. If switch, 1 is closed, a dc current I, determined by the resistance R and battery, voltage E, will be established through the resistor R. The temperature, reached by the water is determined by the dc power dissipated in the, form of heat by the resistor., iac, Switch 1, , Switch 2, , R, e, , ac generator, , E, , Idc, dc source, , FIG. 13.52, An experimental setup to establish a relationship between dc and ac quantities., , If switch 2 is closed and switch 1 left open, the ac current through, the resistor will have a peak value of Im. The temperature reached by, the water is now determined by the ac power dissipated in the form of, heat by the resistor. The ac input is varied until the temperature is the, same as that reached with the dc input. When this is accomplished, the, average electrical power delivered to the resistor R by the ac source is, the same as that delivered by the dc source., The power delivered by the ac supply at any instant of time is, Pac (iac)2R (Im sin qt)2R (I 2m sin2qt)R, but, 1, sin2 qt (1 cos 2qt), 2, , (trigonometric identity)
Page 611 :
EFFECTIVE VALUES, , Therefore,, , , , , , 1, Pac I m2 (1 cos 2qt) R, 2, , and, , I m2 R, I m2 R, Pac cos 2qt, 2, 2, , (13.30), , The average power delivered by the ac source is just the first term,, since the average value of a cosine wave is zero even though the wave, may have twice the frequency of the original input current waveform., Equating the average power delivered by the ac generator to that delivered by the dc source,, Pav(ac) Pdc, I m2 R, , I 2dc R and, 2, or, , Im 2Idc, , Im, Idc 0.707Im, 2, , which, in words, states that, the equivalent dc value of a sinusoidal current or voltage is 1/ 2 or, 0.707 of its maximum value., The equivalent dc value is called the effective value of the sinusoidal, quantity., In summary,, , or, , and, , or, , Ieq(dc) Ieff 0.707Im, , (13.31), , Im 2Ieff 1.414Ieff, , (13.32), , Eeff 0.707Em, , (13.33), , Em 2Eeff 1.414Eeff, , (13.34), , As a simple numerical example, it would require an ac current with, a peak value of 2(10) 14.14 A to deliver the same power to the, resistor in Fig. 13.52 as a dc current of 10 A. The effective value of any, quantity plotted as a function of time can be found by using the following equation derived from the experiment just described:, , i (t) dt, T, , or, , 2, , Ieff , , , T, , (13.35), , Ieff , , area (i2(t)), , T, , (13.36), , 0, , , , 535
Page 612 :
536, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , which, in words, states that to find the effective value, the function i(t), must first be squared. After i(t) is squared, the area under the curve is, found by integration. It is then divided by T, the length of the cycle or, the period of the waveform, to obtain the average or mean value of the, squared waveform. The final step is to take the square root of the mean, value. This procedure gives us another designation for the effective, value, the root-mean-square (rms) value., EXAMPLE 13.19 Find the effective values of the sinusoidal waveform in each part of Fig. 13.53., , i (mA), , v, , i (mA), , 12, , 12, , 0, , 1s, , t, , 169.7 V, 1s, , 0, , (a), , 2s, , t, , t, , (b), , (c), , FIG. 13.53, Example 13.19., , Solution: For part (a), Ieff 0.707(12 103 A) 8.484 mA., For part (b), again Ieff 8.484 mA. Note that frequency did not, change the effective value in (b) above as compared to (a). For part, (c), Veff 0.707(169.73 V) 120 V, the same as available from a, home outlet., EXAMPLE 13.20 The 120-V dc source of Fig. 13.54(a) delivers, 3.6 W to the load. Determine the peak value of the applied voltage, (Em) and the current (Im) if the ac source [Fig. 13.54(b)] is to, deliver the same power to the load., , Im, , Idc, , iac, e, , E, , 120 V, , Em, , P = 3.6 W, Load, , +, P = 3.6 W, Load, , –, , (a), , (b), , FIG. 13.54, Example 13.20.
Page 613 :
EFFECTIVE VALUES, , Solution:, , 537, , v (V), 1 cycle, , Pdc VdcIdc, 3, , Pdc, 3.6 W, Idc , 30 mA, 120 V, Vdc, , and, , , , 0, , Im 2Idc (1.414)(30 mA) 42.42 mA, Em 2Edc (1.414)(120 V) 169.68 V, , 4, , 8, t (s), , –1, , FIG. 13.55, Example 13.21., , EXAMPLE 13.21 Find the effective or rms value of the waveform of, Fig. 13.55., v2 (V), , Solution:, v2 (Fig. 13.56):, (9)(4) (1)(4), , 8, , Veff , , 9, , 40, 2.236 V, 8, , EXAMPLE 13.22 Calculate the effective value of the voltage of Fig., 13.57., (– 1)2 = 1, 1, 0, , v (V), 1 cycle, , 4, , 6, , 8, , 10, , t (s), , –10, , FIG. 13.57, Example 13.22., , Solution:, v2 (Fig. 13.58):, Veff , , (100)(2) (16)(2) (4)(2), , 10, , 240, , 10, , 4.899 V, , v2 (V), 100, , 16, 4, 0, , 2, , 4, , 8, , FIG. 13.56, The squared waveform of Fig. 13.55., , 4, 0, –2, , 4, , 6, , 8, , FIG. 13.58, The squared waveform of Fig. 13.57., , 10, , t (s), , t (s)
Page 614 :
538, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , v (V), , EXAMPLE 13.23 Determine the average and effective values of the, square wave of Fig. 13.59., , 40, , 0, – 40, , 10, , 20, , t (ms), , 1 cycle, , Solution: By inspection, the average value is zero., v2 (Fig. 13.60):, (1600)(10 103) (1600)(10 103), Veff , 20 103, , FIG. 13.59, Example 13.23., , , , 32,000 103, , 1600, 20 103, , Veff 40 V, v2 (V), , (the maximum value of the waveform of Fig. 13.60), , 1600, , 0, , 10, , 20, , t (ms), , FIG. 13.60, The squared waveform of Fig. 13.59., , The waveforms appearing in these examples are the same as those, used in the examples on the average value. It might prove interesting to, compare the effective and average values of these waveforms., The effective values of sinusoidal quantities such as voltage or current will be represented by E and I. These symbols are the same as, those used for dc voltages and currents. To avoid confusion, the peak, value of a waveform will always have a subscript m associated with it:, Im sin qt. Caution: When finding the effective value of the positive, pulse of a sine wave, note that the squared area is not simply (2Am)2 , 4A2m; it must be found by a completely new integration. This will, always be the case for any waveform that is not rectangular., A unique situation arises if a waveform has both a dc and an ac component that may be due to a source such as the one in Fig. 13.61. The, combination appears frequently in the analysis of electronic networks, where both dc and ac levels are present in the same system., vT, , +, , +, , 3 sin ω t, , –, 6V, , vT, , 7.5 V, 6V, 4.5 V, , –, 0, , t, , FIG. 13.61, Generation and display of a waveform having a dc and an ac component., , The question arises, What is the effective value of the voltage vT?, One might be tempted to simply assume that it is the sum of the effective values of each component of the waveform; that is, VT (eff) , 0.7071(1.5 V) 6 V 1.06 V 6 V 7.06 V. However, the rms, value is actually determined by, 2, Veff V 2dc V ac, (rms), , which for the above example is, Veff (6 V)2 (1.06 V)2, 37.124 V, 6.1 V, , (13.37)
Page 615 :
ac METERS AND INSTRUMENTS, , This result is noticeably less than the above solution. The development, of Eq. (13.37) can be found in Chapter 24., , Instrumentation, It is important to note whether the DMM in use is a true rms meter or, simply a meter where the average value is calibrated (as described in, the next section) to indicate the rms level. A true rms meter will read, the effective value of any waveform (such as Figs. 13.49 and 13.61), and is not limited to only sinusoidal waveforms. Since the label true, rms is normally not placed on the face of the meter, it is prudent to, check the manual if waveforms other than purely sinusoidal are to be, encountered., , 13.8, , ac METERS AND INSTRUMENTS, , The d’Arsonval movement employed in dc meters can also be used to, measure sinusoidal voltages and currents if the bridge rectifier of Fig., 13.62 is placed between the signal to be measured and the average reading movement., The bridge rectifier, composed of four diodes (electronic switches),, will convert the input signal of zero average value to one having an, average value sensitive to the peak value of the input signal. The conversion process is well described in most basic electronics texts. Fundamentally, conduction is permitted through the diodes in such a manner as to convert the sinusoidal input of Fig. 13.63(a) to one having the, appearance of Fig. 13.63(b). The negative portion of the input has been, effectively “flipped over” by the bridge configuration. The resulting, waveform of Fig. 13.63(b) is called a full-wave rectified waveform., , vi, , vmovement, , Vm, , 0, , Vm, , , , 2 , , 0, , Vdc = 0.637Vm, , , , 2, , , , –Vm, (a), , (b), , FIG. 13.63, (a) Sinusoidal input; (b) full-wave rectified signal., , The zero average value of Fig. 13.63(a) has been replaced by a pattern having an average value determined by, 2Vm, 4Vm, 2Vm 2Vm, G 0.637Vm, p, 2p, 2p, The movement of the pointer will therefore be directly related to the, peak value of the signal by the factor 0.637., Forming the ratio between the rms and dc levels will result in, 0.707Vm, Vrms, 1.11, 0.637Vm, Vdc, , +, vmovement, vi, , –, , +, , –, FIG. 13.62, Full-wave bridge rectifier., , , , 539
Page 616 :
540, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , revealing that the scale indication is 1.11 times the dc level measured, by the movement; that is,, Meter indication 1.11 (dc or average value), , Some ac meters use a half-wave rectifier arrangement that results in, the waveform of Fig. 13.64, which has half the average value of Fig., 13.63(b) over one full cycle. The result is, , vmovement, Vm, Vdc = 0.318Vm, , , , full-wave (13.38), , 2, , FIG. 13.64, Half-wave rectified signal., , FIG. 13.65, Electrodynamometer movement. (Courtesy of, Weston Instruments, Inc.), , Meter indication 2.22 (dc or average value), , half-wave (13.39), , A second movement, called the electrodynamometer movement, (Fig. 13.65), can measure both ac and dc quantities without a change in, internal circuitry. The movement can, in fact, read the effective value of, any periodic or nonperiodic waveform because a reversal in current, direction reverses the fields of both the stationary and the movable, coils, so the deflection of the pointer is always up-scale., The VOM, introduced in Chapter 2, can be used to measure both dc, and ac voltages using a d’Arsonval movement and the proper switching, networks. That is, when the meter is used for dc measurements, the dial, setting will establish the proper series resistance for the chosen scale, and will permit the appropriate dc level to pass directly to the movement. For ac measurements, the dial setting will introduce a network, that employs a full- or half-wave rectifier to establish a dc level. As discussed above, each setting is properly calibrated to indicate the desired, quantity on the face of the instrument., , EXAMPLE 13.24 Determine the reading of each meter for each situation of Fig. 13.66(a) and (b)., , d’Arsonval, movement, rms scale, (full-wave, rectifier), , dc, , ac, , +, , +, , 20 V, , –, , Vm = 20 V, , –, , Voltmeter, (1), , (2), , (a), Electrodynamometer, movement, rms scale, , dc, , +, , +, 25 V, , e = 15 sin 200t, , –, , –, , Voltmeter, (1), (b), , FIG. 13.66, Example 13.24., , (2)
Page 617 :
ac METERS AND INSTRUMENTS, , Solution:, , , , 541, , For Fig. 13.66(a), situation (1): By Eq. (13.38),, Meter indication 1.11(20 V) 22.2 V, , For Fig. 13.66(a), situation (2):, Vrms 0.707Vm 0.707(20 V) 14.14 V, For Fig. 13.66(b), situation (1):, Vrms Vdc 25 V, For Fig. 13.66(b), situation (2):, Vrms 0.707Vm 0.707(15 V) 10.6 V, Most DMMs employ a full-wave rectification system to convert the, input ac signal to one with an average value. In fact, for the DMM of, Fig. 2.27, the same scale factor of Eq. (13.38) is employed; that is, the, average value is scaled up by a factor of 1.11 to obtain the rms value., In digital meters, however, there are no moving parts such as in the, d’Arsonval or electrodynamometer movements to display the signal, level. Rather, the average value is sensed by a multiprocessor integrated, circuit (IC), which in turn determines which digits should appear on the, digital display., Digital meters can also be used to measure nonsinusoidal signals,, but the scale factor of each input waveform must first be known (normally provided by the manufacturer in the operator’s manual). For, instance, the scale factor for an average responding DMM on the ac rms, scale will produce an indication for a square-wave input that is 1.11, times the peak value. For a triangular input, the response is 0.555 times, the peak value. Obviously, for a sine wave input, the response is 0.707, times the peak value., For any instrument, it is always good practice to read (if only briefly), the operator’s manual if it appears that you will use the instrument on a, regular basis., For frequency measurements, the frequency counter of Fig. 13.67, provides a digital readout of sine, square, and triangular waves from, 5 Hz to 100 MHz at input levels from 30 mV to 42 V. Note the relative, simplicity of the panel and the high degree of accuracy available., The Amp-Clamp® of Fig. 13.68 is an instrument that can measure, alternating current in the ampere range without having to open the circuit. The loop is opened by squeezing the “trigger”; then it is placed, around the current-carrying conductor. Through transformer action, the, level of current in rms units will appear on the appropriate scale. The, accuracy of this instrument is 3% of full scale at 60 Hz, and its scales, have maximum values ranging from 6 A to 300 A. The addition of two, leads, as indicated in the figure, permits its use as both a voltmeter and, an ohmmeter., One of the most versatile and important instruments in the electronics industry is the oscilloscope, which has already been introduced in, this chapter. It provides a display of the waveform on a cathode-ray, tube to permit the detection of irregularities and the determination of, quantities such as magnitude, frequency, period, dc component, and so, on. The analog oscilloscope of Fig. 13.69 can display two waveforms at, the same time (dual-channel) using an innovative interface (front, panel). It employs menu buttons to set the vertical and horizontal scales, by choosing from selections appearing on the screen. One can also store, up to four measurement setups for future use., , FIG. 13.67, Frequency counter. (Courtesy of Tektronix,, Inc.), , FIG. 13.68, Amp-Clamp®. (Courtesy of Simpson, Instruments, Inc.), , FIG. 13.69, Dual-channel oscilloscope. (Courtesy of, Tektronix, Inc.)
Page 618 :
542, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , A student accustomed to watching TV might be confused when, first introduced to an oscilloscope. There is, at least initially, an, assumption that the oscilloscope is generating the waveform on the, screen—much like a TV broadcast. However, it is important to, clearly understand that, an oscilloscope displays only those signals generated elsewhere and, connected to the input terminals of the oscilloscope. The absence of, an external signal will simply result in a horizontal line on the screen, of the scope., On most modern-day oscilloscopes, there is a switch or knob with, the choice DC/GND/AC, as shown in Fig. 13.70(a), that is often, ignored or treated too lightly in the early stages of scope utilization., The effect of each position is fundamentally as shown in Fig. 13.70(b)., In the DC mode the dc and ac components of the input signal can pass, directly to the display. In the AC position the dc input is blocked by the, capacitor, but the ac portion of the signal can pass through to the, screen. In the GND position the input signal is prevented from reaching, the scope display by a direct ground connection, which reduces the, scope display to a single horizontal line., , AC, , Oscilloscope, display, , AC, GND, DC, , GND, DC, (a), , Input signal, , (b), , FIG. 13.70, AC-GND-DC switch for the vertical channel of an oscilloscope., , 13.9, , APPLICATIONS, , (120 V at 60 Hz) versus (220 V at 50 Hz), In North and South America the most common available ac supply is, 120 V at 60 Hz, while in Europe and the Eastern countries it is 220 V, at 50 Hz. The choices of rms value and frequency were obviously made, carefully because they have such an important impact on the design and, operation of so many systems., The fact that the frequency difference is only 10 Hz reveals that, there was agreement on the general frequency range that should be used, for power generation and distribution. History suggests that the question of frequency selection was originally focused on that frequency, that would not exhibit flicker in the incandescent lamps available in, those days. Technically, however, there really wouldn’t be a noticeable, difference between 50 and 60 cycles per second based on this criterion., Another important factor in the early design stages was the effect of frequency on the size of transformers, which play a major role in power, generation and distribution. Working through the fundamental equations for transformer design, you will find that the size of a transformer, is inversely proportional to frequency. The result is that transformers, operating at 50 Hz must be larger (on a purely mathematical basis about, 17% larger) than those operating at 60 Hz. You will therefore find that, transformers designed for the international market where they can oper-
Page 619 :
APPLICATIONS, , ate on 50 Hz or 60 Hz are designed around the 50-Hz frequency. On the, other side of the coin, however, higher frequencies result in increased, concerns about arcing, increased losses in the transformer core due to, eddy current and hysteresis losses (Chapter 19), and skin effect phenomena (Chapter 19). Somewhere in the discussion we must consider, the fact that 60 Hz is an exact multiple of 60 seconds in a minute and, 60 minutes in an hour. Since accurate timing is such a critical part of, our technological design, was this a significant motive in the final, choice? There is also the question about whether the 50 Hz is a result, of the close affinity of this value to the metric system. Keep in mind, that powers of 10 are all powerful in the metric system, with 100 cm in, a meter, 100°C the boiling point of water, and so on. Note that 50 Hz is, exactly half of this special number. All in all, it would seem that both, sides have an argument that would be worth defending. However, in the, final analysis, we must also wonder whether the difference is simply, political in nature., The difference in voltage between North America and Europe is a, different matter entirely in the sense that the difference is close to, 100%. Again, however, there are valid arguments for both sides. There, is no question that larger voltages such as 220 V raise safety issues, beyond those raised by voltages of 120 V. However, when higher voltages are supplied, there is less current in the wire for the same power, demand, permitting the use of smaller conductors—a real money saver., In addition, motors, compressors, and so on, found in common home, appliances and throughout the industrial community can be smaller in, size. Higher voltages, however, also bring back the concern about arcing effects, insulation requirements, and, due to real safety concerns,, higher installation costs. In general, however, international travelers are, prepared for most situations if they have a transformer that can convert, from their home level to that of the country they plan to visit. Most, equipment (not clocks, of course) can run quite well on 50 Hz or 60 Hz, for most travel periods. For any unit not operating at its design frequency, it will simply have to “work a little harder” to perform the, given task. The major problem for the traveler is not the transformer, itself but the wide variety of plugs used from one country to another., Each country has its own design for the “female” plug in the wall. For, the three-week tour, this could mean as many as 6 to 10 different plugs, of the type shown in Fig. 13.71. For a 120-V, 60-Hz supply, the plug is, quite standard in appearance with its two spade leads (and possible, ground connection)., In any event, both the 120 V at 60 Hz and the 220 V at 50 Hz are, obviously meeting the needs of the consumer. It is a debate that could, go on at length without an ultimate victor., , Safety Concerns (High Voltages and dc versus ac), Be aware that any “live” network should be treated with a calculated, level of respect. Electricity in its various forms is not to be feared but, should be employed with some awareness of its potentially dangerous, side effects. It is common knowledge that electricity and water do not, mix (never use extension cords or plug in TVs or radios in the bathroom) because a full 120 V in a layer of water of any height (from a, shallow puddle to a full bath) can be lethal. However, other effects of, dc and ac voltages are less known. In general, as the voltage and current increase, your concern about safety should increase exponentially., , , , FIG. 13.71, Variety of plugs for a 220-V, 50-Hz, connection., , 543
Page 620 :
544, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , V(volts), 170, 120 V rms, ac voltage, 20, 0, –20, , t, tf, , FIG 13.72, Interval of time when sinusoidal voltage is, near zero volts., , For instance, under dry conditions, most human beings can survive a, 120-V ac shock such as obtained when changing a light bulb, turning, on a switch, and so on. Most electricians have experienced such a jolt, many times in their careers. However, ask an electrician to relate how it, feels to hit 220 V, and the response (if he or she has been unfortunate to, have had such an experience) will be totally different. How often have, you heard of a back-hoe operator hitting a 220-V line and having a fatal, heart attack? Remember, the operator is sitting in a metal container on, a damp ground which provides an excellent path for the resulting current to flow from the line to ground. If only for a short period of time,, with the best environment (rubber-sole shoes, etc.), in a situation where, you can quickly escape the situation, most human beings can also survive a 220-V shock. However, as mentioned above, it is one you will, not quickly forget. For voltages beyond 220 V rms, the chances of survival go down exponentially with increase in voltage. It takes only, about 10 mA of steady current through the heart to put it in defibrillation. In general, therefore, always be sure that the power is disconnected when working on the repair of electrical equipment. Don’t, assume that throwing a wall switch will disconnect the power. Throw, the main circuit breaker and test the lines with a voltmeter before working on the system. Since voltage is a two-point phenomenon, don’t be a, hero and work with one line at at time—accidents happen!, You should also be aware that the reaction to dc voltages is quite different from that to ac voltages. You have probably seen in movies or, comic strips that people are often unable to let go of a hot wire. This is, evidence of the most important difference between the two types of, voltages. As mentioned above, if you happen to touch a “hot” 120-V ac, line, you will probably get a good sting, but you can let go. If it happens to be a “hot” 120-V dc line, you will probably not be able to let, go, and a fatality could occur. Time plays an important role when this, happens, because the longer you are subjected to the dc voltage, the, more the resistance in the body decreases until a fatal current can be, established. The reason that we can let go of an ac line is best demonstrated by carefully examining the 120-V rms, 60-Hz voltage in Fig., 13.72. Since the voltage is oscillating, there is a period of time when the, voltage is near zero or less than, say, 20 V, and is reversing in direction., Although this time interval is very short, it appears every 8.3 ms and, provides a window to let go., Now that we are aware of the additional dangers of dc voltages, it is, important to mention that under the wrong conditions, dc voltages as, low as 12 V such as from a car battery can be quite dangerous. If you, happen to be working on a car under wet conditions, or if you are, sweating badly for some reason or, worse yet, wearing a wedding ring, that may have moisture and body salt underneath, touching the positive, terminal may initiate the process whereby the body resistance begins to, drop and serious injury could take place. It is one of the reasons you, seldom see a professional electrician wearing any rings or jewelry—it, is just not worth the risk., Before leaving this topic of safety concerns, you should also be, aware of the dangers of high-frequency supplies. We are all aware of, what 2.45 GHz at 120 V can do to a meat product in a microwave oven., As discussed in Chapter 5, it is therefore very important that the seal, around the oven be as tight as possible. However, don’t ever assume, that anything is absolutely perfect in design—so don’t make it a habit, to view the cooking process in the microwave 6 in. from the door on a
Page 621 :
APPLICATIONS, , , , 545, , continuing basis. Find something else to do, and check the food only, when the cooking process is complete. If you ever visit the Empire, State Building, you will notice that you are unable to get close to the, antenna on the dome due to the high-frequency signals being emitted, with a great deal of power. Also note the large KEEP OUT signs near, radio transmission towers for local radio stations. Standing within 10 ft, of an AM transmitter working at 540 kHz would bring on disaster. Simply holding (not to be tried!) a fluorescent bulb near the tower could, make it light up due to the excitation of the molecules inside the bulb., In total, therefore, treat any situation with high ac voltages or currents, high-energy dc levels, and high frequencies with added care., , Bulb Savers, Ever since the invention of the light bulb, consumers have clamored for, ways to extend the life of a bulb. I can remember the days when I was, taught to always turn a light off when leaving a room and not to play, with a light switch because it cost us a penny (at a time when a penny, had some real value) every time I turned the switch on and off. Through, advanced design we now have bulbs that are guaranteed to last a number of years. They cost more, but there is no need to replace the bulb as, often, and over time there is a financial savings. For some of us it is, simply a matter of having to pay so much for a single bulb., For interest sake, I measured the cold dc resistance of a standard, 60-W bulb and found it to be about 14 . Forgetting any inductive, effects due to the filament and wire, this would mean a current of, 120 V/14 8.6 A when the light is first turned on. This is a fairly, heavy current for the filament to absorb when you consider that the normal operating current is 60 W/120 V 0.5 A. Fortunately, it lasts for, only a few milliseconds, as shown in Fig. 13.73(a), before the bulb, heats up, causing the filament resistance to quickly increase and cut the, current down to reasonable levels. However, over time, hitting the bulb, with 8.6 A every time you turn the switch on will take its toll on the filament, and eventually the filament will simply surrender its natural, characteristics and open up. You can easily tell if a bulb is bad by simply shaking it and listening for the clinking sound of the broken filament hitting the bulb. Assuming an initial current of 8.6 A for a single, bulb, if the light switch controlled four 60-W bulbs in the same room,, the surge current through the switch could be as high as 4(8.6 A) , 34.4 A as shown in Fig. 13.73(b), which probably exceeds the rating of, the breaker (typically 20 A) for the circuit. However, the saving grace is, that it lasts for only a few milliseconds, and circuit breakers are not, designed to react that quickly. Even the GFI safety breakers in the bathroom are typically rated at a 5-ms response time. However, when you, look at the big picture and imagine all these spikes on the line generated throughout a residential community, it is certainly a problem that, the power company has to deal with on a continuing basis., One way to suppress this surge current is to place an inductor in, series with the bulb to choke out the spikes down the line. This method,, in fact, leads to one way of extending the life of a light bulb through the, use of dimmers. Any well-designed dimmer (such as the one described, in Chapter 12) has an inductor in the line to suppress current surges., The results are both an extended life for the bulb and the ability to control the power level. Left on in the full voltage position, the switch, could be used as a regular switch and the life of the bulb could be, , Ibulb (A), 8.6, , 0.5, 0, , 1, , 2, , 3, , 4, , 5, , 6, , 7 t (ms), , (a), , IT (A), four parallel 60-W bulbs, 34.4, , 2, 0, , 0.5, , 1, , 1.5, , 2, , t (s), , 250 ms, (b), , FIG 13.73, Surge currents: (a) single 60-W bulb; (b) four, parallel 60-W bulbs.
Page 622 :
546, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , V (volts), , V (volts), , Vapplied, , 170, , 170, 120 V rms, ac voltage, , 85, , 85, , 120°, 180°, 0, , 30°, , 150°, , Vbulb, , 360°, θ, , 0, –85, , –85, , –170, , –170, (a), , 180°, , 360°, t, , 90°, Turn-on, Dimmer ensures, bulb will not, turn on when, applied voltage is, near its maximum., (b), , FIG. 13.74, Turn-on voltage: (a) equal to or greater than one-half the peak value; (b) when, a dimmer is used., , extended. In fact, many dimmers now use triacs designed to turn on, only when the applied voltage passes through zero. If we look at the full, sine wave of Fig. 13.74(a), we find that the voltage is at least half of its, maximum value of 85 V for a full two-thirds of each cycle, or about, 67% of the time. The chances, therefore, of your turning on a light bulb, with at least 85 V on the line is far better than 2 to 1, so you can expect, the current for a 60-W light bulb to be at least 85 V/14 6 A 67%, of the time, which exceeds the rated 0.5-A rated value by 1100%. If we, use a dimmer with a triac designed to turn on only when the applied, voltage passes through zero or shortly thereafter, as shown in Fig., , (a), , 120-V rms line, +, Id, +0.7 V – +0.7 V, , Ilamp, (for positive region, of applied voltage), , High resistance, Id, , 170 V, peak, +, 168.6 V, , Lamp, , –, , –, , Low, resistance, , Open circuits for, positive region of, applied voltage, 0, High resistance, (diode open circuit), , Return, (b), , + Vd –, , Vd, (c), , FIG. 13.75, Bulb saver: (a) external appearance; (b) basic operation; (c) diode, characteristics at high current levels.
Page 623 :
COMPUTER ANALYSIS, , 13.74(b), the applied voltage will increase from about zero volts, giving, the bulb time to warm up before the full voltage is applied., Another commercial offering to extend the life of light bulbs is the, smaller circular disc shown in Fig. 13.75(a) which is inserted between, the bulb and the holder. Contacts are provided on both sides to permit, conduction through the simple diode network shown in Fig. 13.75(b)., You may recall from an earlier chapter that the voltage across diodes in, the on state is 0.7 V as shown for each diode in Fig. 13.75(b) for the, positive portion of the input voltage. The result is that the voltage to the, bulb is reduced by about 1.4 V throughout the cycle, reducing the, power delivered to the bulb. For most situations the reduced lighting is, not a problem, and the bulb will last longer simply because it is not, pressed to work at full output. However, the real saving in the device is, the manner in which it could help suppress the surge currents through, the light bulb. The true characteristics of a diode are shown in Fig., 13.75(c) for the full range of currents through the diode. For most, applications in electronic circuits, the vertical region is employed. For, excessive currents the diode characteristics flatten out as shown. This, region is characterized as having a large resistance (compared to very, small resistance of the vertical region) which will come into play when, the bulb is first turned on. In other words, when the bulb is first turned, on, the current will be so high that the diode will enter its high resistance region and by Ohm’s law will limit the surge current—thereby, extending the life of the bulb. The two diodes facing the other way are, for the negative portion of the supply voltage., New methods of extending the life of bulbs hit the marketplace every, day. All in all, however, one guaranteed way to extend the life of your, bulbs is to return to the old philosophy of turning lights off when you, leave a room, and “Don’t play with the light switch!”, , 13.10 COMPUTER ANALYSIS, PSpice (Windows), Schematics offer a variety of ac voltage and current sources. However,, for the purposes of this text, the voltage source VSIN and the current, source ISIN are the most appropriate because they have a list of attributes that will cover most areas of normal interest for sinusoidal networks. Under the library, SOURCE.slb, a number of others are listed,, but they don’t have the full range of the above or they are dedicated to, only one type of analysis. On occasion, ISRC will be used because it, has an arrow symbol like that appearing in the text, and it can be used, for dc, ac, and some transient analyses. The symbol for ISIN is simply, a sine wave which utilizes the plus-and-minus sign to indicate direction., The sources VAC, IAC, VSRC, and ISRC are fine if the magnitude and, phase of a specific quantity are desired or if a transient plot is against, frequency. However, they will not provide a transient response against, time even if the frequency and transient information are provided under, Analysis., For all of the sinusoidal sources, the magnitude entered and read is, the peak value of the waveform and not the rms value. This will become, clear when a plot of a quantity is desired and the magnitude calculated, by PSpice (Windows) is the peak value of the transient response. However, for a purely steady-state ac response, the magnitude provided can, , , , 547
Page 624 :
548, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , be the rms value, and the output read as the rms value. Only when a plot, is desired will it be clear that PSpice is accepting every ac magnitude as, the peak value of the waveform. Of course, the phase angle is the same, whether the magnitude is the peak or the rms value., A number of default values are set by PSpice if values are entered, for specific attributes of the source. If not specified, DC and AC values, are defaulted to 0, and Transient values default to the DC value. When, using VSIN, always specify VOFF as 0 V (unless a specific value is, part of the analysis), provide both the AC and the VAMPL values at the, same level, and provide the PHASE angle associated with the source., The TD (time delay), DF (damping factor), and DC value will all, default to 0 if not specified. Similar statements apply to ISIN. Additional information about the various types of sources can be found in, the Circuit Analysis User’s Guide or from Help., Each source can be obtained from the SOURCE.slb library using the, same procedure introduced in previous chapters. To set the attributes of, the source, double-click on the source, and double-click on each attribute, to be defined. The Value of each can then be entered directly in the box, provided. For each entry, be sure to Save Attr which will place the value, alongside the attribute in the listing below. If you would like an attribute, displayed, select Change Display, and when the Change Attribute dialog box appears, choose what you would like to display. The name and, value listed in the choice appear in the boxes at the top of the dialog box., To change the assigned name appearing with the symbol on the, schematic, simply choose PKGREF (package reference) and enter the, desired name. It will not appear on the schematic, however, unless you, follow through with the correct Change Display sequence., , C, The absence of any network configurations to analyze in this chapter, severely limits the content with respect to packaged computer programs. However, the door is still wide open for the application of a language to write programs that can be helpful in the application of some, of the concepts introduced in the chapter. In particular, let us examine, the C program of Fig. 13.76, designed to calculate the average value, of a pulse waveform having up to 5 different levels., The program begins with a heading and preprocessor directive., Recall that the iostream.h header file sets up the input-output path, between the program and the disk operating system. Note that the main, ( ) part of the program extends all the way down to the bottom, as identified by the braces { }. Within this region all the calculations will be, performed, and the results will be displayed., Within the main ( ) part of the program, all the variables to be, employed in the calculations are defined as floating point (decimal values) or integer (whole numbers). The comments on the right identify, each variable. This is followed by a display of the question about how, many levels will be encountered in the waveform using cout (comment, out). The cin (comment in) statement permits a response from the user., Next, the loop statement for is employed to establish a fixed number, of repetitions of the sequence appearing within the parentheses ( ) for, a number of loops defined by the variable levels. The format of this for, statement is such that the first entry within the parentheses ( ) is the initial value of the variable count (1 in this case), followed by a semicolon, and then a test expression determining how many times the sequence to, follow will be repeated. In other words, if levels is 5, then the first pass
Page 625 :
COMPUTER ANALYSIS, , Heading, Preprocessor, directive, , Define, form, and, name, of, variables, Obtain, # of, levels, Body, of, program, Iterative, for, statement, , Calculate Vave, Display, results, , FIG. 13.76, C program designed to calculate the average value of a waveform with up, to five positive or negative pulses., , through the for statement will result in 1 being compared to 5, and the, test expression will be satisfied because 5 is greater than or equal to 1, (< ). On the next pass, count will be increased to 2, and the same test, will be performed. Eventually count will equal 5, the test expression, will not be satisfied, and the program will move to its next statement,, which is Vave VT sum/ T. The last entry count of the for statement simply increments the variable count after each iteration. The first, line within the for statement calls for a line to be skipped, followed by, a question on the display about the level of voltage for the first time, interval. The question will include the current state of the count variable, followed by a colon. In C all character outputs must be displayed in, quotes (not required for numerical values). However, note the absence, of the quotes for count since it will be a numerical value. Next the user, enters the first voltage level through cin, followed by a request for the, time interval. In this case units are not provided but simply measured as, an increment of the whole; that is, if the total period is 5 ms and the first, interval is 2 ms, then just a 2 is entered., The area under the pulse is then calculated to establish the variable, VTsum, which was initially set at 0. On the next pass the value of, VTsum will be the value obtained by the first run plus the new area. In, other words, VTsum is a storage for the total accumulated area. Similarly, T is the accumulated sum of the time intervals., Following a FALSE response from the test expression of the for, statement, the program will move to calculate the average value of the, waveform using the accumulated values of the area and time. A line is, , , , 549
Page 626 :
550, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , v, 8V, , 4V, , 0V, 0, , 1, , 2, , 3, , 4, 5, –1 V, , t (ms), , –3 V, T, , FIG. 13.77, Waveform with five pulses to be analyzed by, the C program of Fig. 13.76., , then skipped and the average value is displayed with the remaining cout, statements. Brackets have been added along the edge of the program to, help identify the various components of the program., A program is now available that can find the average value of any, pulse waveform having up to five positive or negative pulses. It can be, placed in storage and simply called for when needed. Operations such as, the above are not available in either form of PSpice or in any commercially available software package. It took the knowledge of a language, and a few minutes of time to generate a short program of lifetime value., Two runs will clearly reveal what will be displayed and how the output will appear. The waveform of Fig. 13.77 has five levels, entered as, shown in the output file of Fig. 13.78. As indicated the average value is, 1.6 V. The waveform of Fig. 13.79 has only three pulses, and the time, interval for each is different. Note the manner in which the time intervals were entered. Each is entered as a multiplier of the standard unit of, measure for the horizontal axis. The variable levels will be only 3,, requiring only three iterations of the for statement. The result is a negative value of 0.933 V, as shown in the output file of Fig. 13.80., , v, 10 V, , 4V, , 0, , 1, , 2, , 3, , 4, , t (ms), , –6 V, T, , FIG. 13.79, Waveform with three pulses to be analyzed by, the C program of Fig. 13.76., , FIG. 13.78, Output results for the waveform of Fig. 13.77., , FIG. 13.80, Output results for the waveform of Fig. 13.79.
Page 627 :
PROBLEMS, , , , 551, , v (V), , PROBLEMS, 5, , SECTION 13.2 Sinusoidal ac Voltage Characteristics, and Definitions, 1. For the periodic waveform of Fig. 13.81:, a. Find the period T., b. How many cycles are shown?, c. What is the frequency?, *d. Determine the positive amplitude and peak-to-peak, value (think!)., , 0, , 6, , 8, , 10, , 16, , FIG. 13.81, Problem 1., , 2. Repeat Problem 1 for the periodic waveform of Fig., 13.82., v (V), 10, , 0, , 5, , 10, , 15, , 20, , 25, , 30, , 35, , 36, , t (ms), , –10, , FIG. 13.82, Problems 2, 9, and 47., 3. Determine the period and frequency of the sawtooth, waveform of Fig. 13.83., v (V), 20, , 0, , 6, , 16, , 26, , FIG. 13.83, Problems 3 and 48., 4. Find the period of a periodic waveform whose frequency is, a. 25 Hz., b. 35 MHz., c. 55 kHz., d. 1 Hz., 5. Find the frequency of a repeating waveform whose, period is, a. 1/60 s., b. 0.01 s., c. 34 ms., d. 25 ms., 6. Find the period of a sinusoidal waveform that completes, 80 cycles in 24 ms., 7. If a periodic waveform has a frequency of 20 Hz, how, long (in seconds) will it take to complete five cycles?, 8. What is the frequency of a periodic waveform that completes 42 cycles in 6 s?, 9. Sketch a periodic square wave like that appearing in Fig., 13.82 with a frequency of 20,000 Hz and a peak value of, 10 mV., , t (ms), , 18 20, , t (ms)
Page 628 :
552, , , , SINUSOIDAL ALTERNATING WAVEFORMS, 10. For the oscilloscope pattern of Fig. 13.84:, a. Determine the peak amplitude., b. Find the period., c. Calculate the frequency., Redraw the oscilloscope pattern if a 25-mV dc level, were added to the input waveform., SECTION 13.3 The Sine Wave, , Vertical sensitivity = 50 mV/div., Horizontal sensitivity = 10 s/div., , FIG. 13.84, Problem 10., , 11. Convert the following degrees to radians:, a. 45°, b. 60°, c. 120°, d. 270°, e. 178°, f. 221°, 12. Convert the following radians to degrees:, a. p/4, b. p/6, 7, 1, c. 10p, d. 6p, e. 3p, f. 0.55p, 13. Find the angular velocity of a waveform with a period of, a. 2 s., b. 0.3 ms., 1, c. 4 ms., d. 26 s., 14. Find the angular velocity of a waveform with a frequency, of, a. 50 Hz., b. 600 Hz., c. 2 kHz., d. 0.004 MHz., 15. Find the frequency and period of sine waves having an, angular velocity of, a. 754 rad/s., b. 8.4 rad/s., 1, c. 6000 rad/s., d. 16 rad/s., 16. Given f 60 Hz, determine how long it will take the, sinusoidal waveform to pass through an angle of 45°., 17. If a sinusoidal waveform passes through an angle of 30°, in 5 ms, determine the angular velocity of the waveform., SECTION 13.4 General Format for the Sinusoidal, Voltage or Current, 18. Find the amplitude and frequency of the following, waves:, a. 20 sin 377t, b. 5 sin 754t, c. 106 sin 10,000t, d. 0.001 sin 942t, 1, e. 7.6 sin 43.6t, f. (42 ) sin 6.283t, 19. Sketch 5 sin 754t with the abscissa, a. angle in degrees., b. angle in radians., c. time in seconds., 20. Sketch 106 sin 10,000t with the abscissa, a. angle in degrees., b. angle in radians., c. time in seconds., 21. Sketch 7.6 sin 43.6t with the abscissa, a. angle in degrees., b. angle in radians., c. time in seconds., 22. If e 300 sin 157t, how long (in seconds) does it take, this waveform to complete 1/2 cycle?, 23. Given i 0.5 sin a, determine i at a 72°., 24. Given v 20 sin a, determine v at a 1.2p., *25. Given v 30 103 sin a, determine the angles at, which v will be 6 mV.
Page 629 :
GLOSSARY, *26. If v 40 V at a 30° and t 1 ms, determine the, mathematical expression for the sinusoidal voltage., SECTION 13.5 Phase Relations, 27. Sketch sin(377t 60°) with the abscissa, a. angle in degrees., b. angle in radians., c. time in seconds., 28. Sketch the following waveforms:, a. 50 sin(qt 0°), b. 20 sin(qt 2°), c. 5 sin(qt 60°), d. 4 cos qt, e. 2 cos(qt 10°), f. 5 cos(qt 20°), 29. Find the phase relationship between the waveforms of, each set:, a. v 4 sin(qt 50°), i 6 sin(qt 40°), b. v 25 sin(qt 80°), i 5 103 sin(qt 10°), c. v 0.2 sin(qt 60°), i 0.1 sin(qt 20°), d. v 200 sin(qt 210°), i 25 sin(qt 60°), *30. Repeat Problem 29 for the following sets:, a. v 2 cos(qt 30°), b. v 1 sin(qt 20°), i 5 sin(qt 60°), i 10 sin(qt 70°), c. v 4 cos(qt 90°), i 2 sin(qt 10°), 31. Write the analytical expression for the waveforms of Fig., 13.85 with the phase angle in degrees., v (V), , i (A), f = 1000 Hz, f = 60 Hz, , 25, , 2p, 3, qt, , 0, , qt, , 0, , p, 6, , –3 × 10–3, (a), , (b), , FIG. 13.85, Problem 31., 32. Repeat Problem 31 for the waveforms of Fig. 13.86., v (V), , i (A), f = 25 Hz, , 0.01, , 2 × 10–3, f = 10 kHz, , 0, , qt, , 11 p, 18, , t, , 0, 3p, 4, , (a), , (b), , FIG. 13.86, Problem 32., , , , 553
Page 630 :
554, , , , SINUSOIDAL ALTERNATING WAVEFORMS, *33. The sinusoidal voltage v 200 sin(2p1000t 60°) is, plotted in Fig. 13.87. Determine the time t1., *34. The sinusoidal current i 4 sin(50,000t 40°) is plotted in Fig. 13.88. Determine the time t1., v, , i, , 200, , 4A, t1, , 0, , –p, , t1, , p, , 60°, , FIG. 13.87, Problem 33., , 2p, , t, , –p, , 0, , p, , t1, , 2p, , t (ms), , 40°, , FIG. 13.88, Problem 34., , *35. Determine the phase delay in milliseconds between the, following two waveforms:, e, , v 60 sin(1800t 20°), i 1.2 sin(1800t 20°), , i, , 36. For the oscilloscope display of Fig. 13.89:, a. Determine the period of each waveform., b. Determine the frequency of each waveform., c. Find the rms value of each waveform., d. Determine the phase shift between the two waveforms, and which leads or lags., Vertical sensitivity = 0.5 V/div., Horizontal sensitivity = 1 ms/div., , FIG. 13.89, Problem 36., , SECTION 13.6 Average Value, 37. For the waveform of Fig. 13.90:, a. Determine the period., b. Find the frequency., c. Determine the average value., d. Sketch the resulting oscilloscope display if the vertical channel is switched from DC to AC., , Vertical sensitivity = 10 mV/div., Horizontal sensitivity = 0.2 ms/div., , FIG. 13.90, Problem 37.
Page 631 :
PROBLEMS, , , , 555, , 38. Find the average value of the periodic waveforms of Fig., 13.91 over one full cycle., v (V), , i (mA), 20, , 6, 3, 1, , 0, , 2, , 3, , 0, –8, , t (s), , 4, , 6, , 8, , t (ms), , –3, 1 cycle, , (a), , (b), , FIG. 13.91, Problem 38., 39. Find the average value of the periodic waveforms of Fig., 13.92 over one full cycle., v (V), , i (mA), 1 cycle, , 10, , 10, , 5, 0, , 5, 1, , 2, , 3, , 4, , 5, , 6 7, , 8, , 9, , 10, , –5, , p, 4, , 0, –5, –10, –15, , t (s), , –10, , p, , p, 2, , 3p, 2, Sine wave, , 1 cycle, (a), , (b), , FIG. 13.92, Problem 39., *40. a. By the method of approximation, using familiar geometric shapes, find the area under the curve of Fig., 13.93 from zero to 10 s. Compare your solution with, the actual area of 5 volt-seconds (V• s)., b. Find the average value of the waveform from zero to, 10 s., v (V), 1, , 0.993, 0.981, , v = e–t, , 0.951, 0.865, , 0.368, , v = 1 – e–t, 0.632, , 0.135, 0.049, 0.019, 0.007, , 0, , 1, , 2, , 3, , 4, , 5, , 6, , 7, , FIG. 13.93, Problem 40., , 8, , 9, , 10, , t (s), , 2p, , qt
Page 632 :
556, , , , SINUSOIDAL ALTERNATING WAVEFORMS, *41. For the waveform of Fig. 13.94:, a. Determine the period., b. Find the frequency., c. Determine the average value., d. Sketch the resulting oscilloscope display if the vertical channel is switched from DC to AC., , Vertical sensitivity = 10 mV/div., Horizontal sensitivity = 10 s/div., , FIG. 13.94, Problem 41., , SECTION 13.7 Effective Values, 42. Find the effective values of the following sinusoidal, waveforms:, a. v 20 sin 754t, b. v 7.07 sin 377t, c. i 0.006 sin(400t 20°), d. i 16 103 sin(377t 10°), 43. Write the sinusoidal expressions for voltages and currents having the following effective values at a frequency, of 60 Hz with zero phase shift:, a. 1.414 V, b. 70.7 V, c. 0.06 A, d. 24 mA, 44. Find the effective value of the periodic waveform of Fig., 13.95 over one full cycle., 45. Find the effective value of the periodic waveform of Fig., 13.96 over one full cycle., v (V), , v (V), 3, , 1 cycle, , 3, , 1 cycle, , 2, , 2, , 1, , 1, 0, –1, , 1, , 2, , 3, , 4, , 5, , 6, , 7, , 8, , 9, , 10 11 12, , t (s), , 0, –1, , 1, , 2, , 3, , 4, , 5, , 6 7, , 8, , 9, , 10 11, , 12, , t (s), , –2, , –2, , –3, , FIG. 13.96, Problem 45., , FIG. 13.95, Problem 44., v (V), , 46. What are the average and effective values of the square, wave of Fig. 13.97?, 1 cycle, , 47. What are the average and effective values of the waveform of Fig. 13.82?, , 10, , 48. What is the average value of the waveform of Fig. 13.83?, 0, , 4, , –10, , FIG. 13.97, Problem 46., , 8, , t (ms)
Page 633 :
GLOSSARY, , , , 557, , 49. For each waveform of Fig. 13.98, determine the period,, frequency, average value, and effective value., , Vertical sensitivity = 20 mV/div., Horizontal sensitivity = 10 , s/div., (a), , Vertical sensitivity = 0.2 V/div., Horizontal sensitivity = 50 , s/div., (b), PH_Boylestad, , FIG. 13.98, Problem 49., SECTION 13.8 ac Meters and Instruments, 50. Determine the reading of the meter for each situation of, Fig. 13.99., d’Arsonval movement, , ac, , Idc = 4 mA, rms scale, (half-wave, rectifier), , +, , +, 2 k, , v = 16 sin(377t + 20°), , –, , –, , Voltmeter, (a), , (b), , FIG. 13.99, Problem 50., SECTION 13.10 Computer Analysis, Programming Language (C, BASIC, Pascal, etc.), 51. Given a sinusoidal function, write a program to determine the effective value, frequency, and period., 52. Given two sinusoidal functions, write a program to determine the phase shift between the two waveforms, and, indicate which is leading or lagging., 53. Given an alternating pulse waveform, write a program to, determine the average and effective values of the waveform over one complete cycle., , GLOSSARY, Alternating waveform A waveform that oscillates above, and below a defined reference level., Amp-Clamp® A clamp-type instrument that will permit noninvasive current measurements and that can be used as a conventional voltmeter or ohmmeter., , Angular velocity The velocity with which a radius vector, projecting a sinusoidal function rotates about its center., Average value The level of a waveform defined by the condition that the area enclosed by the curve above this level is, exactly equal to the area enclosed by the curve below this, level.
Page 634 :
558, , , , SINUSOIDAL ALTERNATING WAVEFORMS, , Cycle A portion of a waveform contained in one period of time., Effective value The equivalent dc value of any alternating, voltage or current., Electrodynamometer meters Instruments that can measure, both ac and dc quantities without a change in internal circuitry., Frequency ( f ) The number of cycles of a periodic waveform, that occur in 1 second., Frequency counter An instrument that will provide a digital, display of the frequency or period of a periodic time-varying signal., Instantaneous value The magnitude of a waveform at any, instant of time, denoted by lowercase letters., Oscilloscope An instrument that will display, through the use, of a cathode-ray tube, the characteristics of a time-varying, signal., Peak amplitude The maximum value of a waveform as measured from its average, or mean, value, denoted by uppercase letters., Peak-to-peak value The magnitude of the total swing of, a signal from positive to negative peaks. The sum of the, absolute values of the positive and negative peak values., , Peak value The maximum value of a waveform, denoted by, uppercase letters., Period (T ) The time interval between successive repetitions, of a periodic waveform., Periodic waveform A waveform that continually repeats, itself after a defined time interval., Phase relationship An indication of which of two waveforms leads or lags the other, and by how many degrees or, radians., Radian (rad) A unit of measure used to define a particular, segment of a circle. One radian is approximately equal to, 57.3°; 2p rad are equal to 360°., Root-mean-square (rms) value The root-mean-square or, effective value of a waveform., Sinusoidal ac waveform An alternating waveform of unique, characteristics that oscillates with equal amplitude above, and below a given axis., VOM A multimeter with the capability to measure resistance, and both ac and dc levels of current and voltage., Waveform The path traced by a quantity, plotted as a function of some variable such as position, time, degrees, temperature, and so on.
Page 635 :
−, +, , CHAPTER, , Operational, Amplifiers, , 14, , 14.1 INTRODUCTION, An operational amplifier, or op-amp, is a very high gain differential amplifier with, high input impedance and low output impedance. Typical uses of the operational amplifier are to provide voltage amplitude changes (amplitude and polarity), oscillators,, filter circuits, and many types of instrumentation circuits. An op-amp contains a number of differential amplifier stages to achieve a very high voltage gain., Figure 14.1 shows a basic op-amp with two inputs and one output as would result using a differential amplifier input stage. Recall from Chapter 12 that each input, results in either the same or an opposite polarity (or phase) output, depending on, whether the signal is applied to the plus () or the minus () input., , +, , Input 1, , Output, , –, , Input 2, , Figure 14.1 Basic op-amp., , Single-Ended Input, Single-ended input operation results when the input signal is connected to one input, with the other input connected to ground. Figure 14.2 shows the signals connected, , +, , +, Vo, , Vo, Vi, , –, , –, Vi, , (a), , Figure 14.2 Single-ended operation., , (b), , 609
Page 636 :
−, +, , for this operation. In Fig. 14.2a, the input is applied to the plus input (with minus input at ground), which results in an output having the same polarity as the applied input signal. Figure 14.2b shows an input signal applied to the minus input, the output, then being opposite in phase to the applied signal., , Double-Ended (Differential) Input, In addition to using only one input, it is possible to apply signals at each input—this, being a double-ended operation. Figure 14.3a shows an input, Vd, applied between, the two input terminals (recall that neither input is at ground), with the resulting amplified output in phase with that applied between the plus and minus inputs. Figure, 14.3b shows the same action resulting when two separate signals are applied to the, inputs, the difference signal being Vi1 Vi2., , +, , +, Vo, , Vd, , Vo, , Vd, V1, , –, , –, V2, , (a), , (b), , Figure 14.3 Double-ended (differential) operation., , Vi 1, , Vi 2, , +, , Vo1, , –, , Vo 2, , Figure 14.4 Double-ended, output., , +, , Double-Ended Output, While the operation discussed so far had a single output, the op-amp can also be operated with opposite outputs, as shown in Fig. 14.4. An input applied to either input, will result in outputs from both output terminals, these outputs always being opposite in polarity. Figure 14.5 shows a single-ended input with a double-ended output., As shown, the signal applied to the plus input results in two amplified outputs of opposite polarity. Figure 14.6 shows the same operation with a single output measured, , Vo1, , +, , Vo1, Vd, , –, , Vi, , Vo 2, , –, , Figure 14.5 Double-ended output with single-ended input., , 610, , Chapter 14, , Operational Amplifiers, , Vo 2, , Figure 14.6 Double-ended output.
Page 637 :
−, , between output terminals (not with respect to ground). This difference output signal, is Vo1 Vo2. The difference output is also referred to as a floating signal since neither output terminal is the ground (reference) terminal. Notice that the difference output is twice as large as either Vo1 or Vo2 since they are of opposite polarity and subtracting them results in twice their amplitude [i.e., 10 V (10 V) 20 V]. Figure, 14.7 shows a differential input, differential output operation. The input is applied between the two input terminals and the output taken from between the two output terminals. This is fully differential operation., , +, , Figure 14.7 Differential-input,, differential-output operation., , Common-Mode Operation, When the same input signals are applied to both inputs, common-mode operation results, as shown in Fig. 14.8. Ideally, the two inputs are equally amplified, and since, they result in opposite polarity signals at the output, these signals cancel, resulting in, 0-V output. Practically, a small output signal will result., , Figure 14.8 Common-mode, operation., , Common-Mode Rejection, A significant feature of a differential connection is that the signals which are opposite at the inputs are highly amplified, while those which are common to the two inputs are only slightly amplified—the overall operation being to amplify the difference signal while rejecting the common signal at the two inputs. Since noise (any, unwanted input signal) is generally common to both inputs, the differential connection tends to provide attenuation of this unwanted input while providing an amplified, output of the difference signal applied to the inputs. This operating feature, referred, to as common-mode rejection, is discussed more fully in the next section., , 14.2 DIFFERENTIAL AND COMMONMODE OPERATION, One of the more important features of a differential circuit connection, as provided, in an op-amp, is the circuit’s ability to greatly amplify signals that are opposite at the, two inputs, while only slightly amplifying signals that are common to both inputs. An, 14.2, , Differential and Common-Mode Operation, , 611
Page 638 :
−, +, , op-amp provides an output component that is due to the amplification of the difference of the signals applied to the plus and minus inputs and a component due to the, signals common to both inputs. Since amplification of the opposite input signals is, much greater than that of the common input signals, the circuit provides a commonmode rejection as described by a numerical value called the common-mode rejection, ratio (CMRR)., , Differential Inputs, When separate inputs are applied to the op-amp, the resulting difference signal is the, difference between the two inputs., Vd Vi1 Vi2, , (14.1), , Common Inputs, When both input signals are the same, a common signal element due to the two inputs can be defined as the average of the sum of the two signals., Vc 12(Vi1 Vi2), , (14.2), , Output Voltage, Since any signals applied to an op-amp in general have both in-phase and out-ofphase components, the resulting output can be expressed as, Vo AdVd AcVc, , (14.3), , where Vd difference voltage given by Eq. (14.1), Vc common voltage given by Eq. (14.2), Ad differential gain of the amplifier, Ac common-mode gain of the amplifier, , Opposite Polarity Inputs, If opposite polarity inputs applied to an op-amp are ideally opposite signals, Vi1 , Vi2 Vs, the resulting difference voltage is, Eq. (14.1): Vd Vi1 Vi2 Vs (Vs) 2Vs, while the resulting common voltage is, Eq. (14.2): Vc 12(Vi1 Vi2) 12[Vs (Vs)] 0, so that the resulting output voltage is, Eq. (14.3): Vo AdVd AcVc Ad (2Vs) 0 2 AdVs, This shows that when the inputs are an ideal opposite signal (no common element),, the output is the differential gain times twice the input signal applied to one of the, inputs., , Same Polarity Inputs, If the same polarity inputs are applied to an op-amp, Vi1 Vi2 Vs, the resulting difference voltage is, Eq. (14.1): Vd Vi1 Vi2 Vs Vs 0, 612, , Chapter 14, , Operational Amplifiers
Page 639 :
−, +, , while the resulting common voltage is, Eq. (14.2): Vc 12(Vi1 Vi2) 12(Vs Vs) Vs, so that the resulting output voltage is, Eq. (14.3): Vo AdVd AcVc Ad(0) AcVs AcVs, This shows that when the inputs are ideal in-phase signals (no difference signal), the, output is the common-mode gain times the input signal, Vs, which shows that only, common-mode operation occurs., , Common-Mode Rejection, The solutions above provide the relationships that can be used to measure Ad and Ac, in op-amp circuits., 1. To measure Ad: Set Vi1 Vi2 Vs 0.5 V, so that, Eq. (14.1): Vd (Vi1 Vi2) (0.5 V (0.5 V) 1 V, and, , Eq. (14.2): Vc 12(Vi1 Vi2) 12[0.5 V (0.5 V)] 0 V, , Under these conditions the output voltage is, Eq. (14.3): Vo AdVd AcVc Ad(1 V) Ac(0) Ad, Thus, setting the input voltages Vi1 Vi2 0.5 V results in an output voltage, numerically equal to the value of Ad., 2. To measure Ac: Set Vi1 Vi2 Vs 1 V, so that, Eq. (14.1): Vd (Vi1 Vi2) (1 V 1 V) 0 V, and, , Eq. (14.2): Vc 12(Vi1 Vi2) 12(1 V 1 V) 1 V, , Under these conditions the output voltage is, Eq. (14.3): Vo AdVd AcVc Ad (0 V) Ac(1 V) Ac, Thus, setting the input voltages Vi1 Vi2 1 V results in an output voltage, numerically equal to the value of Ac., , Common-Mode Rejection Ratio, Having obtained Ad and Ac (as in the measurement procedure discussed above), we, can now calculate a value for the common-mode rejection ratio (CMRR), which is, defined by the following equation:, Ad, CMRR , Ac, , (14.4), , The value of CMRR can also be expressed in logarithmic terms as, Ad, CMRR (log) 20 log10 , Ac, , 14.2, , (dB), , (14.5), , Differential and Common-Mode Operation, , 613
Page 641 :
−, +, , It should be clear that the desired operation will have Ad very large with Ac very, small. That is, the signal components of opposite polarity will appear greatly amplified at the output, whereas the signal components that are in phase will mostly cancel out so that the common-mode gain, Ac, is very small. Ideally, the value of the, CMRR is infinite. Practically, the larger the value of CMRR, the better the circuit operation., We can express the output voltage in terms of the value of CMRR as follows:, AcVc, Eq. (14.3): Vo AdVd AcVc AdVd 1 , AdVd, , , , , , Using Eq. (14.4), we can write the above as, 1, Vc, Vo AdVd 1 , CMRR Vd, , , , , , (14.6), , Even when both Vd and Vc components of signal are present, Eq. (14.6) shows that, for large values of CMRR, the output voltage will be due mostly to the difference, signal, with the common-mode component greatly reduced or rejected. Some practical examples should help clarify this idea., Determine the output voltage of an op-amp for input voltages of Vi1 150 V, Vi2 , 140 V. The amplifier has a differential gain of Ad 4000 and the value of CMRR, is:, (a) 100., (b) 105., , EXAMPLE 14.2, , Solution, Eq. (14.1): Vd Vi1 Vi2 (150 140) V 10 V, 1, 150 V 140 V, Eq. (14.2): Vc (Vi1 Vi2) 145 V, 2, 2, 1, Vc, (a) Eq. (14.6): Vo AdVd 1 , CMRR Vd, 1 145 V, (4000)(10 V) 1 , 100 10 V, 40 mV(1.145) 45.8 mV, 1 145 V, (b) Vo (4000)(10 V) 1 5 40 mV(1.000145) 40.006 mV, 10 10 V, , , , , , , , , , , , , , Example 14.2 shows that the larger the value of CMRR, the closer the output voltage is to the difference input times the difference gain with the common-mode signal being rejected., , 14.3 OP-AMP BASICS, An operational amplifier is a very high gain amplifier having very high input impedance (typically a few megohms) and low output impedance (less than 100 ). The, basic circuit is made using a difference amplifier having two inputs (plus and minus), and at least one output. Figure 14.10 shows a basic op-amp unit. As discussed ear14.3, , OP-AMP Basics, , 615
Page 642 :
−, +, , Figure 14.10, , Basic op-amp., , lier, the plus () input produces an output that is in phase with the signal applied,, while an input to the minus () input results in an opposite polarity output. The ac, equivalent circuit of the op-amp is shown in Fig. 14.11a. As shown, the input signal, applied between input terminals sees an input impedance, Ri, typically very high. The, output voltage is shown to be the amplifier gain times the input signal taken through, an output impedance, Ro, which is typically very low. An ideal op-amp circuit, as, shown in Fig. 14.11b, would have infinite input impedance, zero output impedance,, and an infinite voltage gain., , Ro, , Vd, , Ri, , Ad Vd, , Vo, , (a), , Vd, , Ad Vd, , Vo, , (b), , Figure 14.11 Ac equivalent of op-amp circuit: (a) practical; (b) ideal., , Basic Op-Amp, The basic circuit connection using an op-amp is shown in Fig. 14.12. The circuit, shown provides operation as a constant-gain multiplier. An input signal, V1, is applied, through resistor R1 to the minus input. The output is then connected back to the same, minus input through resistor Rf. The plus input is connected to ground. Since the signal V1 is essentially applied to the minus input, the resulting output is opposite in, phase to the input signal. Figure 14.13a shows the op-amp replaced by its ac equivalent circuit. If we use the ideal op-amp equivalent circuit, replacing Ri by an infinite, resistance and Ro by zero resistance, the ac equivalent circuit is that shown in Fig., 14.13b. The circuit is then redrawn, as shown in Fig. 14.13c, from which circuit analysis is carried out., , Figure 14.12, , 616, , Chapter 14, , Operational Amplifiers, , Basic op-amp connection.
Page 644 :
−, +, , Vo, Rf, , V1, R1, , so that, , (14.8), , The result, in Eq. (14.8), shows that the ratio of overall output to input voltage is dependent only on the values of resistors R1 and Rf —provided that Av is very large., , Unity Gain, If Rf R1, the gain is, Rf, voltage gain 1, R1, so that the circuit provides a unity voltage gain with 180° phase inversion. If Rf is exactly R1, the voltage gain is exactly 1., , Constant Magnitude Gain, If Rf is some multiple of R1, the overall amplifier gain is a constant. For example, if, Rf 10R1, then, Rf, voltage gain 10, R1, and the circuit provides a voltage gain of exactly 10 along with an 180° phase inversion from the input signal. If we select precise resistor values for Rf and R1, we can, obtain a wide range of gains, the gain being as accurate as the resistors used and is, only slightly affected by temperature and other circuit factors., , Virtual Ground, The output voltage is limited by the supply voltage of, typically, a few volts. As stated, before, voltage gains are very high. If, for example, Vo 10 V and Av 20,000,, the input voltage would then be, 10 V, Vo, Vi 0.5 mV, 20,000, Av, If the circuit has an overall gain (Vo /V1) of, say, 1, the value of V1 would then be, 10 V. Compared to all other input and output voltages, the value of Vi is then small, and may be considered 0 V., Note that although Vi 0 V, it is not exactly 0 V. (The output voltage is a few, volts due to the very small input Vi times a very large gain Av.) The fact that Vi , 0 V leads to the concept that at the amplifier input there exists a virtual short circuit, or virtual ground., The concept of a virtual short implies that although the voltage is nearly 0 V, there, is no current through the amplifier input to ground. Figure 14.14 depicts the virtual, ground concept. The heavy line is used to indicate that we may consider that a short, , Figure 14.14, an op-amp., , 618, , Chapter 14, , Operational Amplifiers, , Virtual ground in
Page 645 :
−, , exists with Vi 0 V but that this is a virtual short so that no current goes through the, short to ground. Current goes only through resistors R1 and Rf as shown., Using the virtual ground concept, we can write equations for the current I as follows:, , +, , V1, Vo, I , R1, Rf, which can be solved for Vo /V1:, Vo, Rf, , V1, R1, The virtual ground concept, which depends on Av being very large, allowed a simple, solution to determine the overall voltage gain. It should be understood that although, the circuit of Fig. 14.14 is not physically correct, it does allow an easy means for determining the overall voltage gain., , 14.4 PRACTICAL OP-AMP CIRCUITS, The op-amp can be connected in a large number of circuits to provide various operating characteristics. In this section, we cover a few of the most common of these circuit connections., , Inverting Amplifier, The most widely used constant-gain amplifier circuit is the inverting amplifier, as, shown in Fig. 14.15. The output is obtained by multiplying the input by a fixed or, constant gain, set by the input resistor (R1) and feedback resistor (Rf)—this output, also being inverted from the input. Using Eq. (14.8) we can write, Rf, Vo V1, R1, , Rf, , –, , V1, R1, , Op-amp, , Vo = −, , Rf, V, R1 1, , +, , Figure 14.15 Inverting constant-gain multiplier., , If the circuit of Fig. 14.15 has R1 100 k and Rf 500 k, what output voltage, results for an input of V1 2 V?, , EXAMPLE 14.3, , Solution, Rf, 500 k, Eq. (14.8): Vo V1 (2 V) 10 V, R1, 100 k, , 14.4 Practical OP-AMP Circuits, , 619
Page 646 :
−, +, , Noninverting Amplifier, The connection of Fig. 14.16a shows an op-amp circuit that works as a noninverting, amplifier or constant-gain multiplier. It should be noted that the inverting amplifier, connection is more widely used because it has better frequency stability (discussed, later). To determine the voltage gain of the circuit, we can use the equivalent representation shown in Fig. 14.16b. Note that the voltage across R1 is V1 since Vi 0 V., This must be equal to the output voltage, through a voltage divider of R1 and Rf, so, that, R1, V1 Vo, R1 Rf, which results in, Rf, Vo, R1 Rf, 1 , R1, R1, V1, , (14.9), , +, , V1, , (, , Vo = 1 +, , Op-amp, , Rf, V, R1 1, , ), , Vi ≈ 0, V1, , –, , Rf, Vo, , R1, Rf, R1, , (a), , (b), , Figure 14.16 Noninverting constant-gain multiplier., , EXAMPLE 14.4, , Calculate the output voltage of a noninverting amplifier (as in Fig. 14.16) for values, of V1 2 V, Rf 500 k, and R1 100 k., , Solution, 500 k, Rf, Eq. (14.9): Vo 1 V1 1 (2 V) 6(2 V) 12 V, 100 k, R1, , , , , , , , , , Unity Follower, The unity-follower circuit, as shown in Fig. 14.17a, provides a gain of unity (1) with, no polarity or phase reversal. From the equivalent circuit (see Fig. 14.17b) it is clear, that, Vo V1, , (14.10), , and that the output is the same polarity and magnitude as the input. The circuit operates like an emitter- or source-follower circuit except that the gain is exactly unity., 620, , Chapter 14, , Operational Amplifiers
Page 647 :
−, +, , Figure 14.17 (a) Unity follower; (b) virtual-ground equivalent circuit., , Summing Amplifier, Probably the most used of the op-amp circuits is the summing amplifier circuit shown, in Fig. 14.18a. The circuit shows a three-input summing amplifier circuit, which provides a means of algebraically summing (adding) three voltages, each multiplied by, a constant-gain factor. Using the equivalent representation shown in Fig. 14.18b, the, output voltage can be expressed in terms of the inputs as, Rf, Rf, Rf, Vo V1 V2 V3, R1, R2, R3, , , , , , (14.11), , In other words, each input adds a voltage to the output multiplied by its separate constant-gain multiplier. If more inputs are used, they each add an additional component, to the output., , Figure 14.18 (a) Summing amplifier; (b) virtual-ground equivalent circuit., , Calculate the output voltage of an op-amp summing amplifier for the following sets, of voltages and resistors. Use Rf 1 M in all cases., (a) V1 1 V, V2 2 V, V3 3 V, R1 500 k, R2 1 M, R3 1 M., (b) V1 2 V, V2 3 V, V3 1 V, R1 200 k, R2 500 k, R3 1 M., 14.4 Practical OP-AMP Circuits, , EXAMPLE 14.5, , 621
Page 648 :
−, +, , Solution, Using Eq. (14.11):, 1000 k, 1000 k, 1000 k, (a) Vo (1 V) (2 V) (3 V), 500 k, 1000 k, 1000 k, [2(1 V) 1(2 V) 1(3 V)] 7 V, 1000 k, 1000 k, 1000 k, (b) Vo (2 V) (3 V) (1 V), 200 k, 500 k, 1000 k, [5(2 V) 2(3 V) 1(1 V)] 3 V, , , , , , , , , , Integrator, So far, the input and feedback components have been resistors. If the feedback component used is a capacitor, as shown in Fig. 14.19a, the resulting connection is called, an integrator. The virtual-ground equivalent circuit (Fig. 14.19b) shows that an expression for the voltage between input and output can be derived in terms of the current I, from input to output. Recall that virtual ground means that we can consider, the voltage at the junction of R and XC to be ground (since Vi 0 V) but that no current goes into ground at that point. The capacitive impedance can be expressed as, 1, 1, XC , j C, sC, , Figure 14.19 Integrator., , where s j is in the Laplace notation.* Solving for Vo/V1 yields, V1, Vo, Vo, I sCVo, R, XC, 1/sC, Vo, 1, , V1, sCR, , (14.12), , The expression above can be rewritten in the time domain as, 1, vo(t) , RC, , v (t) dt, 1, , (14.13), , *Laplace notation allows expressing differential or integral operations which are part of calculus in algebraic, form using the operator s. Readers unfamiliar with calculus should ignore the steps leading to Eq. (14.13) and, follow the physical meaning used thereafter., , 622, , Chapter 14, , Operational Amplifiers
Page 649 :
−, +, , Equation (14.13) shows that the output is the integral of the input, with an inversion and scale multiplier of 1/RC. The ability to integrate a given signal provides the, analog computer with the ability to solve differential equations and therefore provides, the ability to electrically solve analogs of physical system operation., The integration operation is one of summation, summing the area under a waveform or curve over a period of time. If a fixed voltage is applied as input to an integrator circuit, Eq. (14.13) shows that the output voltage grows over a period of time,, providing a ramp voltage. Equation (14.13) can thus be understood to show that the, output voltage ramp (for a fixed input voltage) is opposite in polarity to the input voltage and is multiplied by the factor 1/RC. While the circuit of Fig. 14.19 can operate, on many varied types of input signals, the following examples will use only a fixed, input voltage, resulting in a ramp output voltage., As an example, consider an input voltage, V1 1 V, to the integrator circuit of, Fig. 14.20a. The scale factor of 1/RC is, 1, 1, 1, RC, (1 M)(1 F), so that the output is a negative ramp voltage as shown in Fig. 14.20b. If the scale factor is changed by making R 100 k, for example, then, 1, 1, 10, RC, (100 k)(1 F), and the output is then a steeper ramp voltage, as shown in Fig. 14.20c., , C = 1 µF, , υ1 (t) = 1 V, , R, , 0V, , –, , 0V, , 1 MΩ, , (− RC1 = −1), , υo (t), , Op-amp, , +, , −1 V, , (b), , (a), , (−RC1 = −10), −10 V, , (c), , Figure 14.20 Operation of integrator with step input., , More than one input may be applied to an integrator, as shown in Fig. 14.21, with, the resulting operation given by, , , , 1, vo(t) , R1C, , v (t) dt R1C v (t) dt R1C v (t) dt, 1, , 2, , 2, , 3, , (14.14), , 3, , An example of a summing integrator as used in an analog computer is given in, Fig. 14.21. The actual circuit is shown with input resistors and feedback capacitor,, whereas the analog-computer representation indicates only the scale factor for each, input., 14.4 Practical OP-AMP Circuits, , 623
Page 651 :
−, +, , 14.5 OP-AMP SPECIFICATIONS—DC, OFFSET PARAMETERS, Before going into various practical applications using op-amps, we should become, familiar with some of the parameters used to define the operation of the unit. These, specifications include both dc and transient or frequency operating features, as covered next., , Offset Currents and Voltages, While the op-amp output should be 0 V when the input is 0 V, in actual operation, there is some offset voltage at the output. For example, if one connected 0 V to both, op-amp inputs and then measured 26 mV(dc) at the output, this would represent, 26 mV of unwanted voltage generated by the circuit and not by the input signal. Since, the user may connect the amplifier circuit for various gain and polarity operations,, however, the manufacturer specifies an input offset voltage for the op-amp. The output offset voltage is then determined by the input offset voltage and the gain of the, amplifier, as connected by the user., The output offset voltage can be shown to be affected by two separate circuit conditions. These are: (1) an input offset voltage, VIO, and (2) an offset current due to, the difference in currents resulting at the plus () and minus () inputs., INPUT OFFSET VOLTAGE, VIO, The manufacturer’s specification sheet provides a value of VIO for the op-amp. To, determine the effect of this input voltage on the output, consider the connection shown, in Fig. 14.23. Using Vo AVi, we can write, R1, Vo AVi A VIO Vo , R1 Rf, Solving for Vo, we get, A, A, Vo VIO VIO , 1 A[R1/(R1 Rf)], A[R1/(R1 Rf)], from which we can write, , , , , , R1 Rf, Vo(offset) VIO , R1, , (14.16), , Equation (14.16) shows how the output offset voltage results from a specified input, offset voltage for a typical amplifier connection of the op-amp., Rf, , R1, , +, , –, A, , Vi, , +, VIO, –, , –, , [(, , Vo, Rf, V, R1 IO, , = 1+, , +, , ) [, , RC, , Figure 14.23 Operation showing, effect of input offset voltage, VIO., , 14.5 OP-AMP Specifications—DC Offset Parameters, , 625
Page 652 :
−, +, , EXAMPLE 14.6, , Calculate the output offset voltage of the circuit in Fig. 14.24. The op-amp spec lists, VIO 1.2 mV., , Figure 14.24 Op-amp connection for Examples 14.6 and 14.7., , Solution, R1 Rf, 2 k 150 k, Eq. (14.16): Vo(offset) VIO (1.2 mV) 91.2 mV, R1, 2 k, , , , , , OUTPUT OFFSET VOLTAGE DUE TO INPUT OFFSET CURRENT, IIO, An output offset voltage will also result due to any difference in dc bias currents at, both inputs. Since the two input transistors are never exactly matched, each will operate at a slightly different current. For a typical op-amp connection, such as that, shown in Fig. 14.25, an output offset voltage can be determined as follows. Replacing the bias currents through the input resistors by the voltage drop that each develops, as shown in Fig. 14.26, we can determine the expression for the resulting output voltage. Using superposition, the output voltage due to input bias current IIB,, denoted by V o, is, Rf, V o I IB RC 1 , R1, , , , , , , while the output voltage due to only I , IB, denoted by V o, is, , Rf, V o I , IB R1 , R1, , , , Figure 14.25 Op-amp connection showing input bias currents., , 626, , Chapter 14, , Operational Amplifiers, , , , Figure 14.26 Redrawn circuit of Fig. 14.25.
Page 653 :
−, +, , for a total output offset voltage of, Rf, Rf, , , , Vo(offset due to I , IB and I IB) I IB RC 1 I IB R1, R1, R1, , , , , , (14.17), , Since the main consideration is the difference between the input bias currents rather, than each value, we define the offset current IIO by, IIO I IB I , IB, Since the compensating resistance RC is usually approximately equal to the value of, R1, using RC R1 in Eq. (14.17) we can write, Vo(offset) I IB(R1 Rf) I , IB Rf, , , , I, IBRf I IB Rf Rf (I IB I IB), , resulting in, Vo(offset due to IIO) IIO Rf, , (14.18), , Calculate the offset voltage for the circuit of Fig. 14.24 for op-amp specification listing IIO 100 nA., , EXAMPLE 14.7, , Solution, Eq. (14.18): Vo IIO Rf (100 nA)(150 k) 15 mV, , TOTAL OFFSET DUE TO VIO AND IIO, Since the op-amp output may have an output offset voltage due to both factors, covered above, the total output offset voltage can be expressed as, Vo(offset) Vo(offset due to VIO) Vo(offset due to IIO), , (14.19), , The absolute magnitude is used to accommodate the fact that the offset polarity may, be either positive or negative., Calculate the total offset voltage for the circuit of Fig. 14.27 for an op-amp with specified values of input offset voltage, VIO 4 mV and input offset current IIO , 150 nA., , EXAMPLE 14.8, , Figure 14.27 Op-amp circuit, for Example 14.8., , 14.5 OP-AMP Specifications—DC Offset Parameters, , 627
Page 655 :
−, , per decade (20 dB/decade) or 6 dB per octave (6 dB/octave). (Refer to Chapter, 11 for introductory coverage of dB and frequency response.), Note that while op-amp specifications list an open-loop voltage gain (AVD), the, user typically connects the op-amp using feedback resistors to reduce the circuit voltage gain to a much smaller value (closed-loop voltage gain, ACL). A number of circuit improvements result from this gain reduction. First, the amplifier voltage gain is, a more stable, precise value set by the external resistors; second, the input impedance, of the circuit is increased over that of the op-amp alone; third, the circuit output impedance is reduced from that of the op-amp alone; and finally, the frequency response, of the circuit is increased over that of the op-amp alone., , +, , Gain–Bandwidth, Because of the internal compensation circuitry included in an op-amp, the voltage, gain drops off as frequency increases. Op-amp specifications provide a description of, the gain versus bandwidth. Figure 14.28 provides a plot of gain versus frequency for, a typical op-amp. At low frequency down to dc operation the gain is that value listed, by the manufacturer’s specification AVD (voltage differential gain) and is typically a, very large value. As the frequency of the input signal increases the open-loop gain, drops off until it finally reaches the value of 1 (unity). The frequency at this gain value, is specified by the manufacturer as the unity-gain bandwidth, B1. While this value is, a frequency (see Fig. 14.28) at which the gain becomes 1, it can be considered a bandwidth, since the frequency band from 0 Hz to the unity-gain frequency is also a bandwidth. One could therefore refer to the point at which the gain reduces to 1 as the, unity-gain frequency ( f1) or unity-gain bandwidth (B1)., , Aυ, AVD, , 0.707AVD, , 1, , 0, fC, , f1, , Frequency, (log scale), , B1, , Figure 14.28 Gain versus frequency plot., , Another frequency of interest is that shown in Fig. 14.28, at which the gain drops, by 3 dB (or to 0.707 the dc gain, AVD), this being the cutoff frequency of the op-amp,, fC. In fact, the unity-gain frequency and cutoff frequency are related by, f1 AVD fC, , (14.22), , Equation (14.22) shows that the unity-gain frequency may also be called the gain–, bandwidth product of the op-amp., 14.6, , OP-AMP Specifications—Frequency Parameters, , 629
Page 656 :
−, +, , EXAMPLE 14.10, , Determine the cutoff frequency of an op-amp having specified values B1 1 MHz, and AVD 200 V/mV., , Solution, Since f1 B1 1 MHz, we can use Eq. (14.22) to calculate, f1, 1 MHz, 1 106, fC 3 5 Hz, AVD, 200 V/mV, 200 10, , Slew Rate, SR, Another parameter reflecting the op-amp’s ability to handling varying signals is slew, rate, defined as, slew rate maximum rate at which amplifier output can change in volts per, microsecond (V/s), Vo, SR , t, , V/s, , with t in s, , (14.23), , The slew rate provides a parameter specifying the maximum rate of change of the, output voltage when driven by a large step-input signal.* If one tried to drive the output at a rate of voltage change greater than the slew rate, the output would not be able, to change fast enough and would not vary over the full range expected, resulting in, signal clipping or distortion. In any case, the output would not be an amplified duplicate of the input signal if the op-amp slew rate is exceeded., , EXAMPLE 14.11, , For an op-amp having a slew rate of SR 2 V/s, what is the maximum closed-loop, voltage gain that can be used when the input signal varies by 0.5 V in 10 s?, , Solution, Since Vo ACLVi, we can use, Vo, Vi, ACL, t, t, from which we get, SR, 2 V/s, V / t, ACL o 40, Vi/ t, Vi/ t, 0.5 V/10 s, Any closed-loop voltage gain of magnitude greater than 40 would drive the output at, a rate greater than the slew rate allows, so the maximum closed-loop gain is 40., , *, , The closed-loop gain is that obtained with the output connected back to the input in some way., , 630, , Chapter 14, , Operational Amplifiers
Page 657 :
−, +, , Maximum Signal Frequency, The maximum frequency that an op-amp may operate at depends on both the bandwidth (BW) and slew rate (SR) parameters of the op-amp. For a sinusoidal signal of, general form, vo K sin(2 f t), the maximum voltage rate of change can be shown to be, signal maximum rate of change 2 f K, , V/s, , To prevent distortion at the output, the rate of change must also be less than the slew, rate, that is,, 2 f K SR, K SR, SR, f , 2 K, , so that, , SR, , K, , Hz, (14.24), rad/s, , Additionally, the maximum frequency, f, in Eq. (14.24), is also limited by the unitygain bandwidth., For the signal and circuit of Fig. 14.29, determine the maximum frequency that may, be used. Op-amp slew rate is SR 0.5 V/s., , EXAMPLE 14.12, , Figure 14.29 Op-amp circuit, for Example 14.12., , Solution, For a gain of magnitude, Rf, 240 k, ACL 24, R1, 10 k, the output voltage provides, K ACLVi 24(0.02 V) 0.48 V, Eq. (14.24):, , SR, 0.5 V/s, 6, 1.1 10 rad/s, K, 0.48 V, , Since the signal’s frequency, 300 103 rad/s, is less than the maximum value, determined above, no output distortion will result., , 14.6, , OP-AMP Specifications—Frequency Parameters, , 631
Page 658 :
−, +, , 14.7 OP-AMP UNIT SPECIFICATIONS, In this section, we discuss how the manufacturer’s specifications are read for a typical op-amp unit. A popular bipolar op-amp IC is the 741 described by the information provided in Fig. 14.30. The op-amp is available in a number of packages, an, 8-pin DIP and a 10-pin flatpack being among the more usual forms., , Figure 14.30 741 op-amp specifications., , 632, , Chapter 14, , Operational Amplifiers
Page 659 :
−, +, , Figure 14.30 Continued., , Absolute Maximum Ratings, The absolute maximum ratings provide information on what largest voltage supplies, may be used, how large the input signal swing may be, and at how much power the, device is capable of operating. Depending on the particular version of 741 used, the, largest supply voltage is a dual supply of 18 V or 22 V. In addition, the IC can, internally dissipate from 310 to 570 mW, depending on the IC package used. Table, 14.1 summarizes some typical values to use in examples and problems., , TABLE 14.1 Absolute Maximum Ratings, Supply voltage, Internal power dissipation, Differential input voltage, Input voltage, , 22 V, 500 mW, 30 V, 15 V, , Determine the current draw from a dual power supply of 12 V if the IC dissipates, 500 mW., 14.7, , OP-AMP Unit Specifications, , EXAMPLE 14.13, , 633
Page 660 :
−, +, , Solution, If we assume that each supply provides half the total power to the IC, then, P VI, 250 mW 12 V(I), so that each supply must provide a current of, 250 mW, I 20.83 mA, 12 V, , Electrical Characteristics, Electrical characteristics include many of the parameters covered earlier in this chapter. The manufacturer provides some combination of typical, minimum, or maximum, values for various parameters as deemed most useful to the user. A summary is provided in Table 14.2., , TABLE 14.2 A741 Electrical Characteristics: VCC 15 V, TA 25°C, Characteristic, , MIN, , VIO Input offset voltage, IIO Input offset current, IIB Input bias current, VICR Common-mode input voltage range, VOM Maximum peak output voltage swing, AVD Large-signal differential voltage amplification, ri Input resistance, ro Output resistance, Ci Input capacitance, CMRR Common-mode rejection ratio, ICC Supply current, PD Total power dissipation, , 12, 12, 20, 0.3, , 70, , TYP, , MAX, , 1, 20, 80, 13, 14, 200, 2, 75, 1.4, 90, 1.7, 50, , 6, 200, 500, , 2.8, 85, , Unit, mV, nA, nA, V, V, V/mV, M, , pF, dB, mA, mW, , VIO Input offset voltage: The input offset voltage is seen to be typically, 1 mV, but can go as high as 6 mV. The output offset voltage is then computed based, on the circuit used. If the worst condition possible is of interest, the maximum value, should be used. Typical values are those more commonly expected when using the, op-amp., IIO Input offset current: The input offset current is listed to be typically, 20 nA, while the largest value expected is 200 nA., IIB Input bias current: The input bias current is typically 80 nA and may be, as large as 500 nA., VICR Common-mode input voltage range: This parameter lists the range that, the input voltage may vary over (using a supply of 15 V), about 12 to 13 V. Inputs larger in amplitude than this value will probably result in output distortion and, should be avoided., VOM Maximum peak output voltage swing: This parameter lists the largest, value the output may vary (using a 15-V supply). Depending on the circuit closed634, , Chapter 14, , Operational Amplifiers
Page 661 :
−, , loop gain, the input signal should be limited to keep the output from varying by an, amount no larger than 12 V, in the worst case, or by 14 V, typically., AVD Large-signal differential voltage amplification: This is the open-loop, voltage gain of the op-amp. While a minimum value of 20 V/mV or 20,000 V/V is, listed, the manufacturer also lists a typical value of 200 V/mV or 200,000 V/V., ri Input resistance: The input resistance of the op-amp when measured under open-loop is typically 2 M but could be as little as 0.3 M or 300 k. In a, closed-loop circuit, this input impedance can be much larger, as discussed previously., ro Output resistance: The op-amp output resistance is listed as typically 75 ., No minimum or maximum value is given by the manufacturer for this op-amp. Again,, in a closed-loop circuit, the output impedance can be lower, depending on the circuit, gain., Ci Input capacitance: For high-frequency considerations, it is helpful to know, that the input to the op-amp has typically 1.4 pF of capacitance, a generally small, value compared even to stray wiring., CMRR Common-mode rejection ratio: The op-amp parameter is seen to be, typically 90 dB but could go as low as 70 dB. Since 90 dB is equivalent to 31622.78,, the op-amp amplifies noise (common inputs) by over 30,000 times less than difference inputs., ICC Supply current: The op-amp draws a total of 2.8 mA, typically from the, dual voltage supply, but the current drawn could be as little as 1.7 mA. This parameter helps the user determine the size of the voltage supply to use. It also can be used, to calculate the power dissipated by the IC (PD 2VCCICC)., PD Total power dissipation: The total power dissipated by the op-amp is typically 50 mW but could go as high as 85 mW. Referring to the previous parameter,, the op-amp will dissipate about 50 mW when drawing about 1.7 mA using a dual, 15-V supply. At smaller supply voltages, the current drawn will be less and the total, power dissipated will also be less., Using the specifications listed in Table 14.2, calculate the typical output offset voltage for the circuit connection of Fig. 14.31., , +, , EXAMPLE 14.14, , Figure 14.31 Op-amp circuit, for Examples 14.14, 14.15, and, 14.17., , Solution, The output offset due to VIO is calculated to be, R1 Rf, 12 k 360 k, Eq. (14.16): Vo(offset) VIO (1 mV) 31 mV, 12 k, R1, , , , , , The output voltage due to IIO is calculated to be, 14.7, , OP-AMP Unit Specifications, , 635
Page 662 :
−, +, , Eq. (14.18): Vo(offset) IIORf 20 nA(360 k) 7.2 mV, Assuming that these two offsets are the same polarity at the output, the total output, offset voltage is then, Vo(offset) 31 mV 7.2 mV 38.2 mV, , EXAMPLE 14.15, , For the typical characteristics of the 741 op-amp (ro 75 , A 200 k), calculate, the following values for the circuit of Fig. 14.31., (a) ACL., (b) Zi., (c) Zo., , Solution, (a) Eq. (14.8):, , Rf, V, 360 k, o 30, Vi, R1, 12 k, , 1, , , , (b) Zi R1 12 k, 75 , ro, (c) Zo , 0.011 , 1, (1 A), 1 (200 k), 30, , , , Operating Characteristics, Another group of values used to describe the operation of the op-amp over varying, signals are provided in Table 14.3., , TABLE 14.3 Operating Characteristics: VCC 15 V, TA 25°C, Parameter, B1 Unity gain bandwidth, tr Rise time, , EXAMPLE 14.16, , MIN, , TYP, , MAX, , 1, 0.3, , Unit, MHz, s, , Calculate the cutoff frequency of an op-amp having characteristics given in Tables, 14.2 and 14.3., , Solution, f1, B1, 1 MHz, Eq. (14.22): fC 50 Hz, AVD, AVD, 20,000, , EXAMPLE 14.17, , Calculate the maximum frequency of the input signal for the circuit in Fig. 14.31,, with an input of Vi 25 mV., , Solution, For a closed-loop gain of ACL 30 and an input of Vi 25 mV, the output gain factor is calculated to be, K ACLVi 30(25 mV) 750 mV 0.750 V, 636, , Chapter 14, , Operational Amplifiers
Page 663 :
−, +, , Using Eq. (14.24), the maximum signal frequency, fmax, is, SR, 0.5 V/s, fmax 106 kHz, 2 (0.750 V), 2 K, , Op-Amp Performance, , Input resistance (Ω), , 4 8 12 16, Supply voltage (+VCC), 10 M, 1M, 100 k, 10 k, 100 1 k 10 k 100 k 1 M, Frequency (Hz), , Power consumption (mW), , 110, 105, 100, 95, 90, 85, , Output resistance (Ω), , Voltage gain (dB), , The manufacturer provides a number of graphical descriptions to describe the performance of the op-amp. Figure 14.32 includes some typical performance curves comparing various characteristics as a function of supply voltage. The open-loop voltage, gain is seen to get larger with a larger supply voltage value. While the previous, tabular information provided information at a particular supply voltage, the performance curve shows how the voltage gain is affected by using a range of supply, voltage values., 100, 80, 60, 40, 20, 0, , 10, 15, 20, Supply voltage (+VCC), , 600, 500, 400, 300, 200, 100, 100 1 k 10 k 100 k 1 M, Frequency (Hz), , Figure 14.32, curves., , Performance, , Using Fig. 14.32, determine the open-loop voltage gain for a supply voltage of, VCC 12 V., , EXAMPLE 14.18, , Solution, From the curve in Fig. 14.32, AVD 104 dB. This is a linear voltage gain of, AVD (dB) 20 log10 AVD, 104 dB 20 log AVD, 104, AVD antilog 158.5, 20, , 103, , Another performance curve in Fig. 14.32 shows how power consumption varies, as a function of supply voltage. As shown, the power consumption increases with, larger values of supply voltage. For example, while the power dissipation is about, 50 mW at VCC 15 V, it drops to about 5 mW with VCC 5 V. Two other curves, show how the input and output resistances are affected by frequency, the input impedance dropping and the output resistance increasing at higher frequency., 14.7, , OP-AMP Unit Specifications, , 637
Page 664 :
−, +, , 14.8 PSPICE WINDOWS, The evaluation version of PSpice has only four op-amp units. These are defined by, the subcircuit made up of various transistors, resistors, capacitors, and so on. These, are models of four of the more common op-amp units and have their unit specifications. One can model an op-amp to provide a more ideal unit—this being helpful, when describing theoretical circuit connections. Lets start by describing an op-amp, model that can be used to analyze circuits., , PSpice Op-Amp Model, An op-amp can be described by a schematic circuit having an input impedance, Ri,, an output impedance, RO, and a voltage gain, Av. Figure 14.33 shows this basic circuit, using the typical values of a 741 op-amp:, Ri 2 M,, , RO 75,, , Av 200,000 200 V/mV, , Figure 14.33 PSpice ideal opamp model., , The values of input and output resistance are provided by resistor components with desired values. The gain of the op-amp is provided using a voltage-controlled voltage, source, schematic device part labeled E. Figure 14.34 shows setting the E device for a, gain of 200,000 (the device parameter GAIN is set to a value of 200,000). The schematic, circuit of Fig. 14.33 thus represents a 741 op-amp with typical specs listed above., , Figure 14.34 Setting gain of, part E., , 638, , Chapter 14, , Operational Amplifiers
Page 665 :
−, +, , Program 14.1—Inverting Op-Amp, An inverting op-amp of the type described in Example 14.3 and shown in Fig. 14.15, is considered first. Using the ideal model of Fig. 14.33, an inverting op-amp circuit, is drawn as in Fig. 14.35. With the dc voltage display turned on, the result after running an analysis shows that for an input of 2 V and a circuit gain of 5., Av RF/R1 500 k/100 k 5, , Figure 14.35 Inverting op-amp using ideal model., , The output is exactly 10 V, VO AvVi 5(2 V) 10 V, The input to the minus terminal is 50.01 V, which is virtually ground or 0 V., A practical inverting op-amp circuit is drawn in Fig. 14.36. Using the same resistor, values as in Fig. 14.35 with a practical op-amp unit, the A741, the resulting output, is 9.96 V, near the ideal value of 10 V. This slight difference from the ideal is due, to the actual gain and input impedance of the A741 op-amp unit. Fig. 14.36 shows, dc voltages because the Enable Bias Voltage Display was set on. Notice the minus, input is 69.26 V for this op-amp circuit—slightly different from that using the opamp model of Fig. 14.33., , Figure 14.36 Practical inverting op-amp circuit., , An output listing from the analysis of Fig. 14.36 is shown in Fig. 14.37. Before, the analysis is done, selecting Analysis Setup, Transfer Function, and then Output, of V(RF:2) and Input Source of Vi will provide the small-signal characteristics in, the output listing. The circuit gain is seen to be, 14.8, , PSpice Windows, , Figure 14.37 PSpice output for, inverting op-amp (edited)., , 639
Page 666 :
−, +, , VO/Vi 5, Input resistance at Vi 1, , 105, , Output resistance at VO 4.95, , 103, , Program 14.2—Noninverting Op-Amp, Fig. 14.38 shows a noninverting op-amp circuit. The bias voltages are displayed on, the figure. The theoretical gain of the amplifier circuit should be, Av (1 RF/R1) 1 500 k/100 k 6, , Figure 14.38 Design Center, schematic for noninverting opamp circuit., , For an input of 2 V, the resulting output will be, VO AvVi 5(2 V) 10 V, The output is noninverted from the input., , Program 14.3—Summing Op-Amp Circuit, A summing op-amp circuit such as that in Example 14.5 is shown in Fig. 14.39. Bias, voltages also are displayed in Fig. 14.39, showing the resulting output at 3 V, as was, , Figure 14.39 Summing amplifier for Program 14.3., , 640, , Chapter 14, , Operational Amplifiers
Page 667 :
−, , calculated in Example 14.5. Notice how well the virtual ground concept works with, the minus input being only 3.791 V., , +, , Program 14.4—Unity-Gain Op-Amp Circuit, Figure 14.40 shows a unity-gain op-amp circuit with bias voltages displayed. For an, input of 2 V, the output is exactly 2 V., , Figure 14.40 Unity-gain amplifier., , Program 14.5—Op-Amp Integrator Circuit, An op-amp integrator circuit is shown in Fig. 14.41. The input is selected as VPULSE,, which is set to be a step input as follows:, , Figure 14.41 Op-amp integrator circuit., , Set ac 0, dc 0, V1 0 V, V2 2 V, TD 0, TR 0, TF 0, PW 10 ms,, and PER 20 ms. This provides a step from 0 to 2 V, with no time delay, rise time, or fall time, having a period of 10 ms and repeating after a period of 20 ms. For this, problem, the voltage rises instantly to 2 V, then stays there for a sufficiently long time, for the output to drop as a ramp voltage from the maximum supply level of 20 V, to the lowest level of 20 V. Theoretically, the output for the circuit of Fig. 14.41 is, vO(t) 1/RC, vO(t) 1/(10 k)(0.01 F), , v (t) dt, i, , 2 dt 10,000 2 dt 20,000t, 14.8, , PSpice Windows, , 641
Page 668 :
−, +, , This is a negative ramp voltage dropping at a rate (slope) of 20,000 V/s. This ramp, voltage will drop from 20 V to 20 V in, 40 V/20,000 2, , 103 2 ms, , Fig. 14.42 shows the input step waveform and the resulting output ramp waveform, obtained using PROBE., , Figure 14.42 Probe waveform for integrator circuit., , Program 14.6—Multistage Op-Amp Circuit, A multistage op-amp circuit is shown in Fig. 14.43. The input to stage 1 of 200 mV, provides an output of 200 mV to stages 2 and 3. Stage 2 is an inverting amplifier with, , Figure 14.43 Multistage op-amp circuit., , 642, , Chapter 14, , Operational Amplifiers
Page 669 :
−, , gain 200 k/20 k 10, with an output from stage 2 of 10(200 mV) , 2 V. State 3 is a non-inverting amplifier with gain of (1 200 k/10 k 21), resulting in an output of 21(200 mV) 4.2 V., , +, , PROBLEMS, , § 14.2 Differential and Common-Mode Operation, 1. Calculate the CMRR (in dB) for the circuit measurements of Vd 1 mV, Vo 120 mV, and, VC 1 mV, Vo 20 V., 2. Determine the output voltage of an op-amp for input voltages of Vi1 200 V and Vi2 140, V. The amplifier has a differential gain of Ad 6000 and the value of CMRR is:, (a) 200., (b) 105., , § 14.4 Practical Op-Amp Circuits, 3. What is the output voltage in the circuit of Fig. 14.44?, , Figure 14.44 Problems 3 and 25, , 4. What is the range of the voltage-gain adjustment in the circuit of Fig. 14.45?, , Figure 14.45 Problem 4, , Problems, , 643
Page 670 :
−, +, , 5. What input voltage results in an output of 2 V in the circuit of Fig. 14.46?, , Figure 14.46, , Problem 5, , 6. What is the range of the output voltage in the circuit of Fig. 14.47 if the input can vary from, 0.1 to 0.5 V?, 7. What output voltage results in the circuit of Fig. 14.48 for an input of V1 0.3 V?, , +, , V1, , 200 kΩ, , Vo, V1, (0.1 to 0.5 V), , 20 kΩ, , –, , –, Vo, , 360 kΩ, 12 kΩ, , +, , Figure 14.48, , Figure 14.47 Problem 6, , Problems 7, 8, and 26, , 8. What input must be applied to the input of Fig. 14.48 to result in an output of 2.4 V?, 9. What range of output voltage is developed in the circuit of Fig. 14.49?, 10. Calculate the output voltage developed by the circuit of Fig. 14.50 for Rf 330 k., 11. Calculate the output voltage of the circuit in Fig. 14.50 for Rf 68 k., V1 = 0.5 V, , +, Vo, Rf, , –, V1 = + 0.2 V, , 200 kΩ, , V2 = – 0.5 V, , 10 kΩ, , V3 = + 0.8 V, 10 kΩ, , 22 kΩ, , +, , 12 kΩ, Vo, , –, , Figure 14.50, , Figure 14.49 Problem 9, , 644, , 33 kΩ, , Chapter 14, , Operational Amplifiers, , Problems 10, 11, and 27
Page 671 :
−, +, , 12. Sketch the output waveform resulting in Fig. 14.51., 13. What output voltage results in the circuit of Fig. 14.52 for V1 0.5 V?, 0.1 µ F, , V1 = +1.5 V, , 200 kΩ, , –, –, Vo, Vo, , +, V1, , Figure 14.51 Problem 12, , +, , Figure 14.52 Problem 13, , 14. Calculate the output voltage for the circuit of Fig. 14.53., , Figure 14.53 Problems 14 and 28, , 15. Calculate the output voltages V2 and V3 in the circuit of Fig. 14.54., , Figure 14.54 Problem 15, , Problems, , 645
Page 672 :
−, +, , 16. Calculate the output voltage, Vo, in the circuit of Fig. 14.55., , Figure 14.55 Problems 16 and 29, , 17. Calculate Vo in the circuit of Fig. 14.56., , Figure 14.56 Problem 17, , § 14.5 Op-Amp Specifications—DC Offset Parameters, *, , 646, , 18. Calculate the total offset voltage for the circuit of Fig. 14.57 for an op-amp with specified values of input offset voltage VIO 6 mV and input offset current IIO 120 nA., Chapter 14, , Operational Amplifiers
Page 673 :
−, +, , Figure 14.57, 23, and 24, , *, , Problems 18, 22,, , 19. Calculate the input bias current at each input of an op-amp having specified values of IIO , 4 nA and IIB 20 nA., , § 14.6 Op-Amp Specifications—Frequency Parameters, 20. Determine the cutoff frequency of an op-amp having specified values B1 800 kHz and AVD, 150 V/mV., *, , 21. For an op-amp having a slew rate of SR 2.4 V/s, what is the maximum closed-loop voltage gain that can be used when the input signal varies by 0.3 V in 10 s?, , *, , 22. For an input of V1 50 mV in the circuit of Fig. 14.57, determine the maximum frequency, that may be used. The op-amp slew rate SR 0.4 V/s., 23. Using the specifications listed in Table 14.2, calculate the typical offset voltage for the circuit, connection of Fig. 14.57., , *, , 24. For the typical characteristics of the 741 op-amp, calculate the following values for the circuit, of Fig. 14.57., (a) ACL., (b) Zi., (c) Zo., , § 14.8 PSpice Windows, *, , 25. Use Schematic Capture to draw a circuit to determine the output voltage in the circuit of Fig., 14.44., , *, , 26. Use Schematic Capture to calculate the output voltage in the circuit of Fig. 14.48 for the input, of Vi 0.5 V., , *, , 27. Use Schematic Capture to calculate the output voltage in the circuit of Fig. 14.50 for Rf , 68 k., , *, , 28. Use Schematic Capture to calculate the output voltage in the circuit of Fig. 14.53., , *, , 29. Use Schematic Capture to calculate the output voltage in the circuit of Fig. 14.55., , *, , 30. Use Schematic Capture to calculate the output voltage in the circuit of Fig. 14.56., , *, , 31. Use Schematic Capture to obtain the output waveform for a 2 V step input to an integrator circuit, as shown in Fig. 14.20, with values of R 40 k and C 0.003 F., *, , Please Note: Asterisks indicate more difficult problems., , Problems, , 647
Page 674 :
−, +, , CHAPTER, , 15, , Op-Amp Applications, 15.1 CONSTANT-GAIN MULTIPLIER, One of the most common op-amp circuits is the inverting constant-gain multiplier,, which provides a precise gain or amplification. Figure 15.1 shows a standard circuit, connection with the resulting gain being given by, Rf, A , R1, , (15.1), , Figure 15.1, amplifier., , EXAMPLE 15.1, , Fixed-gain, , Determine the output voltage for the circuit of Fig. 15.2 with a sinusoidal input of, 2.5 mV., , Figure 15.2 Circuit for, Example 15.1., , 648
Page 675 :
−, +, , Solution, The circuit of Fig. 15.2 uses a 741 op-amp to provide a constant or fixed gain,, calculated from Eq. (15.1) to be, 200 k, Rf, A 100, 2 k, R1, The output voltage is then, Vo AVi 100(2.5 mV) 250 mV 0.25 V, A noninverting constant-gain multiplier is provided by the circuit of Fig. 15.3,, with the gain given by, Rf, A 1 , R1, , (15.2), , Figure 15.3 Noninverting, fixed-gain amplifier., , Calculate the output voltage from the circuit of Fig. 15.4 for an input of 120 V., , EXAMPLE 15.2, , Figure 15.4 Circuit for, Example 15.2., , Solution, The gain of the op-amp circuit is calculated using Eq. (15.2) to be, Rf, 240 k, A 1 1 1 100 101, R1, 2.4 k, The output voltage is then, Vo AVi 101(120 V) 12.12 mV, , 15.1, , Constant-Gain Multiplier, , 649
Page 676 :
−, +, , Multiple-Stage Gains, When a number of stages are connected in series, the overall gain is the product of the, individual stage gains. Figure 15.5 shows a connection of three stages. The first stage, is connected to provide noninverting gain as given by Eq. (15.2). The next two stages, provide an inverting gain given by Eq. (15.1). The overall circuit gain is then noninverting and calculated by, A A1A2A3, where A1 1 Rf /R1, A2 Rf /R2, and A3 Rf /R3., , Figure 15.5, , EXAMPLE 15.3, , Constant-gain connection with multiple stages., , Calculate the output voltage using the circuit of Fig. 15.5 for resistor components of, value Rf 470 k, R1 4.3 k, R2 33 k, and R3 33 k for an input of, 80 V., , Solution, The amplifier gain is calculated to be, , , , , , , , , , Rf, Rf, Rf, A A1A2A3 1 , R1, R2, R3, 470 k, 1 , 4.3 k, , , , 470 k, , 470 k, , , , 33 k , 33 k, , (110.3)(14.2)(14.2) 22.2 103, so that, Vo AVi 22.2 103(80 V) 1.78 V, , EXAMPLE 15.4, , Show the connection of an LM124 quad op-amp as a three-stage amplifier with gains, of 10, 18, and 27. Use a 270-k feedback resistor for all three circuits. What, output voltage will result for an input of 150 V?, , Solution, For the gain of 10:, Rf, A1 1 10, R1, 650, , Chapter 15, , Op-Amp Applications
Page 677 :
−, +, , Rf, 10 1 9, R1, Rf, 270 k, R1 30 k, 9, 9, For the gain of 18:, Rf, A2 18, R2, 270 k, Rf, R2 15 k, 18, 18, For the gain of 27:, Rf, A3 27, R3, Rf, 270 k, R3 10 k, 27, 27, The circuit showing the pin connections and all components used is in Fig. 15.6. For, an input of V1 150 V, the output voltage will be, Vo A1A2A3V1 (10)(18)(27)(150 V) 4860(150 V), 0.729 V, , Figure 15.6, , Circuit for Example 15.4 (using LM124)., , A number of op-amp stages could also be used to provide separate gains, as demonstrated in the next example., , Show the connection of three op-amp stages using an LM348 IC to provide outputs, that are 10, 20, and 50 times larger than the input. Use a feedback resistor of Rf , 500 k in all stages., , EXAMPLE 15.5, , Solution, The resistor component for each stage is calculated to be, 15.1 Constant-Gain Multipier, , 651
Page 678 :
−, , Rf, 500 k, R1 50 k, A2, 10, , +, , Rf, 500 k, R2 25 k, A2, 20, Rf, 500 k, R3 10 k, A3, 50, The resulting circuit is drawn in Fig. 15.7., , Figure 15.7, , Circuit for Example 15.5 (using LM348)., , 15.2 VOLTAGE SUMMING, Another popular use of an op-amp is as a summing amplifier. Figure 15.8 shows the, connection with the output being the sum of the three inputs, each multiplied by a, different gain. The output voltage is, , , , Rf, Rf, Rf, Vo V1 V2 V3, R1, R2, R3, , 652, , Chapter 15, , Op-Amp Applications, , , , (15.3)
Page 679 :
−, +, , Figure 15.8, , Summing amplifier., , Calculate the output voltage for the circuit of Fig. 15.9. The inputs are V1 50 mV, sin(1000t) and V2 10 mV sin(3000t)., , EXAMPLE 15.6, , Figure 15.9 Circuit for, Example 15.6., , Solution, The output voltage is, 330 k, 330 k, Vo V1 V2 (10V1 33V2), 33 k, 10 k, , , , , , [10(50 mV) sin(1000t) 33(10 mV) sin(3000t)], [0.5 sin(1000t) 0.33 sin(3000t)], , Voltage Subtraction, Two signals can be subtracted, one from the other, in a number of ways. Figure 15.10, shows two op-amp stages used to provide subtraction of input signals. The resulting, output is given by, , Figure 15.10, two signals., , 15.2 Voltage Summing, , Circuit to subtract, , 653
Page 680 :
−, +, , , , , , Rf, Rf, Rf, Vo V1 V2, R3, R1, R2, , , , Rf, Rf Rf, Vo V2 V1, R2, R3 R1, , EXAMPLE 15.7, , , , , , (15.4), , Determine the output for the circuit of Fig. 15.10 with components Rf 1 M,, R1 100 k, R2 50 k, and R3 500 k., , Solution, The output voltage is calculated to be, 1 M, 1 M 1 M, Vo V2 V1 (20V2 20V1) 20(V2 V1), 50 k, 500 k 100 k, , , , , , The output is seen to be the difference of V2 and V1 multiplied by a gain factor of, 20., Another connection to provide subtraction of two signals is shown in Fig. 15.11., This connection uses only one op-amp stage to provide subtracting two input signals., Using superposition the output can be shown to be, R3, R2 R4, R, , V1 4 V2, Vo , R1 R3, R2, R2, , Figure 15.11, , EXAMPLE 15.8, , (15.5), , Subtraction circuit., , Determine the output voltage for the circuit of Fig. 15.12., , Figure 15.12 Circuit for, Example 15.8., , 654, , Chapter 15, , Op-Amp Applications
Page 681 :
−, +, , Solution, The resulting output voltage can be expressed as, 100 k 100 k, 100 k, 20 k, Vo V1 V2, 100 k, 100 k, 20 k 20 k, , , , , , , , V1 V2, The resulting output voltage is seen to be the difference of the two input voltages., , 15.3 VOLTAGE BUFFER, A voltage buffer circuit provides a means of isolating an input signal from a load by, using a stage having unity voltage gain, with no phase or polarity inversion, and acting as an ideal circuit with very high input impedance and low output impedance., Figure 15.13 shows an op-amp connected to provide this buffer amplifier operation., The output voltage is determined by, Vo V1, , (15.6), , Figure 15.14 shows how an input signal can be provided to two separate outputs. The, advantage of this connection is that the load connected across one output has no (or, little) effect on the other output. In effect, the outputs are buffered or isolated from, each other., , Figure 15.13 Unity-gain, (buffer) amplifier., , Figure 15.14 Use of buffer, amplifier to provide output, signals., , 15.3, , Voltage Buffer, , 655
Page 682 :
−, +, , EXAMPLE 15.9, , Show the connection of a 741 as a unity-gain circuit., , Solution, The connection is shown in Fig. 15.15., , Figure 15.15 Connection for, Example 15.9., , 15.4 CONTROLLED SOURCES, Operational amplifiers can be used to form various types of controlled sources. An, input voltage can be used to control an output voltage or current, or an input current, can be used to control an output voltage or current. These types of connections are, suitable for use in various instrumentation circuits. A form of each type of controlled, source is provided next., , Voltage-Controlled Voltage Source, An ideal form of a voltage source whose output Vo is controlled by an input voltage V1, is shown in Fig. 15.16. The output voltage is seen to be dependent on the input, voltage (times a scale factor k). This type of circuit can be built using an op-amp as, shown in Fig. 15.17. Two versions of the circuit are shown, one using the inverting, input, the other the noninverting input. For the connection of Fig. 15.17a, the output, voltage is, Rf, Vo V1 kV1, R1, , Figure 15.16 Ideal voltagecontrolled voltage source., , Figure 15.17, , 656, , Chapter 15, , Practical voltage-controlled voltage source circuits., , Op-Amp Applications, , (15.7)
Page 683 :
−, +, , while that of Fig. 15.17b results in, , , , , , Rf, Vo 1 V1 kV1, R1, , (15.8), , Voltage-Controlled Current Source, An ideal form of circuit providing an output current controlled by an input voltage is, that of Fig. 15.18. The output current is dependent on the input voltage. A practical, circuit can be built, as in Fig. 15.19, with the output current through load resistor RL, controlled by the input voltage V1. The current through load resistor RL can be seen, to be, V, Io 1 kV1, R1, , (15.9), , Figure 15.18 Ideal voltagecontrolled current source., , Figure 15.19 Practical voltagecontrolled current source., , Current-Controlled Voltage Source, An ideal form of a voltage source controlled by an input current is shown in Fig., 15.20. The output voltage is dependent on the input current. A practical form of the, circuit is built using an op-amp as shown in Fig. 15.21. The output voltage is seen, to be, Vo I1RL kI1, , (15.10), Figure 15.20 Ideal currentcontrolled voltage source., , Figure 15.21 Practical form of, current-controlled voltage source., , Current-Controlled Current Source, An ideal form of a circuit providing an output current dependent on an input current, is shown in Fig. 15.22. In this type of circuit, an output current is provided dependent on the input current. A practical form of the circuit is shown in Fig. 15.23. The, input current I1 can be shown to result in the output current Io so that, 15.4, , Controlled Sources, , 657
Page 684 :
−, +, , Figure 15.23 Practical form of, current-controlled current source., , Figure 15.22 Ideal currentcontrolled current source., , , , , , I1R1, R, Io I1 I2 I1 , 1 1 I1 kI1, R2, R2, , EXAMPLE 15.10, , (15.11), , (a) For the circuit of Fig. 15.24a, calculate IL., (b) For the circuit of Fig. 15.24b, calculate Vo., , Figure 15.24, , Circuits for Example 15.10., , Solution, (a) For the circuit of Fig. 15.24a,, V, 8V, IL 1 4 mA, R1, 2 k, (b) For the circuit of Fig. 15.24b,, Vo I1R1 (10 mA)(2 k) 20 V, , 15.5 INSTRUMENTATION CIRCUITS, A popular area of op-amp application is in instrumentation circuits such as dc or ac, voltmeters. A few typical circuits will demonstrate how op-amps can be used., 658, , Chapter 15, , Op-Amp Applications
Page 685 :
−, +, , DC Millivoltmeter, Figure 15.25 shows a 741 op-amp used as the basic amplifier in a dc millivoltmeter., The amplifier provides a meter with high input impedance and scale factors dependent only on resistor value and accuracy. Notice that the meter reading represents millivolts of signal at the circuit input. An analysis of the op-amp circuit provides the, circuit transfer function, 100 k, , , V RR , 100 k 10 10 mV, , Figure 15.25, , Io, , Rf, , 1, , 1, , 1, , 1, , 1 mA, , S, , Op-amp dc millivoltmeter., , Thus, an input of 10 mV will result in a current through the meter of 1 mA. If the, input is 5 mV, the current through the meter will be 0.5 mA, which is half-scale, deflection. Changing Rf to 200 k, for example, would result in a circuit scale factor of, 200 k, 1, 1 mA, , VI , 100 k 10 , 5 mV, o, , 1, , showing that the meter now reads 5 mV, full scale. It should be kept in mind that, building such a millivoltmeter requires purchasing an op-amp, a few resistors, diodes, capacitors, and a meter movement., , AC Millivoltmeter, Another example of an instrumentation circuit is the ac millivoltmeter shown in Fig., 15.26. The circuit transfer function is, 100 k, 1, 1 mA, , VI RR1 , 100 k 10 , 10 mV, o, , Rf, , 1, , 1, , S, , which appears the same as the dc millivoltmeter, except that in this case the signal, handled is an ac signal. The meter indication provides a full-scale deflection for an, ac input voltage of 10 mV, while an ac input of 5 mV will result in half-scale deflection with the meter reading interpreted in millivolt units., 15.5 Instrumentation Circuits, , 659
Page 686 :
−, +, , Figure 15.26, , Ac millivoltmeter using op-amp., , Display Driver, Figure 15.27 shows op-amp circuits that can be used to drive a lamp display or LED, display. When the noninverting input to the circuit in Fig. 15.27a goes above the, inverting input, the output at terminal 1 goes to the positive saturation level (near, 5 V in this example) and the lamp is driven on when transistor Q1 conducts. As, shown in the circuit, the output of the op-amp provides 30 mA of current to the base, of transistor Q1, which then drives 600 mA through a suitably selected transistor, 20) capable of handling that amount of current. Figure 15.27b shows an, (with, op-amp circuit that can supply 20 mA to drive an LED display when the noninverting input goes positive compared to the inverting input., , Figure 15.27, , 660, , Chapter 15, , Display driver circuits: (a) lamp driver; (b) LED driver., , Op-Amp Applications
Page 687 :
−, +, , Instrumentation Amplifier, A circuit providing an output based on the difference between two inputs (times a, scale factor) is shown in Fig. 15.28. A potentiometer is provided to permit adjusting, the scale factor of the circuit. While three op-amps are used, a single-quad op-amp IC, is all that is necessary (other than the resistor components). The output voltage can be, shown to be, Vo, 2R, , 1 , V1 V2, RP, so that the output can be obtained from, , , , , , 2R, Vo 1 (V1 V2) k(V1 V2), RP, , (15.12), , +, , V2, , R, , R, , –, , R, , –, RP, , Vo, R, , –, , +, , R, R, , +, , V1, , Figure 15.28, amplifier., , EXAMPLE 15.11, , Calculate the output voltage expression for the circuit of Fig. 15.29., , V2, , +, , Instrumentation, , +10 V, 5 kΩ, , –, , 5 kΩ, −10 V, , 5 kΩ, , –, , +10 V, , 500 Ω, , Vo, 5 kΩ, , –, , +10 V, , +, , 5 kΩ, , −10 V, , 5 kΩ, , V1, , +, , Figure 15.29 Circuit for, Example 15.11., , −10 V, , 15.5 Instrumentation Circuits, , 661
Page 688 :
−, +, , Solution, The output voltage can then be expressed using Eq. (15.12) as, , , , , , , , , , 2R, 2(5000), Vo 1 (V1 V2) 1 (V1 V2), RP, 500, 21(V1 V2), , 15.6 ACTIVE FILTERS, A popular application uses op-amps to build active filter circuits. A filter circuit can, be constructed using passive components: resistors and capacitors. An active filter, additionally uses an amplifier to provide voltage amplification and signal isolation or, buffering., A filter that provides a constant output from dc up to a cutoff frequency fOH and, then passes no signal above that frequency is called an ideal low-pass filter. The ideal, response of a low-pass filter is shown in Fig. 15.30a. A filter that provides or passes, signals above a cutoff frequency fOL is a high-pass filter, as idealized in Fig. 15.30b., When the filter circuit passes signals that are above one ideal cutoff frequency and, below a second cutoff frequency, it is called a bandpass filter, as idealized in Fig., 15.30c., , Figure 15.30, , 662, , Chapter 15, , Ideal filter response: (a) low-pass; (b) high-pass; (c) bandpass., , Op-Amp Applications
Page 689 :
−, +, , Low-Pass Filter, A first-order, low-pass filter using a single resistor and capacitor as in Fig. 15.31a has, a practical slope of 20 dB per decade, as shown in Fig. 15.31b (rather than the ideal, response of Fig. 15.30a). The voltage gain below the cutoff frequency is constant at, Rf, Av 1 , R1, , (15.13), , 1, fOH , 2 R1C1, , (15.14), , at a cutoff frequency of, , Connecting two sections of filter as in Fig. 15.32 results in a second-order low-pass, filter with cutoff at 40 dB per decade—closer to the ideal characteristic of Fig., RF, , RG, , Vo / V1, V+, , –, , −20 dB/decade, , Op-amp, R1, , Output (Vo), , +, , V1, , C1, , V−, , fOH, , (a), , Figure 15.31, , f, , (b), , First-order low-pass active filter., , RG, , RF, Vo / V1, , Op-amp, R1, , R2, , C2, , fOH, , (a), , Figure 15.32, , – 40 dB/decade, , Output (Vo), , +, , V1, , C1, , –20 dB/decade, , Aυ, , –, , Second-order low-pass active filter., , f, , (b), , 663
Page 690 :
−, +, , 15.30a. The circuit voltage gain and cutoff frequency are the same for the secondorder circuit as for the first-order filter circuit, except that the filter response drops at, a faster rate for a second-order filter circuit., Calculate the cutoff frequency of a first-order low-pass filter for R1 1.2 k and, C1 0.02 F., , EXAMPLE 15.12, , Solution, 1, 1, fOH , 6.63 kHz, 2 (1.2 103)(0.02 106), 2 R1C1, , High-Pass Active Filter, First- and second-order high-pass active filters can be built as shown in Fig. 15.33., The amplifier gain is calculated using Eq. (15.13). The amplifier cutoff frequency is, 1, fOL , 2 R1C1, , (15.15), , with a second-order filter R1 R2, and C1 C2 results in the same cutoff frequency, as in Eq. (15.15)., RG, , RF, , RG, , RF, , –, , –, , Op-amp, , Op-amp, , Vo, C1, , C1, , +, , V1, , C2, , +, , V1, , R1, , R1, , R2, , (a), , (b), , Vo / V1, , –20 dB/decade, – 40 dB/decade, , fOL, , f, , (c), , Figure 15.33, , 664, , High-pass filter: (a) first order; (b) second order; (c) response plot., , Vo
Page 691 :
−, +, , Calculate the cutoff frequency of a second-order high-pass filter as in Fig. 15.33b for, R1 5 R2 5 2.1 kV, C1 5 C2 5 0.05 mF, and Ro1 5 10 kV, Rof 5 50 kV., , EXAMPLE 15.13, , Solution, Rof, 50 k, Eq. (15.13): Av 1 1 6, Ro1, 10 k, The cutoff frequency is then, 1, 1, Eq. (15.15): fOL , 1.5 kHz, 3, 2 R1C1, 2 (2.1 10 )(0.05 106), , Bandpass Filter, Figure 15.34 shows a bandpass filter using two stages, the first a high-pass filter and, the second a low-pass filter, the combined operation being the desired bandpass, response., , Figure 15.34, , Bandpass active filter., , 15.6 Active Filters, , 665
Page 692 :
−, +, , EXAMPLE 15.14, , Calculate the cutoff frequencies of the bandpass filter circuit of Fig. 15.34 with, R1 R2 10 k, C1 0.1 F, and C2 0.002 F., , Solution, 1, 1, fOL , 159.15 Hz, 2 R1C1, 2 (10 103)(0.1 106), 1, 1, 7.96 kHz, fOH , 2 R2C2, 2 (10 103)(0.002 106), , 15.7 PSPICE WINDOWS, Many of the practical op-amp applications covered in this chapter can be analyzed, using PSpice. Analysis of various problems will be used to display the resulting dc, bias or, using PROBE, to display resulting waveforms. As always, first use Schematic, drawing to draw the circuit diagram and set the desired analysis, then use Simulation to analyze the circuit. Finally, examine the resulting Output or use PROBE to, view various waveforms., , Program 15.1—Summing Op-Amp, A summing op-amp using a 741 IC is shown in Fig. 15.35. Three dc voltage inputs, are summed, with a resulting output dc voltage determined as follows:, VO [(100 k/20 k)(2 V) (100 k/50 k)(3 V) , (100 k/10 k)(1 V)], [(10 V) (6 V) (10 V)] [20 V 6 V] 14 V, , Figure 15.35, , Summing amplifier using A741 op-amp., , The steps in drawing the circuit and doing the analysis are as follows. Using Get, New Part:, Select uA741., Select R and repeatedly place three input resistors and feedback resistor; set, resistor values and change resistor names, if desired., 666, , Chapter 15, , Op-Amp Applications
Page 693 :
−, +, , Select VDC and place three input voltages and two supply voltages; set voltage, values and change voltage names, if desired., Select GLOBAL (global connector) and use to identify supply voltages and make, connection to op-amp power input terminals (4 and 7), Now that the circuit is drawn and all part names and values set as in Fig. 15.35,, press the Simulation button to have PSpice analyze the circuit. Since no specific, analysis has been chosen, only the dc bias will be carried out., Press the Enable Bias Voltage Display button to see the dc voltages at various, points in the circuit. The bias voltages displayed in Fig. 15.35 shows the output to be, 13.99 V (compared to the calculated value of 14 V above)., , Program 15.2—Op-Amp DC Voltmeter, A dc voltmeter built using a A741 op-amp is provided by the schematic of Fig., 15.36. From the material presented in Section 15.5, the transfer function of the, circuit is, IO/V1 (RF/R1)(1/RS) (1 M/1 M)(1/10 k), , Figure 15.36, meter., , Op-amp dc volt-, , The full-scale setting of this voltmeter (for IO full scale at 1 mA) is then, V1(full scale) (10 k)(1 mA) 10 V, Thus, an input of 10 V will result in a meter current of 1 mA—the full-scale deflection of the meter. Any input less then 10 V will result is a proportionately smaller meter deflection., The steps in drawing the circuit and doing the analysis are as follows. Using Get, New Part:, Select A741., Select R and repeatedly place input resistor, feedback resistor; and meter setting, resistor; set resistor values and change resistor names, if desired., Select VDC and place input voltage and two supply voltages; set voltage values, and change voltage names, if desired., Select GLOBAL (global connector) and use to identify supply voltages and make, connection to op-amp power input terminals (4 and 7), Select IPROBE and use as meter movement., 15.7, , PSpice Windows, , 667
Page 694 :
−, +, , Now that the circuit is drawn and all part names and values set as in Fig. 15.36, press, the Simulation button to have PSpice analyze the circuit. Since no specific analysis, has been chosen, only the dc bias will be carried out., Figure 15.36 shows that an input of 5 V will result in a current of 0.5 mA, with, the meter reading of 0.5 being read as 5 V (since 1 mA full scale will occur for 10, V input)., , Program 15.3—Low-Pass Active Filter, Figure 15.37 shows the schematic of a low-pass active filter. This first-order filter circuit passes frequencies from dc up to the cutoff frequency determined by resistor R1, and capacitor C1 using, fOH 1/(2 R1C1), , Figure 15.37, , Low-pass active filter., , For the circuit of Fig. 15.37, this is, fOH 1/(2 R1C1) 1/(2, , 10 k 0.1 F) 159 Hz, , Figure 15.38 shows the Analysis Setup—choosing an ac sweep of 10 points per, decade from 1 Hz to 10 kHz. After running the analysis, a PROBE output showing, the output voltage, VO, is that shown in Fig. 15.39. The cutoff frequency obtained using PROBE is seen to be fh 159.5 Hz, very close to that calculated above., , Figure 15.38, , 668, , Chapter 15, , Analysis Setup for schematic of Fig. 15.37., , Op-Amp Applications
Page 695 :
−, +, , Figure 15.38, , Figure 15.39, , Continued., , Waveform VO for the circuit in Fig. 15.37., , Program 15.4—High-Pass Active Filter, Figure 15.40 shows the schematic of a high-pass active filter. This first-order filter, circuit passes frequencies above a cutoff frequency determined by resistor R1 and capacitor C1 using, fOL 1/(2 R1C1), , Figure 15.40, , High-pass active filter., , 15.7, , PSpice Windows, , 669
Page 696 :
−, +, , For the circuit of Fig. 15.40, this is, fOH 1/(2 R1C1) 1/(2, , 18 k 0.003 F) 2.95 kHz, , The Analysis Setup is set for an ac sweep of 10 points per decade from 10 Hz to, 100 kHz. After running the analysis, a PROBE output showing the output voltage,, VO, is that shown in Fig. 15.41. The cutoff frequency obtained using probe is seen to, be fL 2.9 kHz, very close to that calculated above., , Figure 15.41 Probe output of, VO for the active high-pass filter, circuit of Fig. 15.40., , Program 15.5—Second-Order High-Pass Active Filter, Figure 15.42 shows the schematic of a second-order high-pass active filter. This, second-order filter circuit passes frequencies above a cutoff frequency determined, by resistor R1 and capacitor C1 using, fOL 1/(2 R1C1), , Figure 15.42 Second-order, high-pass active filter., , For the circuit of Fig. 15.42, this is, fOL 1/(2 R1C1) 1/(2, , 18 k 0.0022 F) 4 kHz, , The Analysis Setup is set for an ac sweep of 20 points per decade from 100 Hz to, 100 kHz, as shown in Fig. 15.43. After running the analysis a PROBE output showing the output voltage (VO) is shown in Fig. 15.44. The cutoff frequency obtained using PROBE is seen to be fL 4 kHz, the same as that calculated above., 670, , Chapter 15, , Op-Amp Applications
Page 697 :
−, +, , Figure 15.43, , Analysis Setup for Fig. 15.42., , Figure 15.44, , Probe plot of VO for second-order high-pass active filter., , 15.7, , PSpice Windows, , 671
Page 698 :
−, +, , Fig. 15.45 shows the PROBE plot of the dB gain versus frequency, showing that over, a decade (from about 200 Hz to about 2 kHz) the gain changes by about 40 dB—as, expected for a second-order filter., , Figure 15.45, active filter., , Probe plot of dB (VO /Vi) for second-order high-pass, , Program 15.6—Bandpass Active Filter, Figure 15.46 shows a bandpass active filter circuit. Using the values of Example 15.14,, the bandpass frequencies are, , Figure 15.46, , fOL 1/(2 R1C1) 1/(2, , 10 k 0.1 F) 159 Hz, , fOH 1/(2 R2C2) 1/(2, , 10 k 0.002 F) 7.96 kHz, , Bandpass active filter., , The sweep is set at 10 points per decade from 10 Hz to 1 MHz. The probe plot of VO, in Fig. 15.47 shows the low cutoff frequency at about 153 Hz and the upper cutoff, frequency at about 8.2 kHz, these values matching those calculated above quite well., 672, , Chapter 15, , Op-Amp Applications
Page 699 :
−, +, , Figure 15.47, , Probe plot of bandpass active filter., , § 15.1 Constant-Gain Multiplier, , PROBLEMS, , 1. Calculate the output voltage for the circuit of Fig. 15.48 for an input of Vi 3.5 mV rms., 2. Calculate the output voltage of the circuit of Fig. 15.49 for input of 150 mV rms., 750 kΩ, +9 V, , 180 kΩ, 36 kΩ, , –, , +12 V, 3.6 kΩ, , –, , 11, , 4, Vo, , 741, , 11, , 10, , 4, , 5, , +, , Vo, , 741, , V1, , +, , 6, , 5, , 10, , −9 V, , 6, , V1, , −12 V, , Figure 15.48, *3., , Problem 1, , Figure 15.49, , Problem 2, , Calculate the output voltage in the circuit of Fig. 15.50., 510 kΩ, , 18 kΩ, , 680 kΩ, , –, , 750 kΩ, , –, , –, 33 kΩ, , 22 kΩ, , Vo, , +, , +, , +, , V1, 20 µV, , Figure 15.50, , Problem 3, , Problems, , 673
Page 700 :
−, +, , *4., , Show the connection of an LM124 quad op-amp as a three-stage amplifier with gains of 15,, 22, and 30. Use a 420-k feedback resistor for all stages. What output voltage results for, an input of V1 80 V?, , 5. Show the connection of two op-amp stages using an LM358 IC to provide outputs that are 15, and 30 times larger than the input. Use a feedback resistor, RF 150 k, in all stages., , § 15.2 Voltage Summing, 6. Calculate the output voltage for the circuit of Fig. 15.51 with inputs of V1 40 mV rms and, V2 20 mV rms., 470 kΩ, 47 kΩ, V1, , +15 V, 4, , –, , V2, , 11, , 12 kΩ, , Vo, , 741, 5, , 10, , +, , 6, −15 V, , Figure 15.51, , Problem 6, , Figure 15.52, , Problem 7, , 7. Determine the output voltage for the circuit of Fig. 15.52., 300 kΩ, , V2 = 2 V, , 150 kΩ, , –, 741, , V1 = 1 V, , 10 kΩ, , Vo, , +, 10 kΩ, , 8. Determine the output voltage for the circuit of Fig. 15.53., , Figure 15.53, , 674, , Chapter 15, , Problem 8, , Op-Amp Applications
Page 701 :
−, +, , § 15.3 Voltage Buffer, 9. Show the connection (including pin information) of an LM124 IC stage connected as a unitygain amplifier., 10. Show the connection (including pin information) of two LM358 stages connected as unity-gain, amplifiers to provide the same output., , § 15.4 Controlled Sources, 11. For the circuit of Fig. 15.54, calculate IL., 12. Calculate Vo for the circuit of Fig. 15.55., , Figure 15.54, , Figure 15.55, , Problem 11, , Problem 12, , § 15.5 Instrumentation Circuits, 13. Calculate the output current Io in the circuit of Fig. 15.56., , +12 V, V1 = 10 mV, , 200 kΩ, , 2, , –, , 7, 6, 741, , 3, , Io, , +, , 4, −12 V, , M, , 1 mA, movement, , 100 kΩ, 10 Ω, , Figure 15.56, , Problem 13, , Problems, , 675
Page 702 :
−, +, , *14., , Calculate Vo in the circuit of Fig. 15.57., , V1 = 3 V, , +, 10 kΩ, , 5 kΩ, , –, , 10 kΩ, , –, 1 kΩ, , Vo, 10 kΩ, , –, , +, , 5 kΩ, 10 kΩ, , V2 = 1 V, , +, , Figure 15.57, , Problem 14, , § 15.6 Active Filters, 15. Calculate the cutoff frequency of a first-order low-pass filter in the circuit of Fig. 15.58., 10 kΩ, , 10 kΩ, , –, Vo, 2.2 kΩ, V1, , +, 0.05 µF, , Figure 15.58, , Problem 15, , 16. Calculate the cutoff frequency of the high-pass filter circuit in Fig. 15.59., , Figure 15.59, , 676, , Problem 16, , Chapter 15, , Op-Amp Applications
Page 703 :
−, , 17. Calculate the lower and upper cutoff frequencies of the bandpass filter circuit in Fig. 15.60., , Figure 15.60, , +, , Problem 17, , § 15.7 PSpice Windows, *18., , Use Design Center to draw the schematic of Fig. 15.61 and determine VO., , Figure 15.61, , *19., , Problem 18, , Use Design Center to calculate I(VSENSE) in the circuit of Fig. 15.62., , Figure 15.62, , Problem 19, , Problems, , 677
Page 704 :
−, +, , *20., , Use Design Center to plot the response of the low-pass filter circuit in Fig. 15.63., , Figure 15.63, *21., , Use Design Center to plot the response of the high-pass filter circuit in Fig. 15.64., , Figure 15.64, *22., , Problem 20, , Problem 21, , Use Design Center to plot the response of the bandpass filter circuit in Fig. 15.65., , Figure 15.65, , Problem 22, , *, , Please Note: Asterisks indicate more difficult problems., , 678, , Chapter 15, , Op-Amp Applications
Page 705 :
PL, CHAPTER, , Power, Amplifiers, , 16, , 16.1 INTRODUCTION—DEFINITIONS, AND AMPLIFIER TYPES, An amplifier receives a signal from some pickup transducer or other input source and, provides a larger version of the signal to some output device or to another amplifier, stage. An input transducer signal is generally small (a few millivolts from a cassette, or CD input, or a few microvolts from an antenna) and needs to be amplified sufficiently to operate an output device (speaker or other power-handling device). In smallsignal amplifiers, the main factors are usually amplification linearity and magnitude, of gain. Since signal voltage and current are small in a small-signal amplifier, the, amount of power-handling capacity and power efficiency are of little concern. A voltage amplifier provides voltage amplification primarily to increase the voltage of the, input signal. Large-signal or power amplifiers, on the other hand, primarily provide, sufficient power to an output load to drive a speaker or other power device, typically, a few watts to tens of watts. In the present chapter, we concentrate on those amplifier circuits used to handle large-voltage signals at moderate to high current levels., The main features of a large-signal amplifier are the circuit’s power efficiency, the, maximum amount of power that the circuit is capable of handling, and the impedance, matching to the output device., One method used to categorize amplifiers is by class. Basically, amplifier classes, represent the amount the output signal varies over one cycle of operation for a full, cycle of input signal. A brief description of amplifier classes is provided next., Class A: The output signal varies for a full 360° of the cycle. Figure 16.1a shows, , Figure 16.1 Amplifier operating, classes., , 679
Page 706 :
PL, that this requires the Q-point to be biased at a level so that at least half the signal, swing of the output may vary up and down without going to a high-enough voltage, to be limited by the supply voltage level or too low to approach the lower supply, level, or 0 V in this description., Class B: A class B circuit provides an output signal varying over one-half the, input signal cycle, or for 180° of signal, as shown in Fig. 16.1b. The dc bias point for, class B is therefore at 0 V, with the output then varying from this bias point for a halfcycle. Obviously, the output is not a faithful reproduction of the input if only one, half-cycle is present. Two class B operations—one to provide output on the positiveoutput half-cycle and another to provide operation on the negative-output half-cycle, are necessary. The combined half-cycles then provide an output for a full 360° of operation. This type of connection is referred to as push-pull operation, which is discussed later in this chapter. Note that class B operation by itself creates a very, distorted output signal since reproduction of the input takes place for only 180° of, the output signal swing., Class AB: An amplifier may be biased at a dc level above the zero base current, level of class B and above one-half the supply voltage level of class A; this bias condition is class AB. Class AB operation still requires a push-pull connection to achieve, a full output cycle, but the dc bias level is usually closer to the zero base current level, for better power efficiency, as described shortly. For class AB operation, the output, signal swing occurs between 180° and 360° and is neither class A nor class B operation., Class C: The output of a class C amplifier is biased for operation at less than, 180° of the cycle and will operate only with a tuned (resonant) circuit, which provides a full cycle of operation for the tuned or resonant frequency. This operating, class is therefore used in special areas of tuned circuits, such as radio or communications., Class D: This operating class is a form of amplifier operation using pulse (digital) signals, which are on for a short interval and off for a longer interval. Using digital techniques makes it possible to obtain a signal that varies over the full cycle (using sample-and-hold circuitry) to recreate the output from many pieces of input signal., The major advantage of class D operation is that the amplifier is on (using power), only for short intervals and the overall efficiency can practically be very high, as described next., , Amplifier Efficiency, The power efficiency of an amplifier, defined as the ratio of power output to power, input, improves (gets higher) going from class A to class D. In general terms, we see, that a class A amplifier, with dc bias at one-half the supply voltage level, uses a good, amount of power to maintain bias, even with no input signal applied. This results in, very poor efficiency, especially with small input signals, when very little ac power is, delivered to the load. In fact, the maximum efficiency of a class A circuit, occurring, for the largest output voltage and current swing, is only 25% with a direct or seriesfed load connection and 50% with a transformer connection to the load. Class B operation, with no dc bias power for no input signal, can be shown to provide a maximum efficiency that reaches 78.5%. Class D operation can achieve power efficiency, over 90% and provides the most efficient operation of all the operating classes. Since, class AB falls between class A and class B in bias, it also falls between their efficiency ratings—between 25% (or 50%) and 78.5%. Table 16.1 summarizes the operation of the various amplifier classes. This table provides a relative comparison of, the output cycle operation and power efficiency for the various class types. In class, B operation, a push-pull connection is obtained using either a transformer coupling, or by using complementary (or quasi-complementary) operation with npn and pnp, transistors to provide operation on opposite polarity cycles. While transformer oper680, , Chapter 16, , Power Amplifiers
Page 707 :
PL, TABLE 16.1 Comparison of Amplifier Classes, A, , Class, B, , AB, , Operating cycle, , 360°, , 180° to 360°, , 180°, , Power efficiency, , 25% to 50%, , Between 25%, (50%) and 78.5%, , 78.5%, , C*, Less than 180°, , D, Pulse operation, Typically over 90%, , *Class C is usually not used for delivering large amounts of power, thus the efficiency is not given here., , ation can provide opposite cycle signals, the transformer itself is quite large in many, applications. A transformerless circuit using complementary transistors provides the, same operation in a much smaller package. Circuits and examples are provided later, in this chapter., , 16.2 SERIES-FED CLASS A AMPLIFIER, The simple fixed-bias circuit connection shown in Fig. 16.2 can be used to discuss, the main features of a class A series-fed amplifier. The only differences between this, circuit and the small-signal version considered previously is that the signals handled, by the large-signal circuit are in the range of volts and the transistor used is a power, transistor that is capable of operating in the range of a few to tens of watts. As will, be shown in this section, this circuit is not the best to use as a large-signal amplifier, because of its poor power efficiency. The beta of a power transistor is generally less, than 100, the overall amplifier circuit using power transistors that are capable of handling large power or current while not providing much voltage gain., , Figure 16.2 Series-fed class A, large-signal amplifier., , DC Bias Operation, The dc bias set by VCC and RB fixes the dc base-bias current at, VCC 0.7 V, IB , RB, , (16.1), , with the collector current then being, IC IB, , (16.2), , with the collector–emitter voltage then, VCE VCC ICRC, , (16.3), 16.2 Series-Fed Class A Amplifier, , 681
Page 708 :
PL, To appreciate the importance of the dc bias on the operation of the power amplifier,, consider the collector characteristic shown in Fig. 16.3. An ac load line is drawn using the values of VCC and RC. The intersection of the dc bias value of IB with the dc, load line then determines the operating point (Q-point) for the circuit. The quiescentpoint values are those calculated using Eqs. (16.1) through (16.3). If the dc bias collector current is set at one-half the possible signal swing (between 0 and VCC/RC),, the largest collector current swing will be possible. Additionally, if the quiescent, collector–emitter voltage is set at one-half the supply voltage, the largest voltage swing, will be possible. With the Q-point set at this optimum bias point, the power considerations for the circuit of Fig. 16.2 are determined as described below., , Figure 16.3 Transistor characteristic showing load line and Qpoint., , AC Operation, When an input ac signal is applied to the amplifier of Fig. 16.2, the output will vary, from its dc bias operating voltage and current. A small input signal, as shown in Fig., 16.4, will cause the base current to vary above and below the dc bias point, which, will then cause the collector current (output) to vary from the dc bias point set as well, , Figure 16.4 Amplifier input and output signal variation., , 682, , Chapter 16, , Power Amplifiers
Page 709 :
PL, as the collector–emitter voltage to vary around its dc bias value. As the input signal, is made larger, the output will vary further around the established dc bias point until, either the current or the voltage reaches a limiting condition. For the current this limiting condition is either zero current at the low end or VCC/RC at the high end of its, swing. For the collector–emitter voltage, the limit is either 0 V or the supply voltage, VCC., , Power Considerations, The power into an amplifier is provided by the supply. With no input signal, the dc, current drawn is the collector bias current, ICQ. The power then drawn from the, supply is, Pi(dc) VCCICQ, , (16.4), , Even with an ac signal applied, the average current drawn from the supply remains, the same, so that Eq. (16.4) represents the input power supplied to the class A seriesfed amplifier., OUTPUT POWER, The output voltage and current varying around the bias point provide ac power to, the load. This ac power is delivered to the load, RC, in the circuit of Fig. 16.2. The, ac signal, Vi, causes the base current to vary around the dc bias current and the collector current around its quiescent level, ICQ. As shown in Fig. 16.4, the ac input signal results in ac current and ac voltage signals. The larger the input signal, the larger, the output swing, up to the maximum set by the circuit. The ac power delivered to, the load (RC) can be expressed in a number of ways., Using rms signals: The ac power delivered to the load (RC) may be expressed using, Po(ac) VCE (rms)IC (rms), , (16.5a), , Po(ac) I C2 (rms)RC, , (16.5b), , V C2 (rms), , Po(ac) , RC, , (16.5c), , Using peak signals: The ac power delivered to the load may be expressed using, VCE (p)IC (p), Po(ac) , , 2, , (16.6a), , I C2 (p), Po(ac) , 2RC, , (16.6b), , V C2 E (p), Po(ac) , 2RC, , (16.6c), , Using peak-to-peak signals:, pressed using, , The ac power delivered to the load may be ex-, , VCE (p-p)IC (p-p), Po(ac) , 8, , (16.7a), , 16.2 Series-Fed Class A Amplifier, , 683
Page 710 :
PL, , I C2 (p-p), Po(ac) , RC, 8, , (16.7b), , V C2 E (p-p), Po(ac) , 8RC, , (16.7c), , Efficiency, The efficiency of an amplifier represents the amount of ac power delivered (transferred) from the dc source. The efficiency of the amplifier is calculated using, Po(ac), %, 100%, Pi(dc), , (16.8), , MAXIMUM EFFICIENCY, For the class A series-fed amplifier, the maximum efficiency can be determined, using the maximum voltage and current swings. For the voltage swing it is, maximum VCE (p-p) VCC, For the current swing it is, V C, maximum IC (p-p) C, RC, Using the maximum voltage swing in Eq. (16.7a) yields, VCC (VCC /RC), maximum Po(ac) , 8, V C2 C, , 8RC, The maximum power input can be calculated using the dc bias current set to one-half, the maximum value:, VCC/RC, , maximum Pi (dc) VCC (maximum IC) VCC , 2, V 2C, C, 2RC, We can then use Eq. (16.8) to calculate the maximum efficiency:, maximum Po(ac), maximum % , 100%, maximum Pi(dc), VC2 C/8RC, 100%, , VC2 C/2RC, 25%, The maximum efficiency of a class A series-fed amplifier is thus seen to be 25%., Since this maximum efficiency will occur only for ideal conditions of both voltage, swing and current swing, most series-fed circuits will provide efficiencies of much, less than 25%., Calculate the input power, output power, and efficiency of the amplifier circuit in, 684, , Chapter 16, , Power Amplifiers
Page 711 :
PL, EXAMPLE 16.1, , Fig. 16.5 for an input voltage that results in a base current of 10 mA peak., IC (mA), IC =, , VCC, RC, , =, , 20 V, = 1000, 20 Ω, 900, , 40, , 800, , 30, dc load line, , 700, 600, , VCC = 20 V, IC, , 20, , 500, , IBQ, , Q, , Operating point, , 400, IC, , RB, 1 kΩ, Ci, , RC = 20 Ω, , 300, , 10, , 200, , β = 25, Vi, , IB = 0 mA, , 100, 5, , 10, VCE, , (a), , Figure 16.5, , 15, , 20, , 25, , VCE (V), , VCE = VCC, , Q, , (b), , Operation of a series-fed circuit for Example 16.1., , Solution, Using Eqs. (16.1) through (16.3), the Q-point can be determined to be, VCC 0.7 V, 20 V 0.7 V, IBQ 19.3 mA, RB, 1 k, ICQ IB 25(19.3 mA) 482.5 mA 0.48 A, VCEQ VCC ICRC 20 V (0.48 )(20 ) 10.4 V, This bias point is marked on the transistor collector characteristic of Fig. 16.5b. The, ac variation of the output signal can be obtained graphically using the dc load line, drawn on Fig. 16.5b by connecting VCE VCC 20 V with IC VCC /RC , 1000 mA 1 A, as shown. When the input ac base current increases from its dc bias, level, the collector current rises by, IC (p) IB(p) 25(10 mA peak) 250 mA peak, Using Eq. (16.6b) yields, I2C (p), (250 103 A)2, Po(ac) , RC (20 ) 0.625 W, 2, 2, Using Eq. (16.4) results in, Pi(dc) VCCICQ (20 V)(0.48 A) 9.6 W, The amplifier’s power efficiency can then be calculated using Eq. (16.8):, Po(ac), 0.625 W, %, 100% 100% 6.5%, Pi(dc), 9.6 W, , 16.2 Series-Fed Class A Amplifier, , 685
Page 712 :
PL, 16.3 TRANSFORMER-COUPLED CLASS A, AMPLIFIER, A form of class A amplifier having maximum efficiency of 50% uses a transformer, to couple the output signal to the load as shown in Fig. 16.6. This is a simple circuit, form to use in presenting a few basic concepts. More practical circuit versions are, covered later. Since the circuit uses a transformer to step voltage or current, a review, of voltage and current step-up and step-down is presented next., , Figure 16.6, , Transformer-coupled audio power amplifier., , Transformer Action, A transformer can increase or decrease voltage or current levels according to the turns, ratio, as explained below. In addition, the impedance connected to one side of a transformer can be made to appear either larger or smaller (step up or step down) at the, other side of the transformer, depending on the square of the transformer winding, turns ratio. The following discussion assumes ideal (100%) power transfer from primary to secondary, that is, no power losses are considered., VOLTAGE TRANSFORMATION, As shown in Fig. 16.7a, the transformer can step up or step down a voltage applied to one side directly as the ratio of the turns (or number of windings) on each, side. The voltage transformation is given by, V, N, 2 2, V1, N1, , (16.9), , Equation (16.9) shows that if the number of turns of wire on the secondary side is, larger than on the primary, the voltage at the secondary side is larger than the voltage at the primary side., CURRENT TRANSFORMATION, The current in the secondary winding is inversely proportional to the number of, turns in the windings. The current transformation is given by, I, N, 2 1, I1, N2, 686, , Chapter 16, , Power Amplifiers, , (16.10)
Page 713 :
PL, N1 : N2, , V1, , V2, , Primary, , N2, , N1, V2, V1, , =, , I2, , I1, , N2, , I2, , N1, , I1, , Secondary, , Primary, , =, , N1, N2, , Secondary, , (a), , (b), , N1, , N2, , R2 = RL, , R1 = RL', , RL' = a2 RL =, , ( NN ) R, 1 2, , L, , 2, , Primary, , Figure 16.7 Transformer operation:, (a) voltage transformation; (b) current, transformation; (c) impedance, transformation., , Secondary, (c), , This relationship is shown in Fig. 16.7b. If the number of turns of wire on the secondary is greater than that on the primary, the secondary current will be less than the, current in the primary., IMPEDANCE TRANSFORMATION, Since the voltage and current can be changed by a transformer, an impedance, “seen” from either side (primary or secondary) can also be changed. As shown in Fig., 16.7c, an impedance RL is connected across the transformer secondary. This impedance is changed by the transformer when viewed at the primary side (RL). This can, be shown as follows:, , , , RL, R2, V /I, V2 I1, V2 I1, N N, N, , , , 22 , 2 2 2, RL, R1, V1/I1, I2 V1, V1 I2, N1 N1, N1, , 2, , If we define a N1/N2, where a is the turns ratio of the transformer, the above equation becomes, , , , R1, N, RL, , , 1, R2, N2, RL, , 2, , a2, , (16.11), , We can express the load resistance reflected to the primary side as:, R1 a2R2, , or, , R L a2RL, , (16.12), , where RL is the reflected impedance. As shown in Eq. (16.12), the reflected impedance is related directly to the square of the turns ratio. If the number of turns of the, secondary is smaller than that of the primary, the impedance seen looking into the, primary is larger than that of the secondary by the square of the turns ratio., Calculate the effective resistance seen looking into the primary of a 151 transformer, connected to an 8- load., , EXAMPLE 16.2, , Solution, Eq. (16.12):, , R L a2RL (15)2(8 ) 1800 1.8 k, , 16.3, , Transformer-Coupled Class A Amplifier, , 687
Page 714 :
PL, EXAMPLE 16.3, , What transformer turns ratio is required to match a 16- speaker load so that the effective load resistance seen at the primary is 10 k?, , Solution, Eq. (16.11):, , N, N1, , 2, , 2, , RL, 10 k, , 625, RL, 16 , , N, 1 625 251, N2, , Operation of Amplifier Stage, DC LOAD LINE, The transformer (dc) winding resistance determines the dc load line for the circuit of Fig. 16.6. Typically, this dc resistance is small (ideally 0 ) and, as shown in, Fig. 16.8, a 0- dc load line is a straight vertical line. A practical transformer winding resistance would be a few ohms, but only the ideal case will be considered in this, discussion. There is no dc voltage drop across the 0- dc load resistance, and the, load line is drawn straight vertically from the voltage point, VCEQ VCC., , Figure 16.8, , Load lines for class A transformer-coupled amplifier., , QUIESCENT OPERATING POINT, The operating point in the characteristic curve of Fig. 16.8 can be obtained graphically at the point of intersection of the dc load line and the base current set by the, circuit. The collector quiescent current can then be obtained from the operating point., In class A operation, keep in mind that the dc bias point sets the conditions for the, 688, , Chapter 16, , Power Amplifiers
Page 715 :
PL, maximum undistorted signal swing for both collector current and collector–emitter, voltage. If the input signal produces a voltage swing less than the maximum possible, the efficiency of the circuit at that time will be less than 25%. The dc bias point, is therefore important in setting the operation of a class A series-fed amplifier., AC LOAD LINE, To carry out ac analysis, it is necessary to calculate the ac load resistance “seen”, looking into the primary side of the transformer, then draw the ac load line on the, collector characteristic. The reflected load resistance (R L) is calculated using Eq., (16.12) using the value of the load connected across the secondary (RL) and the turns, ratio of the transformer. The graphical analysis technique then proceeds as follows., Draw the ac load line so that it passes through the operating point and has a slope, equal to 1/R L (the reflected load resistance), the load line slope being the negative, reciprocal of the ac load resistance. Notice that the ac load line shows that the output signal swing can exceed the value of VCC. In fact, the voltage developed across, the transformer primary can be quite large. It is therefore necessary after obtaining, the ac load line to check that the possible voltage swing does not exceed transistor, maximum ratings., SIGNAL SWING AND OUTPUT AC POWER, Figure 16.9 shows the voltage and current signal swings from the circuit of Fig., 16.6. From the signal variations shown in Fig. 16.9, the values of the peak-to-peak, signal swings are, VCE (p-p) VCEmax VCEmin, IC (p-p) ICmax ICmin, The ac power developed across the transformer primary can then be calculated using, (VCEmax VCEmin)(ICmax ICmin), Po(ac) , 8, , (16.13), , The ac power calculated is that developed across the primary of the transformer. Assuming an ideal transformer (a highly efficient transformer has an efficiency of well, over 90%), the power delivered by the secondary to the load is approximately that, calculated using Eq. (16.13). The output ac power can also be determined using the, voltage delivered to the load., IC (A), , ICp-p = (ICmax − ICmin ), , VCE (V), , VCEp-p = (VCEmax − VCEmin ), , VCEmax, , ICmax, , VCEQ, , ICQ, , VCEmin, , ICmin, , 0, , 0, , t, , (b), , (a), , Figure 16.9, , t, , Graphical operation of transformer-coupled class A amplifier., , 16.3, , Transformer-Coupled Class A Amplifier, , 689
Page 716 :
PL, For the ideal transformer, the voltage delivered to the load can be calculated using Eq. (16.9):, N2, VL V2 V, 1, N1, The power across the load can then be expressed as, V L2(rms), PL , , RL, and equals the power calculated using Eq. (16.5c)., Using Eq. (16.10) to calculate the load current yields, N1, IL I2 I, C, N2, with the output ac power then calculated using, PL I L2(rms)RL, , EXAMPLE 16.4, , Calculate the ac power delivered to the 8- speaker for the circuit of Fig. 16.10. The, circuit component values result in a dc base current of 6 mA, and the input signal (Vi), results in a peak base current swing of 4 mA., , Figure 16.10 Transformercoupled class A amplifier for, Example 16.4., , Solution, The dc load line is drawn vertically (see Fig. 16.11) from the voltage point:, VCEQ VCC 10 V, For IB 6 mA, the operating point on Fig. 16.11 is, VCEQ 10 V, , and, , ICQ 140 mA, , The effective ac resistance seen at the primary is, , , , N 2, RL 1 RL (3)2(8) 72 , N2, The ac load line can then be drawn of slope 1/72 going through the indicated operating point. To help draw the load line, consider the following procedure. For a current swing of, 690, , Chapter 16, , Power Amplifiers
Page 717 :
PL, IC (mA), , dc load line, 14 mA, , IC (mA), 14 mA, , 400, , 400, , 350, , 350, , 12 mA, , 300, , 300, , 10 mA, , ICmax = 255 mA, , 250, 8 mA, , 200, , 5, , 10, , 15, , 20, , 8 mA, Operating point, 6 mA, , 150, , 4 mA, , 100, , IB = 2 mA, , 50, 0, , ICQ, , 4 mA, , 100, , A, , 250, ∆ IC 200, , 6 mA, , 150, , 12 mA, ac load line (R'L = 72 Ω), 10 mA, , 25, , ICmin = 25 mA, , 0, , VCE (V), , IB = 2 mA, , 50, 5, , 10, , VCEmin = 1.7 V, (a), , 15, , 20, , 25, , VCE (V), , VCEmax = 18.3 V, (b), , Figure 16.11 Transformer-coupled class A transistor characteristic for Examples, 16.4 and 16.5: (a) device characteristic; (b) dc and ac load lines., , mark a point (A):, ICEQ, , V E, 10 V, IC C, 139 mA, RL, 72 , IC 140 mA, , 139 mA 279 mA along the y-axis, , Connect point A through the Q-point to obtain the ac load line. For the given base, current swing of 4 mA peak, the maximum and minimum collector current and, collector–emitter voltage obtained from Fig. 16.11 are, VCEmin 1.7 V, , ICmin 25 mA, , VCEmax 18.3 V, , ICmax 255 mA, , The ac power delivered to the load can then be calculated using Eq. (16.13):, (VCEmax VCEmin)(ICmax ICmin), Po (ac) , 8, (18.3 V 1.7 V)(255 mA 25 mA), 0.477 W, 8, , Efficiency, So far we have considered calculating the ac power delivered to the load. We next, consider the input power from the battery, power losses in the amplifier, and the overall power efficiency of the transformer-coupled class A amplifier., The input (dc) power obtained from the supply is calculated from the supply dc, voltage and the average power drawn from the supply:, Pi(dc) VCCICQ, , (16.14), , For the transformer-coupled amplifier, the power dissipated by the transformer is small, (due to the small dc resistance of a coil) and will be ignored in the present calculations. Thus the only power loss considered here is that dissipated by the power tran16.3, , Transformer-Coupled Class A Amplifier, , 691
Page 718 :
PL, sistor and calculated using, PQ Pi (dc) Po(ac), , (16.15), , where PQ is the power dissipated as heat. While the equation is simple, it is nevertheless significant when operating a class A amplifier. The amount of power dissipated by the transistor is the difference between that drawn from the dc supply (set, by the bias point) and the amount delivered to the ac load. When the input signal is, very small, with very little ac power delivered to the load, the maximum power is dissipated by the transistor. When the input signal is larger and power delivered to the, load is larger, less power is dissipated by the transistor. In other words, the transistor, of a class A amplifier has to work hardest (dissipate the most power) when the load, is disconnected from the amplifier, and the transistor dissipates least power when the, load is drawing maximum power from the circuit., , EXAMPLE 16.5, , For the circuit of Fig. 16.10 and results of Example 16.4, calculate the dc input power,, power dissipated by the transistor, and efficiency of the circuit for the input signal of, Example 16.4., , Solution, Eq. (16.14): Pi (dc) VCCICQ (10 V)(140 mA) 1.4 W, Eq. (16.15): PQ Pi (dc) Po (ac) 1.4 W 0.477 W 0.92 W, The efficiency of the amplifier is then, Po(ac), 0.477 W, % 100% 100% 34.1%, Pi(dc), 1.4 W, , MAXIMUM THEORETICAL EFFICIENCY, For a class A transformer-coupled amplifier, the maximum theoretical efficiency, goes up to 50%. Based on the signals obtained using the amplifier, the efficiency can, be expressed as, VCEmax VCEmin 2, % 50 , %, VCEmax VCEmin, , , , , , (16.16), , The larger the value of VCEmax and the smaller the value of VCEmin, the closer the efficiency approaches the theoretical limit of 50%., , EXAMPLE 16.6, , Calculate the efficiency of a transformer-coupled class A amplifier for a supply of, 12 V and outputs of:, (a) V(p) 12 V., (b) V(p) 6 V., (c) V(p) 2 V., , Solution, Since VCEQ VCC 12 V, the maximum and minimum of the voltage swing are, (a) VCEmax VCEQ V(p) 12 V 12 V 24 V, VCEmin VCEQ V(p) 12 V 12 V 0 V, resulting in, , 692, , Chapter 16, , Power Amplifiers
Page 719 :
PL, , 24 V 0 V, % 50 % 50%, 24 V 0 V, , , , , , 2, , (b) VCEmax VCEQ V(p) 12 V 6 V 18 V, VCEmin VCEQ V(p) 12 V 6 V 6 V, resulting in, 18 V 6 V 2, % 50 % 12.5%, 18 V 6 V, , , , , , (c) VCEmax VCEQ V(p) 12 V 2 V 14 V, VCEmin VCEQ V(p) 12 V 2 V 10 V, resulting in, 14 V 10 V 2, % 50 % 1.39%, 14 V 10 V, , , , , , Notice how dramatically the amplifier efficiency drops from a maximum of 50% for, V(p) VCC to slightly over 1% for V(p) 2 V., , 16.4 CLASS B AMPLIFIER OPERATION, Class B operation is provided when the dc bias leaves the transistor biased just off,, the transistor turning on when the ac signal is applied. This is essentially no bias, and, the transistor conducts current for only one-half of the signal cycle. To obtain output, for the full cycle of signal, it is necessary to use two transistors and have each conduct on opposite half-cycles, the combined operation providing a full cycle of output, signal. Since one part of the circuit pushes the signal high during one half-cycle and, the other part pulls the signal low during the other half-cycle, the circuit is referred, to as a push-pull circuit. Figure 16.12 shows a diagram for push-pull operation. An, ac input signal is applied to the push-pull circuit, with each half operating on alternate half-cycles, the load then receiving a signal for the full ac cycle. The power transistors used in the push-pull circuit are capable of delivering the desired power to the, load, and the class B operation of these transistors provides greater efficiency than, was possible using a single transistor in class A operation., , Figure 16.12 Block, representation of push-pull, operation., , Input (DC) Power, The power supplied to the load by an amplifier is drawn from the power supply (or, power supplies; see Fig. 16.13) that provides the input or dc power. The amount of, this input power can be calculated using, Pi(dc) VCCIdc, , (16.17), 16.4 Class B Amplifier Operation, , 693
Page 720 :
PL, , Figure 16.13 Connection of push-pull amplifier to load: (a) using two voltage, supplies; (b) using one voltage supply., , where Idc is the average or dc current drawn from the power supplies. In class B operation, the current drawn from a single power supply has the form of a full-wave, rectified signal, while that drawn from two power supplies has the form of a halfwave rectified signal from each supply. In either case, the value of the average current drawn can be expressed as, 2, Idc I(p), , (16.18), , where I(p) is the peak value of the output current waveform. Using Eq. (16.18) in the, power input equation (Eq. 16.17) results in, , , , , , 2, Pi(dc) VCC I(p), , (16.19), , Output (AC) Power, The power delivered to the load (usually referred to as a resistance, RL) can be calculated using any one of a number of equations. If one is using an rms meter to measure the voltage across the load, the output power can be calculated as, V L2(rms), , Po(ac) , R, , (16.20), , L, , If one is using an oscilloscope, the peak, or peak-to-peak, output voltage measured, can be used:, V L2(p-p), V L2(p), , (16.21), Po(ac) , 8RL, 2RL, The larger the rms or peak output voltage, the larger the power delivered to the load., , Efficiency, The efficiency of the class B amplifier can be calculated using the basic equation:, Po(ac), % 100%, Pi(dc), 694, , Chapter 16, , Power Amplifiers
Page 721 :
PL, Using Eqs. (16.19) and (16.21) in the efficiency equation above results in, Po(ac), V L2(p)/2RL, VL(p), % 100% 100% 100%, Pi(dc), VCC[(2/ )I(p)], 4 V CC, , (16.22), , (using I(p) VL(p)/RL). Equation (16.22) shows that the larger the peak voltage, the, higher the circuit efficiency, up to a maximum value when VL(p) VCC, this maximum efficiency then being, maximum efficiency 4 100% 78.5%, , Power Dissipated by Output Transistors, The power dissipated (as heat) by the output power transistors is the difference between the input power delivered by the supplies and the output power delivered to the, load., P2Q Pi(dc) Po(ac), , (16.23), , where P2Q is the power dissipated by the two output power transistors. The dissipated, power handled by each transistor is then, P2Q, (16.24), PQ , 2, For a class B amplifier providing a 20-V peak signal to a 16- load (speaker) and a, power supply of VCC 30 V, determine the input power, output power, and circuit, efficiency., , EXAMPLE 16.7, , Solution, A 20-V peak signal across a 16- load provides a peak load current of, VL(p), 20 V, IL(p) 1.25 A, RL, 16 , The dc value of the current drawn from the power supply is then, 2, 2, Idc IL(p) (1.25 A) 0.796 A, and the input power delivered by the supply voltage is, Pi(dc) VCCIdc (30 V)(0.796 A) 23.9 W, The output power delivered to the load is, 2, , V L(p), (20 V)2, Po(ac) 12.5 W, 2RL, 2(16 ), for a resulting efficiency of, Po(ac), 12.5 W, 100% 100% 52.3%, %, Pi(dc), 23.9 W, , 16.4 Class B Amplifier Operation, , 695
Page 722 :
PL, Maximum Power Considerations, For class B operation, the maximum output power is delivered to the load when, VL(p) VCC:, V2, maximum Po(ac) CC, , 2RL, , (16.25), , The corresponding peak ac current I(p) is then, V C, I(p) C, RL, so that the maximum value of average current from the power supply is, 2, 2VCC, maximum Idc I(p) , RL, Using this current to calculate the maximum value of input power results in, 2VCC, 2V C2 C, maximum Pi (dc) VCC (maximum Idc) VCC , RL, RL, , , , , , (16.26), , The maximum circuit efficiency for class B operation is then, 2, Po(ac), /2RL, V CC, maximum % 100% , 100%, VCC[(2/ )(VCC/RL)], Pi(dc), , 100% 78.54%, 4, , (16.27), , When the input signal results in less than the maximum output signal swing, the circuit efficiency is less than 78.5%., For class B operation, the maximum power dissipated by the output transistors, does not occur at the maximum power input or output condition. The maximum power, dissipated by the two output transistors occurs when the output voltage across the, load is, VL(p) 0.636VCC, , V , 2, , CC, , for a maximum transistor power dissipation of, 2, 2VCC, maximum P2Q 2, RL, , EXAMPLE 16.8, , For a class B amplifier using a supply of VCC 30 V and driving a load of 16 , determine the maximum input power, output power, and transistor dissipation., , Solution, The maximum output power is, V2, (30 V)2, 28.125 W, maximum Po(ac) CC, 2RL, 2(16 ), The maximum input power drawn from the voltage supply is, 696, , (16.28), , Chapter 16, , Power Amplifiers
Page 723 :
PL, , 2V2CC, 2(30 V)2, maximum Pi(dc) , 35.81 W, RL, (16 ), The circuit efficiency is then, Po(ac), 28.125 W, 100% 100% 78.54%, maximum % , Pi(dc), 35.81 W, as expected. The maximum power dissipated by each transistor is, 2, maximum P2Q, 2V CC, 2(30 V)2, 0.5 , maximum PQ 0.5 2, 2 5.7 W, 2, RL, 16 , , , , , , , , , , Under maximum conditions a pair of transistors, each handling 5.7 W at most, can, deliver 28.125 W to a 16- load while drawing 35.81 W from the supply., The maximum efficiency of a class B amplifier can also be expressed as follows:, V L2(p), Po(ac) , 2RL, 2VL(p), Pi(dc) VCC Idc VCC , RL, 2, Po(ac), V L (p)/2RL, % 100 % 100%, VCC[(2/ )(VL(p)/RL)], Pi(dc), , , , so that, , , , VL(p), 78.54%, VCC, , (16.29), , Calculate the efficiency of a class B amplifier for a supply voltage of VCC 24 V, with peak output voltages of:, (a) VL(p) 22 V., (b) VL(p) 6 V., , EXAMPLE 16.9, , Solution, Using Eq. (16.29) gives, VL(p), 22 V, (a) % 78.54 % 78.54 72%, VCC, 24 V, 6V, (b) % 78.54 % 19.6%, 24 V, , , , , , , , , , Notice that a voltage near the maximum [22 V in part (a)] results in an efficiency near, the maximum, while a small voltage swing [6 V in part (b)] still provides an efficiency near 20%. Similar power supply and signal swings would have resulted in, much poorer efficiency in a class A amplifier., , 16.5 CLASS B AMPLIFIER CIRCUITS, A number of circuit arrangements for obtaining class B operation are possible. We, will consider the advantages and disadvantages of a number of the more popular circuits in this section. The input signals to the amplifier could be a single signal, the, circuit then providing two different output stages, each operating for one-half the cy16.5, , Class B Amplifier Circuits, , 697
Page 724 :
PL, cle. If the input is in the form of two opposite polarity signals, two similar stages, could be used, each operating on the alternate cycle because of the input signal. One, means of obtaining polarity or phase inversion is using a transformer, the transformercoupled amplifier having been very popular for a long time. Opposite polarity inputs, can easily be obtained using an op-amp having two opposite outputs or using a few, op-amp stages to obtain two opposite polarity signals. An opposite polarity operation, can also be achieved using a single input and complementary transistors (npn and, pnp, or nMOS and pMOS)., Figure 16.14 shows different ways to obtain phase-inverted signals from a single, input signal. Figure 16.14a shows a center-tapped transformer to provide opposite, phase signals. If the transformer is exactly center-tapped, the two signals are exactly, , V, , Push-pull, signals, , V, , (a), VCC, , RC, R1, C2, , Push-pull, input signals, , Vi, C1, R2, RE, , C3, , (b), , Vi, , Amplifier, EF, To push-pull, circuit, , EF, , Figure 16.14, circuits., , 698, , Phase-splitter, (c), , Chapter 16, , Power Amplifiers
Page 725 :
PL, opposite in phase and of the same magnitude. The circuit of Fig. 16.14b uses a BJT, stage with in-phase output from the emitter and opposite phase output from the collector. If the gain is made nearly 1 for each output, the same magnitude results. Probably most common would be using op-amp stages, one to provide an inverting gain, of unity and the other a noninverting gain of unity, to provide two outputs of the same, magnitude but of opposite phase., , Transformer-Coupled Push–Pull Circuits, The circuit of Fig. 16.15 uses a center-tapped input transformer to produce opposite, polarity signals to the two transistor inputs and an output transformer to drive the load, in a push-pull mode of operation described next., During the first half-cycle of operation, transistor Q1 is driven into conduction, whereas transistor Q2 is driven off. The current I1 through the transformer results in, the first half-cycle of signal to the load. During the second half-cycle of the input signal, Q2 conducts whereas Q1 stays off, the current I2 through the transformer resulting in the second half-cycle to the load. The overall signal developed across the load, then varies over the full cycle of signal operation., , I1, Q1, , +VCC, , IL, N1, , R1, , Vi, , R2, , +VCC, , N2, N1, , Biasing network, , RL, , Q2, I2, , Phase-splitting, input transformer, , Push-pull circuit, connection, , Push-pull output, transformer, , Load, , Figure 16.15, , Push-pull circuit., , Complementary-Symmetry Circuits, Using complementary transistors (npn and pnp) it is possible to obtain a full cycle, output across a load using half-cycles of operation from each transistor, as shown in, Fig. 16.16a. While a single input signal is applied to the base of both transistors, the, transistors, being of opposite type, will conduct on opposite half-cycles of the input., The npn transistor will be biased into conduction by the positive half-cycle of signal,, with a resulting half-cycle of signal across the load as shown in Fig. 16.16b. During, the negative half-cycle of signal, the pnp transistor is biased into conduction when, the input goes negative, as shown in Fig. 16.16c., During a complete cycle of the input, a complete cycle of output signal is developed across the load. One disadvantage of the circuit is the need for two separate voltage supplies. Another, less obvious disadvantage with the complementary circuit is, shown in the resulting crossover distortion in the output signal (see Fig. 16.16d)., Crossover distortion refers to the fact that during the signal crossover from positive, to negative (or vice versa) there is some nonlinearity in the output signal. This results, from the fact that the circuit does not provide exact switching of one transistor off, and the other on at the zero-voltage condition. Both transistors may be partially off, 16.5, , Class B Amplifier Circuits, , 699
Page 726 :
PL, , Figure 16.16, , Complementary-symmetry push-pull circuit., , so that the output voltage does not follow the input around the zero-voltage condition. Biasing the transistors in class AB improves this operation by biasing both transistors to be on for more than half a cycle., A more practical version of a push-pull circuit using complementary transistors, is shown in Fig. 16.17. Note that the load is driven as the output of an emitterfollower so that the load resistance of the load is matched by the low output resistance of the driving source. The circuit uses complementary Darlington-connected, transistors to provide higher output current and lower output resistance., 700, , Chapter 16, , Power Amplifiers
Page 727 :
PL, , Figure 16.17 Complementarysymmetry push-pull circuit using, Darlington transistors., , Quasi-Complementary Push–Pull Amplifier, In practical power amplifier circuits, it is preferable to use npn transistors for both, high-current-output devices. Since the push-pull connection requires complementary, devices, a pnp high-power transistor must be used. A practical means of obtaining, complementary operation while using the same, matched npn transistors for the output is provided by a quasi-complementary circuit, as shown in Fig. 16.18. The push-, , Figure 16.18 Quasi-complementary, push-pull transformerless power, amplifier., , 16.5, , Class B Amplifier Circuits, , 701
Page 728 :
PL, pull operation is achieved by using complementary transistors (Q1 and Q2) before the, matched npn output transistors (Q3 and Q4). Notice that transistors Q1 and Q3 form, a Darlington connection that provides output from a low-impedance emitter-follower., The connection of transistors Q2 and Q4 forms a feedback pair, which similarly provides a low-impedance drive to the load. Resistor R2 can be adjusted to minimize, crossover distortion by adjusting the dc bias condition. The single input signal applied to the push-pull stage then results in a full cycle output to the load. The quasicomplementary push-pull amplifier is presently the most popular form of power, amplifier., , EXAMPLE 16.10, , For the circuit of Fig. 16.19, calculate the input power, output power, and power, handled by each output transistor and the circuit efficiency for an input of 12 V rms., , Figure 16.19 Class B power, amplifier for Examples 16.10, thru 16.12., , Solution, The peak input voltage is, Vi(p) 2 Vi (rms) 2 (12 V) 16.97 V, , 17 V, , Since the resulting voltage across the load is ideally the same as the input signal (the, amplifier has, ideally, a voltage gain of unity),, VL(p) 17 V, and the output power developed across the load is, (17 V)2, V L2(p), Po(ac) 36.125 W, 2RL, 2(4 ), The peak load current is, V (p), 17 V, IL(p) L 4.25 A, RL, 4, from which the dc current from the supplies is calculated to be, 2, 2(4.25 A), Idc IL(p) 2.71 A, 702, , Chapter 16, , Power Amplifiers
Page 729 :
PL, so that the power supplied to the circuit is, Pi(dc) VCCIdc (25 V)(2.71 A) 67.75 W, The power dissipated by each output transistor is, 67.75 W 36.125 W, PQ, Pi Po, PQ 2, , 15.8 W, 2, 2, 2, The circuit efficiency (for the input of 12 V, rms) is then, P, 36.125 W, % o 100% 100% 53.3%, Pi, 67.75 W, , For the circuit of Fig. 16.19, calculate the maximum input power, maximum output, power, input voltage for maximum power operation, and the power dissipated by the, output transistors at this voltage., , EXAMPLE 16.11, , Solution, The maximum input power is, 2V C2 C, 2(25 V)2, 99.47 W, maximum Pi (dc) , RL, 4, The maximum output power is, V2, (25 V)2, maximum Po(ac) CC, 78.125 W, 2RL, 2(4 ), [Note that the maximum efficiency is achieved:], P, 78.125 W, % o 100% 100% 78.54%, Pi, 99.47 W, To achieve maximum power operation the output voltage must be, VL(p) VCC 25 V, and the power dissipated by the output transistors is then, P2Q Pi Po 99.47 W 78.125 W 21.3 W, For the circuit of Fig. 16.19, determine the maximum power dissipated by the output, transistors and the input voltage at which this occurs., , EXAMPLE 16.12, , Solution, The maximum power dissipated by both output transistors is, 2, 2(25 V)2, 2V CC, maximum P2Q 2, , 31.66 W, 24 , RL, , This maximum dissipation occurs at, VL 0.636VL(p) 0.636(25 V) 15.9 V, (Notice that at VL 15.9 V the circuit required the output transistors to dissipate, 31.66 W, while at VL 25 V they only had to dissipate 21.3 W.), , 16.5, , Class B Amplifier Circuits, , 703
Page 730 :
PL, 16.6 AMPLIFIER DISTORTION, A pure sinusoidal signal has a single frequency at which the voltage varies positive, and negative by equal amounts. Any signal varying over less than the full 360° cycle, is considered to have distortion. An ideal amplifier is capable of amplifying a pure, sinusoidal signal to provide a larger version, the resulting waveform being a pure, single-frequency sinusoidal signal. When distortion occurs the output will not be an, exact duplicate (except for magnitude) of the input signal., Distortion can occur because the device characteristic is not linear, in which case, nonlinear or amplitude distortion occurs. This can occur with all classes of amplifier, operation. Distortion can also occur because the circuit elements and devices respond, to the input signal differently at various frequencies, this being frequency distortion., One technique for describing distorted but period waveforms uses Fourier analysis, a method that describes any periodic waveform in terms of its fundamental frequency component and frequency components at integer multiples—these components are called harmonic components or harmonics. For example, a signal that is, originally 1000 Hz could result, after distortion, in a frequency component at 1000, Hz (1 kHz) and harmonic components at 2 kHz (2 1 kHz), 3 kHz (3 1 kHz),, 4 kHz (4 1 kHz), and so on. The original frequency of 1 kHz is called the fundamental frequency; those at integer multiples are the harmonics. The 2-kHz component is therefore called a second harmonic, that at 3 kHz is the third harmonic, and, so on. The fundamental frequency is not considered a harmonic. Fourier analysis does, not allow for fractional harmonic frequencies—only integer multiples of the fundamental., , Harmonic Distortion, A signal is considered to have harmonic distortion when there are harmonic frequency, components (not just the fundamental component). If the fundamental frequency has, an amplitude, A1, and the nth frequency component has an amplitude, An, a harmonic, distortion can be defined as, An, 100%, % nth harmonic distortion % Dn , A1, , (16.30), , The fundamental component is typically larger than any harmonic component., , EXAMPLE 16.13, , Calculate the harmonic distortion components for an output signal having fundamental, amplitude of 2.5 V, second harmonic amplitude of 0.25 V, third harmonic amplitude, of 0.1 V, and fourth harmonic amplitude of 0.05 V., , Solution, Using Eq. (16.30) yields, A2, 0.25 V, % D2 , 100% 100% 10%, 2.5 V, A1, 0.1 V, A3, 100% 100% 4%, % D3 , A1, 2.5 V, 0.05 V, A4, 100% 100% 2%, % D4 , A1, 2.5 V, , 704, , Chapter 16, , Power Amplifiers
Page 731 :
PL, TOTAL HARMONIC DISTORTION, When an output signal has a number of individual harmonic distortion components, the signal can be seen to have a total harmonic distortion based on the individual elements as combined by the relationship of the following equation:, , 2, D 2, D42 100%, % THD D, 2 , 3 , , (16.31), , where THD is total harmonic distortion., Calculate the total harmonic distortion for the amplitude components given in Example 16.13., , EXAMPLE 16.14, , Solution, Using the computed values of D2 0.10, D3 0.04, and D4 0.02 in Eq. (16.31),, , 2, D 2, D 24 100%, % THD D, 2 , 3 , .1, 0, )2(0.0, 4, )2(0.0, 2, )2 100% 0.1095 100%, (0, 10.95%, , An instrument such as a spectrum analyzer would allow measurement of the harmonics present in the signal by providing a display of the fundamental component of, a signal and a number of its harmonics on a display screen. Similarly, a wave analyzer instrument allows more precise measurement of the harmonic components of a, distorted signal by filtering out each of these components and providing a reading of, these components. In any case, the technique of considering any distorted signal as, containing a fundamental component and harmonic components is practical and useful. For a signal occurring in class AB or class B, the distortion may be mainly even, harmonics, of which the second harmonic component is the largest. Thus, although, the distorted signal theoretically contains all harmonic components from the second, harmonic up, the most important in terms of the amount of distortion in the classes, presented above is the second harmonic., SECOND HARMONIC DISTORTION, Figure 16.20 shows a waveform to use for obtaining second harmonic distortion., A collector current waveform is shown with the quiescent, minimum, and maximum, signal levels, and the time at which they occur is marked on the waveform. The sig-, , Figure 16.20 Waveform for, obtaining second harmonic, distortion., , 16.6, , Amplifier Distortion, , 705
Page 733 :
PL, Solution, Using Eq. (16.34), we get, 1(22 V, 1 V) 12 V, 2, , 22 V 1 V, (a) D2 , 100% 2.38%, (20 V 4 V) 12 V, , 20 V 4 V, 100% 0%, (b) D2 , 1, 2, , (no distortion), , Power of Signal Having Distortion, When distortion does occur, the output power calculated for the undistorted signal is, no longer correct. When distortion is present, the output power delivered to the load, resistor RC due to the fundamental component of the distorted signal is, I 21RC, , P1 , 2, , (16.35), , The total power due to all the harmonic components of the distorted signal can then, be calculated using, P (I 12, , I 22, , I 23, , RC, ) , 2, , (16.36), , The total power can also be expressed in terms of the total harmonic distortion,, P (1, , D 22, , D 23, , RC, ) I 12 , (1, 2, , THD2)P1, , (16.37), , For harmonic distortion reading of D2 0.1, D3 0.02, and D4 0.01, with I1 , 4 A and RC 8 , calculate the total harmonic distortion, fundamental power component, and total power., , EXAMPLE 16.16, , Solution, The total harmonic distortion is, THD D, 22, D32, D24 (0, .1, , )2(0.0, 2, )2(0.0, 1, )2, , 0.1, , The fundamental power, using Eq. (16.35), is, I 12RC, (4 A)2(8 ), P1 64 W, 2, 2, The total power calculated using Eq. (16.37) is then, P (1, , THD2)P1 [1, , (0.1)2]64 (1.01)64 64.64 W, , (Note that the total power is due mainly to the fundamental component even with, 10% second harmonic distortion.), , Graphical Description of Harmonic Components, of Distorted Signal, A distorted waveform such as that which occurs in class B operation can be represented using Fourier analysis as a fundamental with harmonic components. Figure, 16.21a shows a positive half-cycle such as the type that would result in one side of a, 16.6, , Amplifier Distortion, , 707
Page 734 :
PL, , Figure 16.21 Graphical representation of a distorted signal through the use of, harmonic components., , class B amplifier. Using Fourier analysis techniques, the fundamental component of, the distorted signal can be obtained, as shown in Fig. 16.21b. Similarly, the second, and third harmonic components can be obtained and are shown in Fig. 16.21c and d,, respectively. Using the Fourier technique, the distorted waveform can be made by, adding the fundamental and harmonic components, as shown in Fig. 16.21e. In general, any periodic distorted waveform can be represented by adding a fundamental, component and all harmonic components, each of varying amplitude and at various, phase angles., , 16.7 POWER TRANSISTOR HEAT SINKING, While integrated circuits are used for small-signal and low-power applications, most, high-power applications still require individual power transistors. Improvements in, production techniques have provided higher power ratings in small-sized packaging, cases, have increased the maximum transistor breakdown voltage, and have provided, faster-switching power transistors., 708, , Chapter 16, , Power Amplifiers
Page 735 :
PL, The maximum power handled by a particular device and the temperature of the, transistor junctions are related since the power dissipated by the device causes an increase in temperature at the junction of the device. Obviously, a 100-W transistor will, provide more power capability than a 10-W transistor. On the other hand, proper heatsinking techniques will allow operation of a device at about one-half its maximum, power rating., We should note that of the two types of bipolar transistors—germanium and silicon—silicon transistors provide greater maximum temperature ratings. Typically, the, maximum junction temperature of these types of power transistors is, Silicon: 150–200°C, Germanium: 100–110°C, For many applications the average power dissipated may be approximated by, PD VCEIC, , (16.38), , This power dissipation, however, is allowed only up to a maximum temperature. Above, this temperature, the device power dissipation capacity must be reduced (or derated), so that at higher case temperatures the power-handling capacity is reduced, down to, 0 W at the device maximum case temperature., The greater the power handled by the transistor, the higher the case temperature., Actually, the limiting factor in power handling by a particular transistor is the temperature of the device’s collector junction. Power transistors are mounted in large, metal cases to provide a large area from which the heat generated by the device may, radiate (be transferred). Even so, operating a transistor directly into air (mounting it, on a plastic board, for example) severely limits the device power rating. If, instead, (as is usual practice), the device is mounted on some form of heat sink, its powerhandling capacity can approach the rated maximum value more closely. A few heat, sinks are shown in Fig. 16.22. When the heat sink is used, the heat produced by the, transistor dissipating power has a larger area from which to radiate (transfer) the heat, into the air, thereby holding the case temperature to a much lower value than would, result without the heat sink. Even with an infinite heat sink (which, of course, is not, available), for which the case temperature is held at the ambient (air) temperature, the, junction will be heated above the case temperature and a maximum power rating must, be considered., Since even a good heat sink cannot hold the transistor case temperature at ambient (which, by the way, could be more than 25°C if the transistor circuit is in a confined area where other devices are also radiating a good amount of heat), it is necessary to derate the amount of maximum power allowed for a particular transistor as a, function of increased case temperature., Figure 16.23 shows a typical power derating curve for a silicon transistor. The, curve shows that the manufacturer will specify an upper temperature point (not nec-, , Figure 16.22, heat sinks., , Typical power, , Figure 16.23 Typical power, derating curve for silicon, transistors., , 16.7 Power Transistor Heat Sinking, , 709
Page 736 :
PL, essarily 25°C), after which a linear derating takes place. For silicon, the maximum, power that should be handled by the device does not reduce to 0 W until the case, temperature is 200°C., It is not necessary to provide a derating curve since the same information could, be given simply as a listed derating factor on the device specification sheet. Stated, mathematically, we have, PD(temp1) PD(temp0) (Temp1 Temp0)(derating factor), , (16.39), , where the value of Temp0 is the temperature at which derating should begin, the value, of Temp1 is the particular temperature of interest (above the value Temp0), PD(temp0), and PD(temp1) are the maximum power dissipations at the temperatures specified, and, the derating factor is the value given by the manufacturer in units of watts (or milliwatts) per degree of temperature., , EXAMPLE 16.17, , Determine what maximum dissipation will be allowed for an 80-W silicon transistor, (rated at 25°C) if derating is required above 25°C by a derating factor of 0.5 W/°C, at a case temperature of 125°C., , Solution, PD(125°C) PD(25°C) (125°C 25°C)(0.5 W/°C), 80 W 100°C(0.5 W/°C) 30 W, It is interesting to note what power rating results from using a power transistor, without a heat sink. For example, a silicon transistor rated at 100 W at (or below), 100°C is rated only 4 W at (or below) 25°C, the free-air temperature. Thus, operated, without a heat sink, the device can handle a maximum of only 4 W at the room temperature of 25°C. Using a heat sink large enough to hold the case temperature to, 100°C at 100 W allows operating at the maximum power rating., , Thermal Analogy of Power Transistor, Selection of a suitable heat sink requires a considerable amount of detail that is not, appropriate to our present basic considerations of the power transistor. However, more, detail about the thermal characteristics of the transistor and its relation to the power, dissipation of the transistor may help provide a clearer understanding of power as limited by temperature. The following discussion should prove useful., A picture of how the junction temperature (TJ), case temperature (TC), and, ambient (air) temperature (TA) are related by the device heat-handling capacity—, a temperature coefficient usually called thermal resistance—is presented in the, thermal-electric analogy shown in Fig. 16.24., In providing a thermal-electrical analogy, the term thermal resistance is used, to describe heat effects by an electrical term. The terms in Fig. 16.24 are defined as, follows:, JA total thermal resistance (junction to ambient), , JC transistor thermal resistance (junction to case), CS insulator thermal resistance (case to heat sink), SA heat-sink thermal resistance (heat sink to ambient), Using the electrical analogy for thermal resistances, we can write, , JA JC, 710, , Chapter 16, , Power Amplifiers, , CS, , SA, , (16.40)
Page 737 :
PL, , Figure 16.24, , Thermal-to-electrical analogy., , The analogy can also be used in applying Kirchhoff’s law to obtain, TJ PDJA, , TA, , (16.41), , The last relation shows that the junction temperature “floats” on the ambient temperature and that the higher the ambient temperature, the lower the allowed value of, device power dissipation., The thermal factor provides information about how much temperature drop (or, rise) results for a given amount of power dissipation. For example, the value of JC, is usually about 0.5°C/W. This means that for a power dissipation of 50 W, the difference in temperature between case temperature (as measured by a thermocouple), and the inside junction temperature is only, TJ TC JCPD (0.5°C/W)(50 W) 25°C, Thus, if the heat sink can hold the case at, say, 50°C, the junction is then only at, 75°C. This is a relatively small temperature difference, especially at lower power-dissipation levels., The value of thermal resistance from junction to free air (using no heat sink) is,, typically,, , JA 40°C/W, , (into free air), , For this thermal resistance, only 1 W of power dissipation results in a junction temperature 40°C greater than the ambient., A heat sink can now be seen to provide a low thermal resistance between case, and air—much less than the 40°C/W value of the transistor case alone. Using a heat, sink having, , SA 2°C/W, and with an insulating thermal resistance (from case to heat sink) of, , CS 0.8°C/W, and finally, for the transistor,, , CJ 0.5°C/W, we can obtain, , JA SA, , CS, , 2.0°C/W, , CJ, 0.8°C/W, , 0.5°C/W 3.3°C/W, 16.7 Power Transistor Heat Sinking, , 711
Page 738 :
PL, So with a heat sink, the thermal resistance between air and the junction is only, 3.3°C/W, compared to 40°C/W for the transistor operating directly into free air. Using the value of JA above for a transistor operated at, say, 2 W, we calculate, TJ TA JAPD (3.3°C/W)(2 W) 6.6°C, In other words, the use of a heat sink in this example provides only a 6.6°C increase, in junction temperature as compared to an 80°C rise without a heat sink., , EXAMPLE 16.18, , A silicon power transistor is operated with a heat sink (SA 1.5°C/W). The transistor, rated at 150 W (25°C), has JC 0.5°C/W, and the mounting insulation has, CS 0.6°C/W. What maximum power can be dissipated if the ambient temperature, is 40°C and TJmax 200°C?, , Solution, TJ TA, 200°C 40°C, PD , JC CS SA, 0.5°C/W 0.6°C/W 1.5°C/W, , 61.5 W, , 16.8 CLASS C AND CLASS D AMPLIFIERS, Although class A, class AB, and class B amplifiers are most used as power amplifiers, class D amplifiers are popular because of their very high efficiency. Class C amplifiers, while not used as audio amplifiers, do find use in tuned circuits as used in, communications., , Class C Amplifier, A class C amplifier, as that shown in Fig. 16.25, is biased to operate for less than, 180° of the input signal cycle. The tuned circuit in the output, however, will provide, a full cycle of output signal for the fundamental or resonant frequency of the tuned, circuit (L and C tank circuit) of the output. This type of operation is therefore limited to use at one fixed frequency, as occurs in a communications circuit, for example. Operation of a class C circuit is not intended primarily for large-signal or power, amplifiers., , Figure 16.25, circuit., , 712, , Chapter 16, , Power Amplifiers, , Class C amplifier
Page 739 :
PL, Class D Amplifier, A class D amplifier is designed to operate with digital or pulse-type signals. An efficiency of over 90% is achieved using this type of circuit, making it quite desirable in, power amplifiers. It is necessary, however, to convert any input signal into a pulsetype waveform before using it to drive a large power load and to convert the signal, back to a sinusoidal-type signal to recover the original signal. Figure 16.26 shows, how a sinusoidal signal may be converted into a pulse-type signal using some form, of sawtooth or chopping waveform to be applied with the input into a comparatortype op-amp circuit so that a representative pulse-type signal is produced. While the, letter D is used to describe the next type of bias operation after class C, the D could, also be considered to stand for “Digital,” since that is the nature of the signals provided to the class D amplifier., , Figure 16.26 Chopping of, sinusoidal waveform to produce, digital waveform., , Figure 16.27 shows a block diagram of the unit needed to amplify the class D signal and then convert back to the sinusoidal-type signal using a low-pass filter. Since, the amplifier’s transistor devices used to provide the output are basically either off or, on, they provide current only when they are turned on, with little power loss due to, , Figure 16.27 Block diagram of, class D amplifier., , 16.8 Class C and Class D Amplifiers, , 713
Page 740 :
PL, their low on-voltage. Since most of the power applied to the amplifier is transferred, to the load, the efficiency of the circuit is typically very high. Power MOSFET devices have been quite popular as the driver devices for the class D amplifier., , 16.9 PSPICE WINDOWS, Program 16.1—Series-Fed Class A Amplifier, Using Design Center, the circuit of a series-fed class A amplifier is drawn as shown, in Fig. 16.28. Figure 16.29 shows some of the analysis output. Edit the transistor, model for values of only BF 90 and IS 2E-15. This keeps the transistor model, more ideal so that PSpice calculations better match those below., The dc bias of the collector voltage is shown to be, Vc(dc) 12.47 V, , Figure 16.28, amplifier., , Series-fed class A, , Figure 16.29, , Analysis output for the circuit of Fig. 16.28., , With transistor beta set to 90, the ac gain is calculated as follows:, IE Ic 95 mA (from analysis output of PSpice), Re 26 mV/95 mA 0.27 , For a gain of, AV Rc/re 100/0.27 370, The output voltage is then, Vo AvVi (370) 10 mV 3.7 V(peak), The output waveform obtained using probe is shown in Fig. 16.30., 714, , Chapter 16, , Power Amplifiers
Page 741 :
PL, , Figure 16.30 Probe output for, the circuit of Fig. 16.28., , For a peak-to-peak output of, Vo(p-p) 15.6 V 8.75 V 6.85 V, the peak output is, Vo(p) 6.85 V/2 3.4 V, which compares well with that calculated above., From the circuit output analysis, the input power is, Pi VCCIC (22 V) (95 mA) 2.09 W, From the probe ac data, the output power is, Po(ac) Vo(p-p)2/[8 RL] (6.85)2/[8 100] 58 mW, The efficiency is then, % Po/Pi 100% (58 mW/2.09 W) 100% 2.8%, A larger input signal would increase the ac power delivered to the load and increase, the efficiency (the maximum being 25%)., , Program 16.2—Quasi-Complementary Push-Pull Amplifier, Figure 16.31shows a quasi-complementary push-pull class B power amplifier. For the, input of Vi 20 V(p), the output waveform obtained using probe is shown in Fig. 16.32., , Figure 16.31 Quasi-complementary, class B power amplifier., , 16.9, , PSpice Windows, , 715
Page 742 :
PL, , Figure 16.32, , Probe output of the circuit in Fig. 16.31., , The resulting ac output voltage is seen to be, Vo(p-p) 33.7 V, so that, Po V o2(p-p)/(8 RL) (33.7 V)2/(8 8 ) 17.7 W, The input power for that amplitude signal is, Pi VCC Idc VCC[(2/ )(Vo(p-p)/2)RL)], (22 V) [[(2/ )(33.7 V/2)/8] 29.5 W, The circuit efficiency is then, % Po /Pi 100% (17.7 W/29.5 W) 100% 60%, , Program 16.3—Op-Amp Push-Pull Amplifier, Figure 16.33 shows an op-amp push-pull amplifier providing ac output to an 8- load., , Figure 16.33, , 716, , Chapter 16, , Op-amp class B amplifier., , Power Amplifiers
Page 743 :
PL, As shown, the op-amp provides a gain of, Av RF/R1 47 k/18 k 2.6, For the input, Vi 1 V, the output is, Vo(p) AvVi 2.6 (1 V) 2.6 V, Figure 16.34 shows the PROBE display of the output voltage., , Figure 16.34 Probe output for, the circuit of Fig. 16.33., , The output power, input power, and circuit efficiency are then calculated to be, Po V o2(p-p)/(8 RL) (20.4 V)2/(8 8 ) 6.5 W, The input power for that amplitude signal is, Pi VCCIdc VCC[(2/ )(Vo(p-p)/2)/RL], (12 V) [(2/ ) (20.4 V/2)/8] 9.7 W, The circuit efficiency is then, % Po /Pi 100% (6.5 W/9.7 W) 100% 67%, , PROBLEMS, , § 16.2 Series-Fed Class A Amplifier, 1. Calculate the input and output power for the circuit of Fig. 16.35. The input signal results in a, base current of 5 mA rms., 2. Calculate the input power dissipated by the circuit of Fig. 16.35 if RB is changed to 1.5 k., 3. What maximum output power can be delivered by the circuit of Fig. 16.35 if RB is changed to, 1.5 k?, 4. If the circuit of Fig. 16.35 is biased at its center voltage and center collector operating point,, what is the input power for a maximum output power of 1.5 W?, , § 16.3 Transformer-Coupled Class A Amplifier, 5. A class A transformer-coupled amplifier uses a 251 transformer to drive a 4- load. Calculate the effective ac load (seen by the transistor connected to the larger turns side of the transformer)., 6. What turns ratio transformer is needed to couple to an 8- load so that it appears as an 8-k, effective load?, 7. Calculate the transformer turns ratio required to connect four parallel 16- speakers so that, they appear as an 8-k effective load., Problems, , Figure 16.35, , Problems 1–4, , 717
Page 744 :
PL, *, , 8. A transformer-coupled class A amplifier drives a 16- speaker through a 3.871 transformer., Using a power supply of VCC 36 V, the circuit delivers 2 W to the load. Calculate:, (a) P(ac) across transformer primary., (b) VL(ac)., (c) V(ac) at transformer primary., (d) The rms values of load and primary current., 9. Calculate the efficiency of the circuit of Problem 8 if the bias current is ICQ 150 mA., 10. Draw the circuit diagram of a class A transformer-coupled amplifier using an npn transistor., , § 16.4 Class B Amplifier Operation, , *, , 11. Draw the circuit diagram of a class B npn push-pull power amplifier using transformer-coupled, input., 12. For a class B amplifier providing a 22-V peak signal to an 8- load and a power supply of, VCC 25 V, determine:, (a) Input power., (b) Output power., (c) Circuit efficiency., 13. For a class B amplifier with VCC 25 V driving an 8- load, determine:, (a) Maximum input power., (b) Maximum output power., (c) Maximum circuit efficiency., 14. Calculate the efficiency of a class B amplifier for a supply voltage of VCC 22 V driving a, 4- load with peak output voltages of:, (a) VL(p) 20 V., (b) VL(p) 4 V., , § 16.5 Class B Amplifier Circuits, 15. Sketch the circuit diagram of a quasi-complementary amplifier, showing voltage waveforms in, the circuit., 16. For the class B power amplifier of Fig. 16.36, calculate:, (a) Maximum Po(ac)., (b) Maximum Pi(dc)., (c) Maximum %., (d) Maximum power dissipated by both transistors., , Figure 16.36, , 718, , Chapter 16, , Power Amplifiers, , Problems 16 and 17
Page 745 :
PL, *, , 17. If the input voltage to the power amplifier of Fig. 16.36 is 8-V rms, calculate:, (a) Pi(dc)., (b) Po(ac)., (c) %., (d) Power dissipated by both power output transistors., , *, , 18. For the power amplifier of Fig. 16.37, calculate:, (a) Po(ac)., (b) Pi(dc)., (c) %., (d) Power dissipated by both output transistors., , Figure 16.37, , Problem 18, , § 16.6 Amplifier Distortion, 19. Calculate the harmonic distortion components for an output signal having fundamental amplitude of 2.1 V, second harmonic amplitude of 0.3 V, third harmonic component of 0.1 V, and, fourth harmonic component of 0.05 V., 20. Calculate the total harmonic distortion for the amplitude components of Problem 19., 21. Calculate the second harmonic distortion for an output waveform having measured values of, VCEmin 2.4 V, VCEQ 10 V, and VCEmax 20 V., 22. For distortion readings of D2 0.15, D3 0.01, and D4 0.05, with I1 3.3 A and RC 4 ,, calculate the total harmonic distortion fundamental power component and total power., , § 16.7 Power Transistor Heat Sinking, 23. Determine the maximum dissipation allowed for a 100-W silicon transistor (rated at 25°C) for, a derating factor of 0.6 W/°C at a case temperature of 150°C., *, , 24. A 160-W silicon power transistor operated with a heat sink (SA 1.5°C/W) has JC 0.5°C/W, and a mounting insulation of CS0.8°C/W. What maximum power can be handled by the transistor at an ambient temperature of 80°C? (The junction temperature should not exceed 200°C.), 25. What maximum power can a silicon transistor (TJmax 200°C) dissipate into free air at an ambient temperature of 80°C?, , Problems, , 719
Page 746 :
PL, § 16.9 PSpice Windows, *, , 26. Use Design Center to draw the schematic of Fig. 16.35 with Vi 9.1 mV., , *, , 27. Use Design Center to draw the schematic of Fig. 16.36 with Vi 25 V(p). Determine the circuit efficiency., , *, , 28. Use Design Center to draw the schematic of an op-amp class B amplifier as in Fig. 16.33. Use, R1 10 k, RF 50 k, and Vi 2.5 V(p). Determine the circuit efficiency., *Please Note: Asterisks indicate more difficult problems., , 720, , Chapter 16, , Power Amplifiers
Page 747 :
CHAPTER, , Linear-Digital ICs, , 17, , 17.1 INTRODUCTION, While there are many ICs containing only digital circuits and many that contain only, linear circuits, there are a number of units that contain both linear and digital circuits., Among the linear/digital ICs are comparator circuits, digital/analog converters, interface circuits, timer circuits, voltage-controlled oscillator (VCO) circuits, and phaselocked loops (PLLs)., The comparator circuit is one to which a linear input voltage is compared to another reference voltage, the output being a digital condition representing whether the, input voltage exceeded the reference voltage., Circuits that convert digital signals into an analog or linear voltage, and those that, convert a linear voltage into a digital value, are popular in aerospace equipment, automotive equipment, and compact disk (CD) players, among many others., Interface circuits are used to enable connecting signals of different digital voltage, levels, from different types of output devices, or from different impedances so that, both the driver stage and the receiver stage operate properly., Timer ICs provide linear and digital circuits to use in various timing operations,, as in a car alarm, a home timer to turn lights on or off, and a circuit in electromechanical equipment to provide proper timing to match the intended unit operation., The 555 timer has long been a popular IC unit. A voltage-controlled oscillator provides an output clock signal whose frequency can be varied or adjusted by an input, voltage. One popular application of a VCO is in a phase-locked loop unit, as used in, various communication transmitters and receivers., , 17.2 COMPARATOR UNIT OPERATION, A comparator circuit accepts input of linear voltages and provides a digital output, that indicates when one input is less than or greater than the second. A basic comparator circuit can be represented as in Fig. 17.1a. The output is a digital signal that, stays at a high voltage level when the noninverting () input is greater than the voltage at the inverting () input and switches to a lower voltage level when the noninverting input voltage goes below the inverting input voltage., Figure 17.1b shows a typical connection with one input (the inverting input in this, example) connected to a reference voltage, the other connected to the input signal, voltage. As long as Vin is less than the reference voltage level of 2 V, the output remains at a low voltage level (near 10 V). When the input rises just above 2 V, the, 721
Page 748 :
+V, −Input, , +V (+10 V), , –, Output, , +Input, , Vref, (+2 V), , –, , Vin, , +, , +, , −V (−10 V), , −V, , Figure 17.1 Comparator unit:, (a) basic unit; (b) typical, application., , Output, , (a), , (b), , output quickly switches to a high-voltage level (near 10 V). Thus the high output, indicates that the input signal is greater than 2 V., Since the internal circuit used to build a comparator contains essentially an opamp circuit with very high voltage gain, we can examine the operation of a comparator using a 741 op-amp, as shown in Fig. 17.2. With reference input (at pin 2) set, to 0 V, a sinusoidal signal applied to the noninverting input (pin 3) will cause the output to switch between its two output states, as shown in Fig. 17.2b. The input Vi going even a fraction of a millivolt above the 0-V reference level will be amplified by, the very high voltage gain (typically over 100,000) so that the output rises to its positive output saturation level and remains there while the input stays above Vref 0 V., When the input drops just below the 0-V reference level, the output is driven to its, lower saturation level and stays there while the input remains below Vref 0 V. Figure 17.2b clearly shows that the input signal is linear while the output is digital., , Figure 17.2 Operation of 741, op-amp as comparator., , In general use, the reference level need not be 0 V but can be any desired positive or negative voltage. Also, the reference voltage may be connected to either plus, or minus input and the input signal then applied to the other input., , Use of Op-Amp as Comparator, Figure 17.3a shows a circuit operating with a positive reference voltage connected to, the minus input and the output connected to an indicator LED. The reference voltage, level is set at, 10 k, Vref (12 V) 6 V, 10 k 10 k, 722, , Chapter 17, , Linear-Digital ICs
Page 749 :
+12 V, , 10 kΩ, , –, 741, 10 kΩ, , Vi, , Vo, , +, , 470 Ω, , −12 V, , LED, , LED on when, Vi goes above, Vref (= +6 V), , LED, , LED on when, Vi goes below, Vref (= +6 V), , (a), +12 V, , 10 kΩ, , Vi, , –, 741, , +, 10 kΩ, , Vo, 470 Ω, , −12 V, , (b), , Figure 17.3 A 741 op-amp, used as a comparator., , Since the reference voltage is connected to the inverting input, the output will switch, to its positive saturation level when the input, Vi, goes more positive than the 6-V, reference voltage level. The output, Vo, then drives the LED on as an indication that, the input is more positive than the reference level., As an alternative connection, the reference voltage could be connected to the noninverting input as shown in Fig. 17.3b. With this connection, the input signal going, below the reference level would cause the output to drive the LED on. The LED can, thus be made to go on when the input signal goes above or below the reference level,, depending on which input is connected as signal input and which as reference input., , Using Comparator IC Units, While op-amps can be used as comparator circuits, separate IC comparator units are, more suitable. Some of the improvements built into a comparator IC are faster switching between the two output levels, built-in noise immunity to prevent the output from, oscillating when the input passes by the reference level, and outputs capable of directly driving a variety of loads. A few popular IC comparators are covered next, describing their pin connections and how they may be used., 311 COMPARATOR, The 311 voltage comparator shown in Fig. 17.4 contains a comparator circuit that, can operate as well from dual power supplies of 15 V as from a single 5-V supply (as used in digital logic circuits). The output can provide a voltage at one of two, distinct levels or can be used to drive a lamp or a relay. Notice that the output is taken, 17.2 Comparator Unit Operation, , 723
Page 750 :
Figure 17.4, , A 311 comparator (eight-pin DIP unit)., , from a bipolar transistor to allow driving a variety of loads. The unit also has balance, and strobe inputs, the strobe input allowing gating of the output. A few examples will, show how this comparator unit can be used in some common applications., A zero-crossing detector that senses (detects) the input voltage crossing through, 0 V is shown using the 311 IC in Fig. 17.5. The inverting input is connected to ground, (the reference voltage). The input signal going positive drives the output transistor on,, with the output then going low (10 V in this case). The input signal going negative, (below 0 V) will drive the output transistor off, the output then going high (to 10, V). The output is thus an indication of whether the input is above or below 0 V. When, the input is any positive voltage, the output is low, while any negative voltage will, result in the output going to a high voltage level., , Figure 17.5, , Zero-crossing detector using a 311 IC., , Figure 17.6 shows how a 311 comparator can be used with strobing. In this example, the output will go high when the input goes above the reference level—but, only if the TTL strobe input is off (or 0 V). If the TTL strobe input goes high, it, drives the 311 strobe input at pin 6 low, causing the output to remain in the off state, (with output high) regardless of the input signal. In effect, the output remains high, 724, , Chapter 17, , Linear-Digital ICs
Page 751 :
Figure 17.6 Operation of a 311, comparator with strobe input., , unless strobed. If strobed, the output then acts normally, switching from high to low, depending on the input signal level. In operation, the comparator output will respond, to the input signal only during the time the strobe signal allows such operation., Figure 17.7 shows the comparator output driving a relay. When the input goes below 0 V, driving the output low, the relay is activated, closing the normally open (N.O.), contacts at that time. These contacts can then be connected to operate a large variety, of devices. For example, a buzzer or bell wired to the contacts can be driven on whenever the input voltage drops below 0 V. As long as the voltage is present at the input, terminal, the buzzer will remain off., , Figure 17.7, , Operation of a 311 comparator with relay output., , 339 COMPARATOR, The 339 IC is a quad comparator containing four independent voltage comparator circuits connected to external pins as shown in Fig. 17.8. Each comparator has inverting and noninverting inputs and a single output. The supply voltage applied to a, pair of pins powers all four comparators. Even if one wishes to use one comparator,, all four will be drawing power., 17.2 Comparator Unit Operation, , 725
Page 752 :
Figure 17.8, IC (339)., , Quad comparator, , To see how these comparator circuits can be used, Fig. 17.9 shows one of the 339, comparator circuits connected as a zero-crossing detector. Whenever the input signal, goes above 0 V, the output switches to V. The input switches to V only when the, input goes below 0 V., A reference level other than 0 V can also be used, and either input terminal could, be used as the reference, the other terminal then being connected to the input signal., The operation of one of the comparator circuits is described next., V + (5 V), , Vi, , 3, , 5, , 5.1 kΩ, , +, , Input, Vi, , Time, , 2, Output, Vo, , 339, 4, Vref = 0 V, , –, , 12, V − (−5 V), , Vo, V+, , (a), Time, , V−, , 726, , Figure 17.9, , Operation of one 339 comparator circuit as a zero-crossing detector., , Chapter 17, , Linear-Digital ICs
Page 753 :
The differential input voltage (difference voltage across input terminals) going, positive drives the output transistor off (open circuit), while a negative differential input voltage drives the output transistor on—the output then at the supply low level., If the negative input is set at a reference level Vref, the positive input goes above, Vref and results in a positive differential input with output driven to the open-circuit, state. When the noninverting input goes below Vref, resulting in a negative differential input, the output will be driven to V., If the positive input is set at the reference level, the inverting input going below, Vref results in the output open circuit while the inverting input going above Vref results in the output at V. This operation is summarized in Fig. 17.10., V+, V+, Vref, , +, , Input, , +, Input < Vref ← output open circuit, , Input > Vref ← output open circuit, 339, Vref, , 339, , Input < Vref ← output =V −, , –, , Input, V−, , ← output, , =V−, , –, V−, , (a), , Figure 17.10, input., , Input > Vref, , (b), , Operation of a 339 comparator circuit with reference input: (a) minus input; (b) plus, , Since the output of one of these comparator circuits is from an open-circuit collector, applications in which the outputs from more than one circuit can be wire-ORed, are possible. Figure 17.11 shows two comparator circuits connected with common, output and also with common input. Comparator 1 has a 5-V reference voltage in+9 V, , 4, , –, , 5.1 kΩ, , 3, 2, , 7.5 kΩ, , Output, , 1, 5, , +, 9.1 kΩ, Vref1 ≅ +5 V, +9 V, 8.2 kΩ, Vref2 ≅ +1 V, , +5 V, , 6, , –, , Output high, , 1, , 1 kΩ, , 2, , +1 V, , 7, , +, , Output low, , Output low, , 12, , Figure 17.11 Operation of two, 339 comparator circuits as a, window detector., , Input, , 17.2 Comparator Unit Operation, , 727
Page 754 :
put connected to the noninverting input. The output will be driven low by comparator 1 when the input signal goes above 5 V. Comparator 2 has a reference voltage, of 1 V connected to the inverting input. The output of comparator 2 will be driven, low when the input signal goes below 1 V. In total, the output will go low whenever the input is below 1 V or above 5 V, as shown in Fig. 17.11, the overall operation being that of a voltage window detector. The high output indicates that the input is within a voltage window of 1 to 5 V (these values being set by the reference, voltage levels used)., , 17.3 DIGITAL–ANALOG CONVERTERS, Many voltages and currents in electronics vary continuously over some range of values. In digital circuitry the signals are at either one of two levels, representing the binary values of 1 or zero. An analog–digital converter (ADC) obtains a digital value, representing an input analog voltage, while a digital–analog converter (DAC) changes, a digital value back into an analog voltage., , Digital-to-Analog Conversion, LADDER NETWORK CONVERSION, Digital-to-analog conversion can be achieved using a number of different methods. One popular scheme uses a network of resistors, called a ladder network. A ladder network accepts inputs of binary values at, typically, 0 V or Vref and provides an, output voltage proportional to the binary input value. Figure 17.12a shows a ladder, network with four input voltages, representing 4 bits of digital data and a dc voltage, output. The output voltage is proportional to the digital input value as given by the, relation, D0 20 D1 21 D2 22 D3 23, Vref, Vo , 24, , Figure 17.12 Four-stage ladder network used as a DAC: (a) basic circuit;, (b) circuit example with 0110 input., , 728, , Chapter 17, , Linear-Digital ICs, , (17.1)
Page 755 :
In the example shown in Fig. 17.12b, the output voltage resulting should be, 01121408, Vo (16 V) 6 V, 16, Therefore, 01102, digital, converts to 6 V, analog., The function of the ladder network is to convert the 16 possible binary values, from 0000 to 1111 into one of 16 voltage levels in steps of Vref/16. Using more sections of ladder allows having more binary inputs and greater quantization for each, step. For example, a 10-stage ladder network could extend the number of voltage steps, or the voltage resolution to Vref/210 or Vref/1024. A reference voltage of Vref 10 V, would then provide output voltage steps of 10 V/1024 or approximately 10 mV. More, ladder stages provide greater voltage resolution. In general, the voltage resolution for, n ladder stages is, V ef, r, 2n, , (17.2), , Figure 17.13 shows a block diagram of a typical DAC using a ladder network., The ladder network, referred in the diagram as an R-2R ladder, is sandwiched between the reference current supply and current switches connected to each binary input, the resulting output current proportional to the input binary value. The binary input turns on selected legs of the ladder, the output current being a weighted summing, of the reference current. Connecting the output current through a resistor will produce an analog voltage, if desired., , Digital inputs, , Current switches, , Io, , R-2 R ladder, , Vref, , Reference, current, , Figure 17.13 DAC IC using, R-2R ladder network., , Analog-to-Digital Conversion, DUAL-SLOPE CONVERSION, A popular method for converting an analog voltage into a digital value is the dualslope method. Figure 17.14a shows a block diagram of the basic dual-slope converter., The analog voltage to be converted is applied through an electronic switch to an integrator or ramp-generator circuit (essentially a constant current charging a capacitor, to produce a linear ramp voltage). The digital output is obtained from a counter operated during both positive and negative slope intervals of the integrator., The method of conversion proceeds as follows. For a fixed time interval (usually, the full count range of the counter), the analog voltage connected to the integrator, raises the voltage at the comparator input to some positive level. Figure 17.14b shows, that at the end of the fixed time interval the voltage from the integrator is greater for, the larger input voltage. At the end of the fixed count interval, the count is set to zero, and the electronic switch connects the integrator to a reference or fixed input voltage., 17.3, , Digital-Analog Converters, , 729
Page 756 :
Analog input, , Digital input, , Integrator, Comparator, , Reference, input, , Count, pulses, , Stop, count, , Control, logic, , Digital, counter, , Clear, pulse, , Vref, , Count over, Clock, , Linear, , Digital, , Linear/Digital, (a), , L, , ar, , r, ge, , in, , pu, , ut, Inp, , o, tv, , lta, , ge, , Fixed, discharge, rate, , e, , tag, , vol, , e, , put voltag, , Smaller in, , Smaller, digital, count, , Digital, count, , Larger, digital, count, , Fixed time, interval, Count interval, (b), , Figure 17.14 Analog-to-digital conversion using dual-slope method: (a) logic diagram;, (b) waveform., , The integrator output (or capacitor input) then decreases at a fixed rate. The counter, advances during this time, while the integrator’s output decreases at a fixed rate until it drops below the comparator reference voltage, at which time the control logic, receives a signal (the comparator output) to stop the count. The digital value stored, in the counter is then the digital output of the converter., Using the same clock and integrator to perform the conversion during positive and, negative slope intervals tends to compensate for clock frequency drift and integrator, accuracy limitations. Setting the reference input value and clock rate can scale the, counter output as desired. The counter can be a binary, BCD, or other form of digital counter, if desired., LADDER-NETWORK CONVERSION, Another popular method of analog-to-digital conversion uses a ladder network, along with counter and comparator circuits (see Fig. 17.15). A digital counter advances from a zero count while a ladder network driven by the counter outputs a staircase voltage, as shown in Fig. 17.15b, which increases one voltage increment for each, count step. A comparator circuit, receiving both staircase voltage and analog input, 730, , Chapter 17, , Linear-Digital ICs
Page 757 :
Figure 17.15 Analog-to-digital conversion using ladder network: (a) logic diagram; (b) waveform., , voltage, provides a signal to stop the count when the staircase voltage rises above the, input voltage. The counter value at that time is the digital output., The amount of voltage change stepped by the staircase signal depends on the number of count bits used. A 12-stage counter operating a 12-stage ladder network using, a reference voltage of 10 V would step each count by a voltage of, V f, 10 V, 1re, 2 2.4 mV, 2, 4096, This would result in a conversion resolution of 2.4 mV. The clock rate of the counter, would affect the time required to carry out a conversion. A clock rate of 1 MHz operating a 12-stage counter would need a maximum conversion time of, 4096 1 s 4096 s 4.1 ms, The minimum number of conversions that could be carried out each second would, then be, number of conversions 1/4.1 ms 244 conversions/second, Since on the average, with some conversions requiring little count time and others, near maximum count time, a conversion time of 4.1 ms/2 2.05 ms would be needed,, and the average number of conversions would be 2 244 488 conversions/second., A slower clock rate would result in fewer conversions per second. A converter using, fewer count stages (and less conversion resolution) would carry out more conversions, per second. The conversion accuracy depends on the accuracy of the comparator., 17.3, , Digital-Analog Converters, , 731
Page 758 :
17.4 TIMER IC UNIT OPERATION, Another popular analog–digital integrated circuit is the versatile 555 timer. The IC is, made of a combination of linear comparators and digital flip-flops as described in, Fig. 17.16. The entire circuit is usually housed in an 8-pin package as specified in, Fig. 17.16. A series connection of three resistors sets the reference voltage levels to, the two comparators at 2VCC/3 and VCC/3, the output of these comparators setting or, resetting the flip-flop unit. The output of the flip-flop circuit is then brought out, through an output amplifier stage. The flip-flop circuit also operates a transistor inside the IC, the transistor collector usually being driven low to discharge a timing capacitor., VCC, , Threshold, 6, , 8, R, Control, voltage, , +, ( 23 VCC), , 5, R, , –, , 1, Output, stage, , F/F, ( 13 VCC), , Discharge, , –, , R, , Figure 17.16, timer IC., , Details of 555, , Output, 7, , +, 2, , 1, , 3, , 2, Trigger, input, , 4, Reset, , Vref, , Astable Operation, One popular application of the 555 timer IC is as an astable multivibrator or clock, circuit. The following analysis of the operation of the 555 as an astable circuit includes details of the different parts of the unit and how the various inputs and outputs are utilized. Figure 17.17 shows an astable circuit built using an external resistor and capacitor to set the timing interval of the output signal., Figure 17.17 Astable, multivibrator using 555 IC., , 732
Page 759 :
Capacitor C charges toward VCC through external resistors RA and RB. Referring, to Fig. 17.17, the capacitor voltage rises until it goes above 2VCC/3. This voltage is, the threshold voltage at pin 6, which drives comparator 1 to trigger the flip-flop so, that the output at pin 3 goes low. In addition, the discharge transistor is driven on,, causing the output at pin 7 to discharge the capacitor through resistor RB. The capacitor voltage then decreases until it drops below the trigger level (VCC/3). The flipflop is triggered so that the output goes back high and the discharge transistor is turned, off, so that the capacitor can again charge through resistors RA and RB toward VCC., Figure 17.18a shows the capacitor and output waveforms resulting from the astable, circuit. Calculation of the time intervals during which the output is high and low can, be made using the relations, Thigh 0.7(RA RB)C, , (17.3), , Tlow 0.7RBC, , (17.4), , T period Thigh Tlow, , (17.5), , The total period is, , The frequency of the astable circuit is then calculated using*, 1, 1.44, f , T, (RA 2RB)C, , Figure 17.18, , (17.6), , Astable multivibrator for Example 17.1: (a) circuit; (b) waveforms., , *The period can be directly calculated from, T 0.693(RA 2RB)C 0.7(RA 2RB)C, and the frequency from, 1.44, f , (RA 2RB)C, , 17.4, , Timer IC Unit Operation, , 733
Page 760 :
EXAMPLE 17.1, , Determine the frequency and draw the output waveform for the circuit of Fig. 17.18a., , Solution, Using Eqs. (17.3) through (17.6) yields, Thigh 0.7(RA RB)C 0.7(7.5 103 7.5 103)(0.1 106), 1.05 ms, Tlow 0.7RBC 0.7(7.5 103)(0.1 106) 0.525 ms, T Thigh Tlow 1.05 ms 0.525 ms 1.575 ms, 1, 1, f , 635 Hz, T, 1.575 103, The waveforms are drawn in Fig. 17.18b., , Monostable Operation, The 555 timer can also be used as a one-shot or monostable multivibrator circuit, as, shown in Fig. 17.19. When the trigger input signal goes negative, it triggers the oneshot, with output at pin 3 then going high for a time period, Thigh 1.1RAC, , (17.7), , Referring back to Fig. 17.16, the negative edge of the trigger input causes comparator 2 to trigger the flip-flop, with the output at pin 3 going high. Capacitor C charges, toward VCC through resistor RA. During the charge interval, the output remains high., When the voltage across the capacitor reaches the threshold level of 2VCC/3, comparator 1 triggers the flip-flop, with output going low. The discharge transistor also, goes low, causing the capacitor to remain at near 0 V until triggered again., Figure 17.19b shows the input trigger signal and the resulting output waveform, for the 555 timer operated as a one-shot. Time periods for this circuit can range from, microseconds to many seconds, making this IC useful for a range of applications., , Figure 17.19, , 734, , Chapter 17, , Operation of 555 timer as one-shot: (a) circuit; (b) waveforms., , Linear-Digital ICs
Page 761 :
Determine the period of the output waveform for the circuit of Fig. 17.20 when triggered by a negative pulse., , EXAMPLE 17.2, , Figure 17.20 Monostable circuit for Example 17.2., , Solution, Using Eq. (17.7), we obtain, Thigh 1.1RAC 1.1(7.5 103)(0.1 106) 0.825 ms, , 17.5 VOLTAGE-CONTROLLED, OSCILLATOR, A voltage-controlled oscillator (VCO) is a circuit that provides a varying output signal (typically of square-wave or triangular-wave form) whose frequency can be adjusted over a range controlled by a dc voltage. An example of a VCO is the 566 IC, unit, which contains circuitry to generate both square-wave and triangular-wave signals whose frequency is set by an external resistor and capacitor and then varied by, an applied dc voltage. Figure 17.21a shows that the 566 contains current sources to, charge and discharge an external capacitor C1 at a rate set by external resistor R1 and, the modulating dc input voltage. A Schmitt trigger circuit is used to switch the current sources between charging and discharging the capacitor, and the triangular voltage developed across the capacitor and square wave from the Schmitt trigger are provided as outputs through buffer amplifiers., Figure 17.21b shows the pin connection of the 566 unit and a summary of formula and value limitations. The oscillator can be programmed over a 10-to-1 frequency range by proper selection of an external resistor and capacitor, and then modulated over a 10-to-1 frequency range by a control voltage, VC., A free-running or center-operating frequency, fo, can be calculated from, 2, V VC, fo , , R1C1, V, , , , , , (17.8), , with the following practical circuit value restrictions:, 1. R1 should be within the range 2 k R1 20 k., 2. VC should be within range 34V VC V., 17.5, , Voltage-Controlled Oscillator, , 735
Page 762 :
Figure 17.21 A 566 function, generator: (a) block diagram;, (b) pin configuration and summary, of operating data., , 3. fo should be below 1 MHz., 4. V should range between 10 V and 24 V., Figure 17.22 shows an example in which the 566 function generator is used to, provide both square-wave and triangular-wave signals at a fixed frequency set by R1,, C1, and VC. A resistor divider R2 and R3 sets the dc modulating voltage at a fixed, value, , Figure 17.22 Connection of, 566 VCO unit., , 736, , Chapter 17, , Linear-Digital ICs
Page 763 :
R3, 10 k, VC , V (12 V) 10.4 V, R2 R3, 1.5 k 10 k, (which falls properly in the voltage range 0.75V 9 V and V 12 V). Using Eq., (17.8) yields, 12 10.4, 2, 32.5 kHz, fo , (10 103)(820 1012), 12, , , , , , The circuit of Fig. 17.23 shows how the output square-wave frequency can be adjusted using the input voltage, VC, to vary the signal frequency. Potentiometer R3 allows varying VC from about 9 V to near 12 V, over the full 10-to-1 frequency range., With the potentiometer wiper set at the top, the control voltage is, 5 k 18 k, R3 R4, (V) (12 V) 11.74 V, VC , 510, , 5 k 18 k, R2 R3 R4, resulting in a lower output frequency of, 2, 12 11.74, 19.7 kHz, fo , (10 103)(220 1012), 12, , , , , , Figure 17.23 Connection of, 566 as a VCO unit., , With the wiper arm of R3 set at the bottom, the control voltage is, 18 k, R4, , ) (12 V) 9.19 V, VC (V, 510 5 k 18 k, R2 R3 R4, resulting in an upper frequency of, 2, 12 9.19, 212.9 kHz, fo , (10 103)(220 1012), 12, , , , , , The frequency of the output square wave can then be varied using potentiometer R3, over a frequency range of at least 10 to 1., Rather than varying a potentiometer setting to change the value of VC, an input, modulating voltage, Vin, can be applied as shown in Fig. 17.24. The voltage divider, sets VC at about 10.4 V. An input ac voltage of about 1.4 V peak can drive VC around, the bias point between voltages of 9 and 11.8 V, causing the output frequency to vary, over about a 10-to-1 range. The input signal Vin thus frequency-modulates the output, voltage around the center frequency set by the bias value of VC 10.4 V ( fo , 121.2 kHz)., 17.5, , Voltage-Controlled Oscillator, , 737
Page 764 :
Figure 17.24 Operation of, VCO with frequency-modulating, input., , 17.6 PHASE-LOCKED LOOP, A phase-locked loop (PLL) is an electronic circuit that consists of a phase detector,, a low-pass filter, and a voltage-controlled oscillator connected as shown in Fig. 17.25., Common applications of a PLL include: (1) frequency synthesizers that provide multiples of a reference signal frequency [e.g., the carrier frequency for the multiple channels of a citizens’ band (CB) unit or marine-radio-band unit can be generated using, a single-crystal-controlled frequency and its multiples generated using a PLL]; (2), FM demodulation networks for FM operation with excellent linearity between the input signal frequency and the PLL output voltage; (3) demodulation of the two data, transmission or carrier frequencies in digital-data transmission used in frequency-shift, keying (FSK) operation; and (4) a wide variety of areas including modems, telemetry receivers and transmitters, tone decoders, AM detectors, and tracking filters., An input signal, Vi, and that from a VCO, Vo, are compared by a phase comparator, (refer to Fig. 17.25) providing an output voltage, Ve, that represents the phase difference between the two signals. This voltage is then fed to a low-pass filter that pro-, , Figure 17.25, , 738, , Chapter 17, , Block diagram of basic phase-locked loop (PLL)., , Linear-Digital ICs
Page 765 :
vides an output voltage (amplified if necessary) that can be taken as the output voltage from the PLL and is used internally as the voltage to modulate the VCO’s frequency. The closed-loop operation of the circuit is to maintain the VCO frequency, locked to that of the input signal frequency., , Basic PLL Operation, The basic operation of a PLL circuit can be explained using the circuit of Fig. 17.25, as reference. We will first consider the operation of the various circuits in the phaselocked loop when the loop is operating in lock (the input signal frequency and the, VCO frequency are the same). When the input signal frequency is the same as that, from the VCO to the comparator, the voltage, Vd, taken as output is the value needed, to hold the VCO in lock with the input signal. The VCO then provides output of a, fixed-amplitude square-wave signal at the frequency of the input. Best operation is, obtained if the VCO center frequency, fo, is set with the dc bias voltage midway in, its linear operating range. The amplifier allows this adjustment in dc voltage from that, obtained as output of the filter circuit. When the loop is in lock, the two signals to, the comparator are of the same frequency, although not necessarily in phase. A fixed, phase difference between the two signals to the comparator results in a fixed dc voltage to the VCO. Changes in the input signal frequency then result in change in the, dc voltage to the VCO. Within a capture-and-lock frequency range, the dc voltage, will drive the VCO frequency to match that of the input., While the loop is trying to achieve lock, the output of the phase comparator contains frequency components at the sum and difference of the signals compared. A lowpass filter passes only the lower-frequency component of the signal so that the loop, can obtain lock between input and VCO signals., Owing to the limited operating range of the VCO and the feedback connection of, the PLL circuit, there are two important frequency bands specified for a PLL. The, capture range of a PLL is the frequency range centered about the VCO free-running, frequency, fo, over which the loop can acquire lock with the input signal. Once the, PLL has achieved capture, it can maintain lock with the input signal over a somewhat, wider frequency range called the lock range., , Applications, The PLL can be used in a wide variety of applications, including (1) frequency demodulation, (2) frequency synthesis, and (3) FSK decoders. Examples of each of these, follow., FREQUENCY DEMODULATION, FM demodulation or detection can be directly achieved using the PLL circuit. If, the PLL center frequency is selected or designed at the FM carrier frequency, the filtered or output voltage of the circuit of Fig. 17.25 is the desired demodulated voltage, varying in value proportional to the variation of the signal frequency. The PLL, circuit thus operates as a complete intermediate-frequency (IF) strip, limiter, and demodulator as used in FM receivers., One popular PLL unit is the 565, shown in Fig. 17.26a. The 565 contains a phase, detector, amplifier, and voltage-controlled oscillator, which are only partially connected internally. An external resistor and capacitor, R1 and C1, are used to set the, free-running or center frequency of the VCO. Another external capacitor, C2, is used, to set the low-pass filter passband, and the VCO output must be connected back as, input to the phase detector to close the PLL loop. The 565 typically uses two power, supplies, V and V., 17.6, , Phase-Locked Loop, , 739
Page 766 :
V+, 10, , 565, , C2, , 2, Input, , 3.6 kΩ, , Phase, detector, , 3, , Amp., , 5, 4, , 7, , Demodulated, output, , 6, , Reference, output, , VCO, , Output, , 9, , 8, R1, , 1, V−, , C1, , (a), , +6 V, 10, C2, 330 pF, Demodulated, output, , 2, , FM signal, input, , 3.6 kΩ, , Phase, detector, , 3, , Amp., , 7, , 5, , Reference, output, , 6, 4, , VCO, , Output, 8, R1, 10 kΩ, , V7, , +6 V, , +5.3 V, , 9, , C1, 220 pF, , 1, fo =, , 0.3, R1 C1, , −6 V, (b), , +5 V, +4.7 V, , Frequency, fo, fL, fL, (= 136.36 kHz) fo +, 2, 2, (= 45.45 kHz), (= 227.27 kHz), ± fL, (± 181.82 kHz), fo −, , Figure 17.26 Phase-locked loop, (PLL): (a) basic block diagram:, (b) PLL connected as a frequency, demodulator: (c) output voltage, vs. frequency plot., , (c), , Figure 17.26b shows the PLL connected to work as an FM demodulator. Resistor R1 and capacitor C1 set the free-running frequency, fo,, 0.3, fo , R1C1, , (17.9), , 0.3, , 136.36 kHz, 3, (10 10 )(220 1012), with limitation 2 k, , R1, , 20 k. The lock range is, 8f, fL o, V, 8(136.36 103), 181.8 kHz, 6, , 740, , Chapter 17, , Linear-Digital ICs
Page 767 :
for supply voltages V 6 V. The capture range is, , , 2 (181.8 10 ), 1, 156.1 kHz, (3.6 10 )(330 10 ), 2 , 1, 2 fL, fC , 2, R2C2, 3, , 12, , 3, , The signal at pin 4 is a 136.36-kHz square wave. An input within the lock range of, 181.8 kHz will result in the output at pin 7 varying around its dc voltage level set, with input signal at fo. Figure 17.26c shows the output at pin 7 as a function of the, input signal frequency. The dc voltage at pin 7 is linearly related to the input signal, frequency within the frequency range fL 181.8 kHz around the center frequency, 136.36 kHz. The output voltage is the demodulated signal that varies with frequency, within the operating range specified., FREQUENCY SYNTHESIS, A frequency synthesizer can be built around a PLL as shown in Fig. 17.27. A frequency divider is inserted between the VCO output and the phase comparator so that, the loop signal to the comparator is at frequency fo while the VCO output is Nfo. This, output is a multiple of the input frequency as long as the loop is in lock. The input, signal can be stabilized at f1 with the resulting VCO output at Nf1 if the loop is set, , Input, f1, , Phase, comparator, , Low-pass, filter, , Amp., , fo, , ÷N, , VCO, Output, Nfo, (a), +5 V, , C2, 330 pF, R1, 10 kΩ, , 5.1 kΩ, 8, , 7, , 10, 4, , 2, , 14, , Nfo, , 565, Vi, f1, , Input A, , 10 kΩ, , 5, , 5, , 3, 9, , 9, , 1, , 7490, , C1, 220 pF, −5 V, , 1 12, , 8, , QA ÷ 2, QB ÷ 4, QC ÷ 8, , QD ÷ 16, 10, 11, 3, 6, 2, 7, R0 (1) R0 (2) R 9 (1) R 9 (2), fo, , (b), , Figure 17.27, , Frequency synthesizer: (a) block diagram; (b) implementation using 565 PLL unit., , 17.6, , Phase-Locked Loop, , 741
Page 768 :
up to lock at the fundamental frequency (when fo f1). Figure 17.27b shows an example using a 565 PLL as frequency multiplier and a 7490 as divider. The input Vi, at frequency f1 is compared to the input (frequency fo) at pin 5. An output at Nfo (4fo, in the present example) is connected through an inverter circuit to provide an input, at pin 14 of the 7490, which varies between 0 and 5 V. Using the output at pin 9,, which is divided by 4 from that at the input to the 7490, the signal at pin 4 of the, PLL is four times the input frequency as long as the loop remains in lock. Since the, VCO can vary over only a limited range from its center frequency, it may be necessary to change the VCO frequency whenever the divider value is changed. As long as, the PLL circuit is in lock, the VCO output frequency will be exactly N times the input frequency. It is only necessary to readjust fo to be within the capture-and-lock, range, the closed loop then resulting in the VCO output becoming exactly Nf1 at lock., FSK DECODERS, An FSK (frequency-shift keyed) signal decoder can be built as shown in Fig. 17.28., The decoder receives a signal at one of two distinct carrier frequencies, 1270 Hz or, 1070 Hz, representing the RS-232C logic levels or mark (5 V) or space (14 V),, respectively. As the signal appears at the input, the loop locks to the input frequency, and tracks it between two possible frequencies with a corresponding dc shift at the, output., , Figure 17.28 Connection of, 565 as FSK decoder., , The RC ladder filter (three sections of C 0.02 F and R 10 k) is used to, remove the sum frequency component. The free-running frequency is adjusted with, R1 so that the dc voltage level at the output (pin 7) is the same as that at pin 6. Then, an input at frequency 1070 Hz will drive the decoder output voltage to a more positive voltage level, driving the digital output to the high level (space or 14 V). An, input at 1270 Hz will correspondingly drive the 565 dc output less positive with the, digital output, which then drops to the low level (mark or 5 V)., , 17.7 INTERFACING CIRCUITRY, Connecting different types of circuits, either in digital or analog circuits, may require, some sort of interfacing circuit. An interface circuit may be used to drive a load or to, obtain a signal as a receiver circuit. A driver circuit provides the output signal at a, 742, , Chapter 17, , Linear-Digital ICs
Page 769 :
voltage or current level suitable to operate a number of loads, or to operate such devices as relays, displays, or power units. A receiver circuit essentially accepts an input signal, providing high input impedance to minimize loading of the input signal., Furthermore, the interface circuits may include strobing, which provides connecting, the interface signals during specific time intervals established by the strobe., Figure 17.29a shows a dual-line driver, each driver accepting input of TTL signals, providing output capable of driving TTL or MOS device circuits. This type of, interface circuit comes in various forms, some as inverting and others as noninverting units. The circuit of Fig. 17.29b shows a dual-line receiver having both inverting, and noninverting inputs so that either operating condition can be selected. As an example, connection of an input signal to the inverting input would result in an inverted, output from the receiver unit. Connecting the input to the noninverting input would, provide the same interfacing except that the output obtained would have the same polarity as the received signal. The driver-receiver unit of Fig. 17.29 provides an output, when the strobe signal is present (high in this case)., , Figure 17.29 Interface units: (a) dual-line drivers (SN75150); (b) dual-line, receivers (SN75152)., , Another type of interface circuit is that used to connect various digital input and, output units, signals with devices such as keyboards, video terminals, and printers., One of the EIA electronic industry standards is referred to as RS-232C. This standard, states that a digital signal represents a mark (logic-1) and a space (logic-0). The definitions of mark and space vary with the type of circuit used (although a full reading, of the standard will spell out the acceptable limits of mark and space signals)., 17.7 Interfacing Circuitry, , 743
Page 770 :
RS-232C-to-TTL Converter, For TTL circuits, 5 V is a mark and 0 V is a space. For RS-232C, a mark could be, 12 V and a space 12 V. Figure 17.30a provides a tabulation of some mark and, space definitions. For a unit having outputs defined by RS-232C that is to operate, into another unit operating with a TTL signal level, an interface circuit as shown in, Fig. 17.30b could be used. A mark output from the driver (at 12 V) would be clipped, by the diode so that the input to the inverter circuit is near 0 V, resulting in an output of 5 V (TTL mark). A space output at 12 V would drive the inverter output, low for a 0-V output (a space)., , Figure 17.30, , Interfacing signal standards and converter circuits., , Another example of an interface circuit converts the signals from a TTY current, loop into TTL levels as shown in Fig. 17.30c. An input mark results when 20 mA of, current is drawn from the source through the output line of the teletype (TTY). This, current then goes through the diode element of an opto-isolator, driving the output, transistor on. The input to the inverter going low results in a 5-V signal from the, 7407 inverter output so that a mark from the teletype results in a mark to the TTL, input. A space from the teletype current loop provides no current, with the optoisolator transistor remaining off and the inverter output then 0 V, which is a TTL, space signal., Another means of interfacing digital signals is made using open-collector output, or tri-state output. When a signal is output from a transistor collector (see Fig. 17.31), that is not connected to any other electronic component, the output is open-collector., This permits connecting a number of signals to the same wire or bus. Any transistor, going on then provides a low output voltage, while all transistors remaining off provide a high output voltage., 744, , Chapter 17, , Linear-Digital ICs
Page 771 :
Figure 17.31, , Connections to data lines: (a) open-collector output; (b) tri-state output., , 17.8 PSPICE WINDOWS, Many of the practical op-amp applications covered in this chapter can be analyzed, using PSpice. Analysis of various problems can display the resulting dc bias, or one, can use PROBE to display resulting waveforms., , Program 17.1—Comparator Circuit Used to Drive an LED, Using Design Center, draw the circuit of a comparator circuit with output driving an, LED indicator as shown in Fig. 17.32. To be able to view the magnitude of the dc, output voltage, place a VPRINT1 component at Vo with DC and MAG selected. To, view the dc current through the LED, place an IPRINT component in series with the, LED current meter as shown in Fig. 17.32. The Analysis Setup provides for a dc, sweep as shown in Fig. 17.33. The DC Sweep is set, as shown, for Vi from 4 to 8 V, in 1-V steps. After running the simultation, some of the resulting analysis output obtained is shown in Fig. 17.34., , Figure 17.32, , Comparator circuit used to drive an LED., , 17.8, , PSpice Windows, , 745
Page 772 :
Figure 17.33, , Analysis Setup for a dc sweep of the circuit of Fig. 17.32., , The circuit of Fig. 17.32 shows a voltage divider which provides 6 V to the minus input so that any input (Vi) below 6 V will result in the output at the minus saturation voltage (near 10 V). Any input above 6 V results in the output going to, the positive saturation level (near 10 V). The LED will therefore be driven on by, any input above the reference level of 6 V and left off by any input below 6 V., The listing of Fig. 17.34 shows a table of the output voltage and a table of the LED, current for inputs from 4 to 8 V. The table shows that the LED current is nearly 0 for, inputs up to 6 V and that a current of about 20 mA lights the LED for inputs at 6, V or above., , Program 17.2—Comparator Operation, , Figure 17.34 Analysis output, (edited) for circuit of Fig. 17.32., , The operation of a comparator IC can be demonstrated using a 741 op-amp as shown, in Fig. 17.35. The input is a 5 V, peak sinusoidal signa. The Analysis Setup provides, for Transient analysis with Print Step of 20 ns and Final Time of 3 ms. Since the, input signal is applied to the noninverting input, the output is in-phase with the input. When the input goes above 0 V, the output goes to the positive saturation level,, , 746, , Chapter 17, , Linear-Digital ICs
Page 773 :
Figure 17.35, comparator., , Schematic for a, , near 5 V. When the input goes below 0 V, the output goes to the negative saturation level—this being 0 V since the minus voltage input is set to that value. Figure, 17.36 shows a PROBE output of input and output voltages., , Figure 17.36, , Probe output for the comparator of Fig. 17.35., , Program 17.3—Operation of 555 Timer as Oscillator, Figure 17.37 shows a 555 timer connected as an oscillator. Equations (17.3) and (17.4), can be used to calculate the charge and discharge times as follows:, Thigh 0.7(RA RB)C 0.7(7.5 k 7.15 k)(0.1 F) 1.05 ms, Tlow 0.7RBC 0.7(7.5 k)(0.1 F) 0.525 ms, , Figure 17.37, , Schematic of a 555 timer oscillator., , 17.8, , PSpice Windows, , 747
Page 774 :
Figure 17.38, , Probe output for the 555 oscillator of Fig. 17.37., , The resulting trigger and output waveforms are shown in Fig. 17.38. When the trigger charges to the upper trigger level, the output goes to the low output level of 0 V., The output stays low until the trigger input discharges to the low trigger level, at which, time the output goes to the high level of 5 V., , PROBLEMS, , § 17.2 Comparator Unit Operation, 1. Draw the diagram of a 741 op-amp operated from 15-V supplies with Vi() 0 V and, Vi() 5 V. Include terminal pin connections., 2. Sketch the output waveform for the circuit of Fig. 17.39., 3. Draw a circuit diagram of a 311 op-amp showing an input of 10 V rms applied to the inverting input and the plus input to ground. Identify all pin numbers., 4. Draw the resulting output waveform for the circuit of Fig. 17.40., , Figure 17.39, , Problem 2, , Figure 17.40, , Problem 4, , 5. Draw the circuit diagram of a zero-crossing detector using a 339 comparator stage with 12-V, supplies., , 748, , Chapter 17, , Linear-Digital ICs
Page 775 :
6. Sketch the output waveform for the circuit of Fig. 17.41., , Figure 17.41, *, , Problem 6, , 7. Describe the operation of the circuit in Fig. 17.42., , Figure 17.42, , Problem 7, , § 17.3 Digital–Analog Converters, 8. Sketch a five-stage ladder network using 15-k and 30-k resistors., 9. For a reference voltage of 16 V, calculate the output voltage for an input of 11010 to the circuit of Problem 8., 10. What voltage resolution is possible using a 12-stage ladder network with a 10-V reference voltage?, Problems, , 749
Page 776 :
11. For a dual-slope converter, describe what occurs during the fixed time interval and the count, interval., 12. How many count steps occur using a 12-stage digital counter at the output of an ADC?, 13. What is the maximum count interval using a 12-stage counter operated at a clock rate of, 20 MHz?, , § 17.4 Timer IC Unit Operation, 14. Sketch the circuit of a 555 timer connected as an astable multivibrator for operation at, 350 kHz. Determine the value of capacitor, C, needed using RA RB 7.5 k., 15. Draw the circuit of a one-shot using a 555 timer to provide one time period of 20 s. If RA , 7.5 k, what value of C is needed?, 16. Sketch the input and output waveforms for a one-shot using a 555 timer triggered by a 10-kHz, clock for RA 5.1 k and C 5 nF., , § 17.5 Voltage-Controlled Oscillator, 17. Calculate the center frequency of a VCO using a 566 IC as in Fig. 17.22 for R1 4.7 k,, R2 1.8 k, R3 11 k, and C1 0.001 F., *, , 18. What frequency range results in the circuit of Fig. 17.23 for C1 0.001 F?, 19. Determine the capacitor needed in the circuit of Fig. 17.22 to obtain a 200-kHz output., , § 17.6 Phase-Locked Loop, 20. Calculate the VCO free-running frequency for the circuit of Fig. 17.26b with R1 4.7 k and, C1 0.001 F., 21. What value of capacitor, C1, is required in the circuit of Fig. 17.26b to obtain a center frequency of 100 kHz?, 22. What is the lock range of the PLL circuit in Fig. 17.26b for R1 4.7 k and C1 0.001 F?, , § 17.7 Interfacing Circuitry, 23. Describe the signal conditions for current-loop and RS-232C interfaces., 24. What is a data bus?, 25. What is the difference between open-collector and tri-state output?, , § 17.8 PSpice Windows, *, , 26. Use Design Center to draw a schematic circuit as in Fig. 17.32, using an LM111 with Vi 5 V, rms applied to minus () input and 5 V rms applied to plus () input. Use Probe to view, the output waveform., , *, , 27. Use Design Center to draw a schematic circuit as in Fig. 17.35. Examine the output listing for, the results., , *, , 28. Use Design Center to draw a 555 oscillator with resulting output with tlow 2 ms, thigh , 5 ms., *Please note: Asterisks indicate more difficult problems., , 750, , Chapter 17, , Linear-Digital ICs
Page 777 :
Af, CHAPTER, , Feedback, and Oscillator, Circuits, , 18, , 18.1 FEEDBACK CONCEPTS, Feedback has been mentioned previously. In particular, feedback was used in op-amp, circuits as described in Chapters 14 and 15. Depending on the relative polarity of the, signal being fed back into a circuit, one may have negative or positive feedback. Negative feedback results in decreased voltage gain, for which a number of circuit features are improved as summarized below. Positive feedback drives a circuit into oscillation as in various types of oscillator circuits., A typical feedback connection is shown in Fig. 18.1. The input signal, Vs, is applied to a mixer network, where it is combined with a feedback signal, Vf. The difference of these signals, Vi, is then the input voltage to the amplifier. A portion of the, amplifier output, Vo, is connected to the feedback network (), which provides a reduced portion of the output as feedback signal to the input mixer network., If the feedback signal is of opposite polarity to the input signal, as shown in Fig., 18.1, negative feedback results. While negative feedback results in reduced overall, voltage gain, a number of improvements are obtained, among them being:, 1., 2., 3., 4., 5., 6., , Higher input impedance., Better stabilized voltage gain., Improved frequency response., Lower output impedance., Reduced noise., More linear operation., , Figure 18.1 Simple block diagram of feedback amplifier., , 751
Page 778 :
Af, 18.2 FEEDBACK CONNECTION TYPES, There are four basic ways of connecting the feedback signal. Both voltage and current, can be fed back to the input either in series or parallel. Specifically, there can be:, 1., 2., 3., 4., , Voltage-series feedback (Fig. 18.2a)., Voltage-shunt feedback (Fig. 18.2b)., Current-series feedback (Fig. 18.2c)., Current-shunt feedback (Fig. 18.2d)., , In the list above, voltage refers to connecting the output voltage as input to the, feedback network; current refers to tapping off some output current through the feedback network. Series refers to connecting the feedback signal in series with the input, signal voltage; shunt refers to connecting the feedback signal in shunt (parallel) with, an input current source., Series feedback connections tend to increase the input resistance, while shunt, feedback connections tend to decrease the input resistance. Voltage feedback tends to, decrease the output impedance, while current feedback tends to increase the output, impedance. Typically, higher input and lower output impedances are desired for most, , Figure 18.2 Feedback amplifier types: (a) voltage-series feedback, Af Vo /Vs;, (b) voltage-shunt feedback, Af Vo /Is; (c) current-series feedback, Af Io /Vs; (d), current-shunt feedback, Af Io /Is., , 752, , Chapter 18, , Feedback and Oscillator Circuits
Page 779 :
Af, cascade amplifiers. Both of these are provided using the voltage-series feedback connection. We shall therefore concentrate first on this amplifier connection., , Gain with Feedback, In this section we examine the gain of each of the feedback circuit connections of, Fig. 18.2. The gain without feedback, A, is that of the amplifier stage. With feedback,, , the overall gain of the circuit is reduced by a factor (1 A), as detailed below., A summary of the gain, feedback factor, and gain with feedback of Fig. 18.2 is provided for reference in Table 18.1., TABLE 18.1 Summary of Gain, Feedback, and Gain with Feedback from Fig. 18.2, Voltage-Series, , Voltage-Shunt, , Current-Series, , Current-Shunt, , Gain without feedback, , A, , V, o, Vi, , V, o, Ii, , I, o, Vi, , I, o, Ii, , Feedback, , , , Vf, , Vo, , If, , Vo, , Vf, , Io, , If, , Io, , Gain with feedback, , Af, , V, o, Vs, , V, o, Is, , I, o, Vs, , I, o, Is, , VOLTAGE-SERIES FEEDBACK, Figure 18.2a shows the voltage-series feedback connection with a part of the output voltage fed back in series with the input signal, resulting in an overall gain reduction. If there is no feedback (Vf 0), the voltage gain of the amplifier stage is, V, Vo, A o , Vs, Vi, , (18.1), , If a feedback signal, Vf, is connected in series with the input, then, Vi Vs Vf, Since, , Vo AVi A(Vs Vf) AVs AVf AVs A(Vo), , then, , (1 A)Vo AVs, , so that the overall voltage gain with feedback is, Vo, A, , Af , Vs, 1 A, , (18.2), , Equation (18.2) shows that the gain with feedback is the amplifier gain reduced by, the factor (1 A). This factor will be seen also to affect input and output impedance among other circuit features., VOLTAGE-SHUNT FEEDBACK, The gain with feedback for the network of Fig. 18.2b is, Vo, A Ii, A Ii, A Ii, Af , , , , Is, Ii If, Ii Vo, Ii A Ii, A, Af , 1 A, , (18.3), , 18.2 Feedback Connection Types, , 753
Page 780 :
Af, Input Impedance with Feedback, VOLTAGE-SERIES FEEDBACK, A more detailed voltage-series feedback connection is shown in Fig. 18.3. The input impedance can be determined as follows:, V, Vs Vf, Vs Vo, Vs AVi, Ii i , , , , Zi, Zi, Zi, Zi, Ii Zi Vs AVi, Vs IiZi AVi IiZi AIiZi, V, Zif s Zi (A)Zi Zi(1 A), Ii, , (18.4), , The input impedance with series feedback is seen to be the value of the input impedance without feedback multiplied by the factor (1 A) and applies to both voltage-series (Fig. 18.2a) and current-series (Fig. 18.2c) configurations., , Figure 18.3, , Voltage-series feedback connection., , VOLTAGE-SHUNT FEEDBACK, A more detailed voltage-shunt feedback connection is shown in Fig. 18.4. The input impedance can be determined to be, , Figure 18.4 Voltage-shunt, feedback connection., , 754, , Chapter 18, , Feedback and Oscillator Circuits
Page 781 :
Af, , V, Vi, Vi, Zif i , , Is, Ii If, Ii Vo, V /I i, i , Ii/Ii Vo /Ii, Zi, Zif , 1 A, , (18.5), , This reduced input impedance applies to the voltage-series connection of Fig. 18.2a, and the voltage-shunt connection of Fig. 18.2b., , Output Impedance with Feedback, The output impedance for the connections of Fig. 18.2 are dependent on whether voltage or current feedback is used. For voltage feedback, the output impedance is decreased, while current feedback increases the output impedance., VOLTAGE-SERIES FEEDBACK, The voltage-series feedback circuit of Fig. 18.3 provides sufficient circuit detail, to determine the output impedance with feedback. The output impedance is determined by applying a voltage, V, resulting in a current, I, with Vs shorted out (Vs , 0). The voltage V is then, V IZo AVi, For Vs 0,, , Vi Vf, , so that, , V IZo AVf IZo A(V), , Rewriting the equation as, V AV IZo, allows solving for the output resistance with feedback:, V, Zo, Zof , I, 1 A, , (18.6), , Equation (18.6) shows that with voltage-series feedback the output impedance is reduced from that without feedback by the factor (1 A)., CURRENT-SERIES FEEDBACK, The output impedance with current-series feedback can be determined by applying a signal V to the output with Vs shorted out, resulting in a current I, the ratio of, V to I being the output impedance. Figure 18.5 shows a more detailed connection with, current-series feedback. For the output part of a current-series feedback connection shown, in Fig. 18.5, the resulting output impedance is determined as follows. With Vs 0,, Vi Vf, V, V, V, I AVi AVf AI, Zo, Zo, Zo, Zo(1 A)I V, V, Zof Zo(1 A), I, , (18.7), , 18.2 Feedback Connection Types, , 755
Page 782 :
Af, Ii, , +, , +, , Vs, , Vi, , –, , +, , I o = AVi, Zi, , Zo, , Vo, , RL, , –, , –, , +, Vf = β Io, , β =, , Vf, Io, , Figure 18.5 Current-series, feedback connection., , –, , A summary of the effect of feedback on input and output impedance is provided in, Table 18.2., TABLE 18.2 Effect of Feedback Connection on Input and Output Impedance, Voltage-Series, Zif, , Zi(1 A), , (increased), Zo, Zof, , 1 A, (decreased), , EXAMPLE 18.1, , Current-Series, , Voltage-Shunt, , Current-Shunt, , Zi(1 A), , Zi, , 1 A, (decreased), Zo, , 1 A, (decreased), , Zi, , 1 A, (decreased), , (increased), Zo(1 A), (increased), , Zo(1 A), (increased), , Determine the voltage gain, input, and output impedance with feedback for voltage, series feedback having A 100, Ri 10 k, Ro 20 k for feedback of (a) , 0.1 and (b) 0.5., , Solution, Using Eqs. (18.2), (18.4), and (18.6), we obtain, A, 100, 100, (a) Af 9.09, 1 A, 1 (0.1)(100), 11, Zif Zi (1 A) 10 k (11) 110 k, 20 103, Zo, Zof , 1.82 k, 11, 1 A, 100, A, 100, (b) Af 1.96, 51, 1 A, 1 (0.5)(100), Zif Zi (1 A) 10 k (51) 510 k, Zo, 20 103, Zof , 392.16 , 1 A, 51, Example 18.1 demonstrates the trade-off of gain for improved input and output, resistance. Reducing the gain by a factor of 11 (from 100 to 9.09) is complemented by, a reduced output resistance and increased input resistance by the same factor of 11., Reducing the gain by a factor of 51 provides a gain of only 2 but with input resistance, 756, , Chapter 18, , Feedback and Oscillator Circuits
Page 783 :
increased by the factor of 51 (to over 500 k) and output resistance reduced from, 20 k to under 400 . Feedback offers the designer the choice of trading away some, of the available amplifier gain for other improved circuit features., , Af, , Reduction in Frequency Distortion, For a negative-feedback amplifier having A 1, the gain with feedback is Af 1/., It follows from this that if the feedback network is purely resistive, the gain with feedback is not dependent on frequency even though the basic amplifier gain is frequency, dependent. Practically, the frequency distortion arising because of varying amplifier, gain with frequency is considerably reduced in a negative-voltage feedback amplifier, circuit., , Reduction in Noise and Nonlinear Distortion, Signal feedback tends to hold down the amount of noise signal (such as power-supply, hum) and nonlinear distortion. The factor (1 A) reduces both input noise and, resulting nonlinear distortion for considerable improvement. However, it should be, noted that there is a reduction in overall gain (the price required for the improvement, in circuit performance). If additional stages are used to bring the overall gain up to the, level without feedback, it should be noted that the extra stage(s) might introduce as, much noise back into the system as that reduced by the feedback amplifier. This, problem can be somewhat alleviated by readjusting the gain of the feedback-amplifier, circuit to obtain higher gain while also providing reduced noise signal., , Effect of Negative Feedback on Gain and Bandwidth, In Eq. (18.2), the overall gain with negative feedback is shown to be, A, 1, A, Af , 1 A, A, , , for A, , 1, , As long as A 1, the overall gain is approximately 1/. We should realize that for, a practical amplifier (for single low- and high-frequency breakpoints) the open-loop, gain drops off at high frequencies due to the active device and circuit capacitances., Gain may also drop off at low frequencies for capacitively coupled amplifier stages., Once the open-loop gain A drops low enough and the factor A is no longer much, larger than 1, the conclusion of Eq. (18.2) that Af 1/ no longer holds true., Figure 18.6 shows that the amplifier with negative feedback has more bandwidth, (Bf) than the amplifier without feedback (B). The feedback amplifier has a higher upper 3-dB frequency and smaller lower 3-dB frequency., , Gain, , A, , Ao, , 0.707Afo, Afo, 0.707Ao, f1f f1, , f2 f2f, , Frequency, , B, , Figure 18.6 Effect of negative, feedback on gain and bandwidth., , Bf, , 18.2 Feedback Connection Types, , 757
Page 784 :
Af, It is interesting to note that the use of feedback, while resulting in a lowering of, voltage gain, has provided an increase in B and in the upper 3-dB frequency particularly. In fact, the product of gain and frequency remains the same so that the gain–, bandwidth product of the basic amplifier is the same value for the feedback amplifier. However, since the feedback amplifier has lower gain, the net operation was to, trade gain for bandwidth (we use bandwidth for the upper 3-dB frequency since typically f2 f1)., , Gain Stability with Feedback, In addition to the factor setting a precise gain value, we are also interested in how, stable the feedback amplifier is compared to an amplifier without feedback. Differentiating Eq. (18.2) leads to, , A , |1 A| A , dA, 1, dA, A A A for A, dAf, , 1, , dA, , (18.8), , f, , f, , 1, , (18.9), , f, , , , dAf, This shows that magnitude of the relative change in gain is reduced by the, Af, dA, factor A compared to that without feedback ., A, , , , EXAMPLE 18.2, , If an amplifier with gain of 1000 and feedback of 0.1 has a gain change of, 20% due to temperature, calculate the change in gain of the feedback amplifier., , Solution, Using Eq. (18.9), we get, (20%) 0.2%, A A A , , 0.1(1000), dAf, , 1, , dA, , 1, , f, , The improvement is 100 times. Thus, while the amplifier gain changes from |A| , 1000 by 20%, the gain with feedback changes from |Af | 100 by only 0.2%., , 18.3 PRACTICAL FEEDBACK CIRCUITS, Examples of practical feedback circuits will provide a means of demonstrating the effect feedback has on the various connection types. This section provides only a basic introduction to this topic., , Voltage-Series Feedback, Figure 18.7 shows an FET amplifier stage with voltage-series feedback. A part of the, output signal (Vo) is obtained using a feedback network of resistors R1 and R2. The, feedback voltage Vf is connected in series with the source signal Vs, their difference, being the input signal Vi., Without feedback the amplifier gain is, V, A o gmRL, Vi, where RL is the parallel combination of resistors:, 758, , Chapter 18, , Feedback and Oscillator Circuits, , (18.10)
Page 785 :
Af, , Figure 18.7 FET amplifier stage, with voltage-series feedback., , RL RDRo(R1 R2), , (18.11), , The feedback network provides a feedback factor of, Vf, R2, , Vo, R1 R2, , (18.12), , Using the values of A and above in Eq. (18.2), we find the gain with negative feedback to be, , If A, , gmRL, A, Af , 1 [R2RL/(R1 R2)]gm, 1 A, , (18.13), , 1, R1 R2, , Af , , R2, , (18.14), , 1, we have, , EXAMPLE 18.3, Calculate the gain without and with feedback for the FET amplifier circuit of Fig., 18.7 and the following circuit values: R1 80 k, R2 20 k, Ro 10 k, RD , 10 k, and gm 4000 S., , Solution, Ro RD, 10 k (10 k), RL , 5 k, Ro RD, 10 k 10 k, Neglecting 100 k resistance of R1 and R2 in series, A gmRL (4000 106 S)(5 k) 20, The feedback factor is, R2, 20 k, , 0.2, R1 R2, 80 k 20 k, The gain with feedback is, A, 20, 20, Af 4, 1 A, 1 (0.2)(20), 5, , 18.3, , Practical Feedback Circuits, , 759
Page 786 :
Af, Figure 18.8 shows a voltage-series feedback connection using an op-amp. The gain, of the op-amp, A, without feedback, is reduced by the feedback factor, R2, , R1 R2, , (18.15), , Figure 18.8 Voltage-series, feedback in an op-amp connection., , EXAMPLE 18.4, , Calculate the amplifier gain of the circuit of Fig. 18.8 for op-amp gain A 100,000, and resistances R1 1.8 k and R2 200 ., , Solution, R2, 200 , , 0.1, R1 R2, 200 1.8 k, A, 100,000, Af , 1 A, 1 (0.1)(100,000), 100,000, 9.999, 10,001, Note that since A, , 1,, 1, 1, Af 10, , 0.1, , The emitter-follower circuit of Fig. 18.9 provides voltage-series feedback. The, signal voltage, Vs, is the input voltage, Vi. The output voltage, Vo, is also the feed-, , Figure 18.9 Voltage-series, feedback circuit (emitter-follower)., , 760, , Chapter 18, , Feedback and Oscillator Circuits
Page 787 :
Af, back voltage in series with the input voltage. The amplifier, as shown in Fig. 18.9,, provides the operation with feedback. The operation of the circuit without feedback, provides Vf 0, so that, hfeIbRE, hfeRE(Vs/hie), hfeRE, Vo, , A , Vs, Vs, Vs, hi e, Vf, 1, Vo, , and, , The operation with feedback then provides that, hfeRE/hie, Vo, A, Af , , Vs, 1 A, 1 (1)(hfeRE/hie), , For hfeRE, , hie,, , hfeRE, , hie hfeRE, Af 1, , Current-Series Feedback, Another feedback technique is to sample the output current (Io) and return a proportional voltage in series with the input. While stabilizing the amplifier gain, the current-series feedback connection increases input resistance., Figure 18.10 shows a single transistor amplifier stage. Since the emitter of this, stage has an unbypassed emitter, it effectively has current-series feedback. The current through resistor RE results in a feedback voltage that opposes the source signal, applied so that the output voltage Vo is reduced. To remove the current-series feedback, the emitter resistor must be either removed or bypassed by a capacitor (as is, usually done)., , Figure 18.10 Transistor amplifier with unbypassed emitter resistor (RE) for current-series feedback: (a) amplifier circuit; (b) ac equivalent circuit without feedback., , 18.3, , Practical Feedback Circuits, , 761
Page 788 :
Af, WITHOUT FEEDBACK, Referring to the basic format of Fig. 18.2a and summarized in Table 18.1, we have, Ibhfe, hfe, I, A o , Vi, Ibhie RE, hie RE, , (18.16), , Vf, I RE, o, RE, Io, Io, , (18.17), , The input and output impedances are, Zi RB(hie RE) hie RE, , (18.18), , Zo RC, , (18.19), , WITH FEEDBACK, hfe, hfe/hie, I, A, Af o , , h, fe, Vs, 1 A, hie hfeRE, 1 (RE) , hie RE, , , , , , (18.20), , The input and output impedance is calculated as specified in Table 18.2., , , , , , (18.21), , , , , , (18.22), , hfeRE, Zif Zi (1 A) hie 1 hie hfeRE, hie, hfeRE, Zof Zo(1 A) RC 1 , hi e, The voltage gain (A) with feedback is, hfeRC, Vo, IoRC, I, Avf , , o RC Af RC , Vs, Vs, Vs, hie hfeRE, , , , EXAMPLE 18.5, , (18.23), , Calculate the voltage gain of the circuit of Fig. 18.11., , Figure 18.11 BJT amplifier with, current-series feedback for, Example 18.5., , Solution, Without feedback,, hfe, I, 120, A o 0.085, Vi, hie RE, 900 510, 762, , Chapter 18, , Feedback and Oscillator Circuits
Page 789 :
Af, , Vf, RE 510, Io, The factor (1 A) is then, 1 A 1 (0.085)(510) 44.35, The gain with feedback is then, I, A, 0.085, Af o 1.92 103, Vs, 1 A, 44.35, and the voltage gain with feedback Avf is, V, Avf o Af RC (1.92 103)(2.2 103) 4.2, Vs, Without feedback (RE 0), the voltage gain is, RC, 2.2 103, Av , 293.3, re, 7.5, , Voltage-Shunt Feedback, The constant-gain op-amp circuit of Fig. 18.12a provides voltage-shunt feedback. Referring to Fig. 18.2b and Table 18.1 and the op-amp ideal characteristics Ii 0, Vi , 0, and voltage gain of infinity, we have, Vo, A , , Ii, , (18.24), , If, 1, , Vo, Ro, , (18.25), , Vo, Vo, A, 1, Af , , Ro, Is, Ii, 1 A, , , (18.26), , The gain with feedback is then, , This is a transfer resistance gain. The more usual gain is the voltage gain with feedback,, Vo Is, 1, R, Avf , (Ro) o, Is V1, R1, R1, , (18.27), , The circuit of Fig. 18.13 is a voltage-shunt feedback amplifier using an FET with, Ro, Ro, , If, , –, , R1, V1, , –, , V1, Is =, R1, , Vo, , Ii, , +, , ∞, , Vo, , +, (b), (a), , Figure 18.12 Voltage-shunt negative feedback amplifier: (a) constant-gain circuit; (b) equivalent circuit., , 18.3, , Practical Feedback Circuits, , 763
Page 790 :
Af, , no feedback, Vf 0., V, A o gmRDRS, Ii, , (18.28), , If, 1, , Vo, RF, , (18.29), , The feedback is, , With feedback, the gain of the circuit is, gmRDRS, V, A, Af o , 1 (1/RF)(gmRDRS), Is, 1 A, gmRDRSRF, , , RF gmRDRS, , (18.30), , The voltage gain of the circuit with feedback is then, gmRDRSRF, 1, V Is, Avf o , , , RF gmRDRS RS, Is Vs, , , , gmRDRF, RF, , (gmRD) , (18.31), RF gmRDRS, RF gmRDRS, Calculate the voltage gain with and without feedback for the circuit of Fig. 18.13a, , Figure 18.13 Voltage-shunt feedback amplifier using an FET: (a) circuit; (b), equivalent circuit., , EXAMPLE 18.6, , with values of gm 5 mS, RD 5.1 k, RS 1 k, and RF 20 k., , Solution, Without feedback, the voltage gain is, Av gm RD (5 103)(5.1 103) 25.5, With feedback the gain is reduced to, 764, , Chapter 18, , Feedback and Oscillator Circuits
Page 791 :
Af, , RF, Avf (gmRD) , RF gmRDRS, 20 103, (25.5) , 3, (20 10 ) (5 103)(5.1 103)(1 103), 25.5(0.44) 11.2, , 18.4 FEEDBACK AMPLIFIER—PHASE AND, FREQUENCY CONSIDERATIONS, So far we have considered the operation of a feedback amplifier in which the feedback signal was opposite to the input signal—negative feedback. In any practical circuit this condition occurs only for some mid-frequency range of operation. We know, that an amplifier gain will change with frequency, dropping off at high frequencies, from the mid-frequency value. In addition, the phase shift of an amplifier will also, change with frequency., If, as the frequency increases, the phase shift changes then some of the feedback, signal will add to the input signal. It is then possible for the amplifier to break into, oscillations due to positive feedback. If the amplifier oscillates at some low or high, frequency, it is no longer useful as an amplifier. Proper feedback-amplifier design requires that the circuit be stable at all frequencies, not merely those in the range of interest. Otherwise, a transient disturbance could cause a seemingly stable amplifier to, suddenly start oscillating., , Nyquist Criterion, In judging the stability of a feedback amplifier, as a function of frequency, the A, product and the phase shift between input and output are the determining factors. One, of the most popular techniques used to investigate stability is the Nyquist method. A, Nyquist diagram is used to plot gain and phase shift as a function of frequency on a, complex plane. The Nyquist plot, in effect, combines the two Bode plots of gain versus frequency and phase shift versus frequency on a single plot. A Nyquist plot is, used to quickly show whether an amplifier is stable for all frequencies and how stable the amplifier is relative to some gain or phase-shift criteria., As a start, consider the complex plane shown in Fig. 18.14. A few points of various gain (A) values are shown at a few different phase-shift angles. By using the, positive real axis as reference (0°), a magnitude of A 2 is shown at a phase shift, of 0° at point 1. Additionally, a magnitude of A 3 at a phase shift of 135° is, , Figure 18.14 Complex plane, showing typical gain-phase points., , 18.4, , Feedback Amplifier—Phase and Frequency Considerations, , 765
Page 792 :
Af, , shown at point 2 and a magnitude/phase of A 1 at 180° is shown at point 3. Thus, points on this plot can represent both gain magnitude of A and phase shift. If the, points representing gain and phase shift for an amplifier circuit are plotted at increasing frequency, then a Nyquist plot is obtained as shown by the plot in Fig. 18.15., At the origin, the gain is 0 at a frequency of 0 (for RC-type coupling). At increasing, frequency, points f1, f2, and f3 and the phase shift increased, as did the magnitude of, A. At a representative frequency f4, the value of A is the vector length from the origin to point f4 and the phase shift is the angle . At a frequency f5, the phase shift is, 180°. At higher frequencies, the gain is shown to decrease back to 0., The Nyquist criterion for stability can be stated as follows:, The amplifier is unstable if the Nyquist curve plotted encloses (encircles) the, , Figure 18.15, , Nyquist plot., , 1 point, and it is stable otherwise., An example of the Nyquist criterion is demonstrated by the curves in Fig. 18.16., The Nyquist plot in Fig. 18.16a is stable since it does not encircle the 1 point,, whereas that shown in Fig. 18.16b is unstable since the curve does encircle the 1, point. Keep in mind that encircling the 1 point means that at a phase shift of 180°, the loop gain (A) is greater than 1; therefore, the feedback signal is in phase with, the input and large enough to result in a larger input signal than that applied, with the, result that oscillation occurs., , Gain and Phase Margins, , Figure 18.16 Nyquist plots, showing stability conditions;, (a) stable; (b) unstable., , From the Nyquist criterion, we know that a feedback amplifier is stable if the loop, gain (A) is less than unity (0 dB) when its phase angle is 180°. We can additionally, determine some margins of stability to indicate how close to instability the amplifier, is. That is, if the gain (A) is less than unity but, say, 0.95 in value, this would not, be as relatively stable as another amplifier having, say, (A) 0.7 (both measured at, 180°). Of course, amplifiers with loop gains 0.95 and 0.7 are both stable, but one is, 766, , Chapter 18, , Feedback and Oscillator Circuits
Page 793 :
Af, closer to instability, if the loop gain increases, than the other. We can define the, following terms:, Gain margin (GM) is defined as the negative of the value of |A| in decibels at the, frequency at which the phase angle is 180°. Thus, 0 dB, equal to a value of A 1,, is on the border of stability and any negative decibel value is stable. The GM may be, evaluated in decibels from the curve of Fig. 18.17., Phase margin (PM) is defined as the angle of 180° minus the magnitude of the, angle at which the value |A| is unity (0 dB). The PM may also be evaluated directly, from the curve of Fig. 18.17., , Figure 18.17, , Bode plots showing gain and phase margins., , 18.5 OSCILLATOR OPERATION, The use of positive feedback that results in a feedback amplifier having closed-loop, gain |Af | greater than 1 and satisfies the phase conditions will result in operation as, an oscillator circuit. An oscillator circuit then provides a varying output signal. If the, output signal varies sinusoidally, the circuit is referred to as a sinusoidal oscillator., If the output voltage rises quickly to one voltage level and later drops quickly to another voltage level, the circuit is generally referred to as a pulse or square-wave oscillator., To understand how a feedback circuit performs as an oscillator, consider the feedback circuit of Fig. 18.18. When the switch at the amplifier input is open, no oscillation occurs. Consider that we have a fictitious voltage at the amplifier input (Vi)., This results in an output voltage Vo AVi after the amplifier stage and in a voltage, Vf (AVi) after the feedback stage. Thus, we have a feedback voltage Vf AVi,, where A is referred to as the loop gain. If the circuits of the base amplifier and feedback network provide A of a correct magnitude and phase, Vf can be made equal to, 18.5, , Oscillator Operation, , 767
Page 794 :
Af, , Figure 18.18, , Feedback circuit used as an oscillator., , Vi. Then, when the switch is closed and fictitious voltage Vi is removed, the circuit, will continue operating since the feedback voltage is sufficient to drive the amplifier, and feedback circuits resulting in a proper input voltage to sustain the loop operation., The output waveform will still exist after the switch is closed if the condition, , A 1, , (18.32), , is met. This is known as the Barkhausen criterion for oscillation., In reality, no input signal is needed to start the oscillator going. Only the condition A 1 must be satisfied for self-sustained oscillations to result. In practice, A, is made greater than 1 and the system is started oscillating by amplifying noise voltage, which is always present. Saturation factors in the practical circuit provide an “average” value of A of 1. The resulting waveforms are never exactly sinusoidal. However, the closer the value A is to exactly 1, the more nearly sinusoidal is the waveform., Figure 18.19 shows how the noise signal results in a buildup of a steady-state oscillation condition., , Figure 18.19, , Buildup of steady-state oscillations., , Another way of seeing how the feedback circuit provides operation as an oscillator is obtained by noting the denominator in the basic feedback equation (18.2), Af , A/(1 A). When A 1 or magnitude 1 at a phase angle of 180°, the denominator becomes 0 and the gain with feedback, Af, becomes infinite. Thus, an infinitesimal signal (noise voltage) can provide a measurable output voltage, and the circuit, acts as an oscillator even without an input signal., The remainder of this chapter is devoted to various oscillator circuits that use a, variety of components. Practical considerations are included so that workable circuits, in each of the various cases are discussed., 768, , Chapter 18, , Feedback and Oscillator Circuits
Page 795 :
Af, 18.6 PHASE-SHIFT OSCILLATOR, An example of an oscillator circuit that follows the basic development of a feedback, circuit is the phase-shift oscillator. An idealized version of this circuit is shown in, Fig. 18.20. Recall that the requirements for oscillation are that the loop gain, A, is, greater than unity and that the phase shift around the feedback network is 180° (providing positive feedback). In the present idealization, we are considering the feedback, network to be driven by a perfect source (zero source impedance) and the output of, the feedback network to be connected into a perfect load (infinite load impedance)., The idealized case will allow development of the theory behind the operation of the, phase-shift oscillator. Practical circuit versions will then be considered., , Figure 18.20 Idealized, phase-shift oscillator., , Concentrating our attention on the phase-shift network, we are interested in the, attenuation of the network at the frequency at which the phase shift is exactly 180°., Using classical network analysis, we find that, 1, f , 2 RC6, , (18.33), , 1, , 29, , (18.34), , and the phase shift is 180°., For the loop gain A to be greater than unity, the gain of the amplifier stage must, be greater than 1/ or 29:, A 29, , (18.35), , When considering the operation of the feedback network, one might naively select the values of R and C to provide (at a specific frequency) 60°-phase shift per section for three sections, resulting in a 180° phase shift, as desired. This, however, is, not the case, since each section of the RC in the feedback network loads down the, previous one. The net result that the total phase shift be 180° is all that is important., The frequency given by Eq. (18.33) is that at which the total phase shift is 180°. If, one measured the phase shift per RC section, each section would not provide the same, phase shift (although the overall phase shift is 180°). If it were desired to obtain exactly a 60° phase shift for each of three stages, then emitter-follower stages would be, needed for each RC section to prevent each from being loaded from the following, circuit., 18.6 Phase-Shift Oscillator, , 769
Page 796 :
Af, FET Phase-Shift Oscillator, A practical version of a phase-shift oscillator circuit is shown in Fig. 18.21a. The circuit is drawn to show clearly the amplifier and feedback network. The amplifier stage, is self-biased with a capacitor bypassed source resistor RS and a drain bias resistor, RD. The FET device parameters of interest are gm and rd. From FET amplifier theory, the amplifier gain magnitude is calculated from, A, , gmRL, , (18.36), , where RL in this case is the parallel resistance of RD and rd, R rd, RL D, RD rd, , (18.37), , We shall assume as a very good approximation that the input impedance of the FET, amplifier stage is infinite. This assumption is valid as long as the oscillator operating, frequency is low enough so that FET capacitive impedances can be neglected. The, output impedance of the amplifier stage given by RL should also be small compared, to the impedance seen looking into the feedback network so that no attenuation due, to loading occurs. In practice, these considerations are not always negligible, and the, amplifier stage gain is then selected somewhat larger than the needed factor of 29 to, assure oscillator action., , Figure 18.21, , EXAMPLE 18.7, , 770, , Practical phase-shift oscillator circuits: (a) FET version; (b) BJT version., , It is desired to design a phase-shift oscillator (as in Fig. 18.21a) using an FET having gm 5000 S, rd 40 k, and feedback circuit value of R 10 k. Select the, value of C for oscillator operation at 1 kHz and RD for A 29 to ensure oscillator, action., Chapter 18, , Feedback and Oscillator Circuits
Page 797 :
Af, Solution, Equation (18.33) is used to solve for the capacitor value. Since f 1/2 RC6, we, can solve for C:, 1, 1, C , 6.5 nF, 3, (6.28)(10 10 )(1 103)(2.45), 2 Rf 6, , Using Eq. (18.36), we solve for RL to provide a gain of, say, A 40 (this allows, for some loading between RL and the feedback network input impedance):, A, , gmRL, , A, 40, RL , 8 k, gm, 5000 106, , Using Eq. (18.37), we solve for RD 10 k., , Transistor Phase-Shift Oscillator, If a transistor is used as the active element of the amplifier stage, the output of the, feedback network is loaded appreciably by the relatively low input resistance (hie) of, the transistor. Of course, an emitter-follower input stage followed by a common-emitter amplifier stage could be used. If a single transistor stage is desired, however, the, use of voltage-shunt feedback (as shown in Fig. 18.21b) is more suitable. In this connection, the feedback signal is coupled through the feedback resistor R in series with, the amplifier stage input resistance (Ri)., Analysis of the ac circuit provides the following equation for the resulting oscillator frequency:, 1, 1, , f , 2 RC 6, (R, 4, /R), C, , (18.38), , For the loop gain to be greater than unity, the requirement on the current gain of the, transistor is found to be, RC, R, hfe 23 29 4 , R, RC, , (18.39), , IC Phase-Shift Oscillator, As IC circuits have become more popular, they have been adapted to operate in oscillator circuits. One need buy only an op-amp to obtain an amplifier circuit of stabilized gain setting and incorporate some means of signal feedback to produce an oscillator circuit. For example, a phase-shift oscillator is shown in Fig. 18.22. The output, , Figure 18.22 Phase-shift, oscillator using op-amp., , 18.6 Phase-Shift Oscillator, , 771
Page 798 :
Af, of the op-amp is fed to a three-stage RC network, which provides the needed 180° of, phase shift (at an attenuation factor of 1/29). If the op-amp provides gain (set by resistors Ri and Rf) of greater than 29, a loop gain greater than unity results and the circuit acts as an oscillator [oscillator frequency is given by Eq. (18.33)]., , 18.7 WIEN BRIDGE OSCILLATOR, A practical oscillator circuit uses an op-amp and RC bridge circuit, with the oscillator frequency set by the R and C components. Figure 18.23 shows a basic version of, a Wien bridge oscillator circuit. Note the basic bridge connection. Resistors R1 and, R2 and capacitors C1 and C2 form the frequency-adjustment elements, while resistors, R3 and R4 form part of the feedback path. The op-amp output is connected as the, bridge input at points a and c. The bridge circuit output at points b and d is the input to the op-amp., , Figure 18.23, , Wien bridge oscillator circuit using op-amp amplifier., , Neglecting loading effects of the op-amp input and output impedances, the analysis of the bridge circuit results in, , and, , R, R1, C, 3 , 2, R4, R2, C1, , (18.40), , 1, fo , 2 , R, , 1C, 1R, 2C2, , (18.41), , If, in particular, the values are R1 R2 R and C1 C2 C, the resulting oscillator frequency is, , and, , 1, fo , 2 RC, , (18.42), , R, 3 2, R4, , (18.43), , Thus a ratio of R3 to R4 greater than 2 will provide sufficient loop gain for the circuit to oscillate at the frequency calculated using Eq. (18.42)., 772, , Chapter 18, , Feedback and Oscillator Circuits
Page 799 :
Af, Calculate the resonant frequency of the Wien bridge oscillator of Fig. 18.24., , Figure 18.24, , EXAMPLE 18.8, , Wien bridge oscillator circuit for Example 18.8., , Solution, Using Eq. (18.42) yields, 1, 1, fo , 3120.7 Hz, 2 RC, 2 (51 103)(0.001 106), , Design the RC elements of a Wien bridge oscillator as in Fig. 18.24 for operation at, fo 10 kHz., , EXAMPLE 18.9, , Solution, Using equal values of R and C we can select R 100 k and calculate the required, value of C using Eq. (18.42):, 1, 109, 1, C , 3, 3 159 pF, 2 foR, 6.28(10 10 )(100 10 ), 6.28, We can use R3 300 k and R4 100 k to provide a ratio R3/R4 greater than 2, for oscillation to take place., , 18.8 TUNED OSCILLATOR CIRCUIT, Tuned-Input, Tuned-Output Oscillator Circuits, A variety of circuits can be built using that shown in Fig. 18.25 by providing tuning, in both the input and output sections of the circuit. Analysis of the circuit of Fig., 18.25 reveals that the following types of oscillators are obtained when the reactance, elements are as designated:, 18.8, , Tuned Oscillator Circuit, , 773
Page 800 :
Af, , Figure 18.25 Basic configuration, of resonant circuit oscillator., , Reactance Element, Oscillator Type, , X1, , X2, , X3, , Colpitts oscillator, Hartley oscillator, Tuned input, tuned output, , C, L, LC, , C, L, LC, , L, C, —, , Colpitts Oscillator, FET COLPITTS OSCILLATOR, A practical version of an FET Colpitts oscillator is shown in Fig. 18.26. The circuit is basically the same form as shown in Fig. 18.25 with the addition of the components needed for dc bias of the FET amplifier. The oscillator frequency can be found, to be, , where, , 1, fo , 2 L, C, , eq, , (18.44), , C C2, Ceq 1, C1 C2, , (18.45), , Figure 18.26, oscillator., , 774, , Chapter 18, , Feedback and Oscillator Circuits, , FET Colpitts
Page 801 :
Af, TRANSISTOR COLPITTS OSCILLATOR, A transistor Colpitts oscillator circuit can be made as shown in Fig. 18.27. The, circuit frequency of oscillation is given by Eq. (18.44)., , Figure 18.27, oscillator., , Transistor Colpitts, , IC COLPITTS OSCILLATOR, An op-amp Colpitts oscillator circuit is shown in Fig. 18.28. Again, the op-amp, provides the basic amplification needed while the oscillator frequency is set by an LC, feedback network of a Colpitts configuration. The oscillator frequency is given by Eq., (18.44)., , Figure 18.28, oscillator., , Op-amp Colpitts, , Hartley Oscillator, If the elements in the basic resonant circuit of Fig. 18.25 are X1 and X2 (inductors), and X3 (capacitor), the circuit is a Hartley oscillator., 18.8, , Tuned Oscillator Circuit, , 775
Page 802 :
Af, FET HARTLEY OSCILLATOR, An FET Hartley oscillator circuit is shown in Fig. 18.29. The circuit is drawn so, that the feedback network conforms to the form shown in the basic resonant circuit, (Fig. 18.25). Note, however, that inductors L1 and L2 have a mutual coupling, M,, which must be taken into account in determining the equivalent inductance for the, resonant tank circuit. The circuit frequency of oscillation is then given approximately by, , with, , 1, fo , 2 , Leq, , C, , (18.46), , Leq L1 L2 2M, , (18.47), , TRANSISTOR HARTLEY OSCILLATOR, Figure 18.30 shows a transistor Hartley oscillator circuit. The circuit operates at, a frequency given by Eq. (18.46)., , Figure 18.29, , FET Hartley oscillator., , Figure 18.30, , Transistor Hartley oscillator circuit., , 18.9 CRYSTAL OSCILLATOR, A crystal oscillator is basically a tuned-circuit oscillator using a piezoelectric crystal, as a resonant tank circuit. The crystal (usually quartz) has a greater stability in holding constant at whatever frequency the crystal is originally cut to operate. Crystal oscillators are used whenever great stability is required, such as in communication transmitters and receivers., 776, , Chapter 18, , Feedback and Oscillator Circuits
Page 803 :
Af, Characteristics of a Quartz Crystal, A quartz crystal (one of a number of crystal types) exhibits the property that when, mechanical stress is applied across the faces of the crystal, a difference of potential, develops across opposite faces of the crystal. This property of a crystal is called the, piezoelectric effect. Similarly, a voltage applied across one set of faces of the crystal, causes mechanical distortion in the crystal shape., When alternating voltage is applied to a crystal, mechanical vibrations are set, up—these vibrations having a natural resonant frequency dependent on the crystal., Although the crystal has electromechanical resonance, we can represent the crystal, action by an equivalent electrical resonant circuit as shown in Fig. 18.31. The inductor L and capacitor C represent electrical equivalents of crystal mass and compliance,, while resistance R is an electrical equivalent of the crystal structure’s internal friction. The shunt capacitance CM represents the capacitance due to mechanical mounting of the crystal. Because the crystal losses, represented by R, are small, the equivalent crystal Q (quality factor) is high—typically 20,000. Values of Q up to almost, 106 can be achieved by using crystals., The crystal as represented by the equivalent electrical circuit of Fig. 18.31 can, have two resonant frequencies. One resonant condition occurs when the reactances of, the series RLC leg are equal (and opposite). For this condition, the series-resonant, impedance is very low (equal to R). The other resonant condition occurs at a higher, frequency when the reactance of the series-resonant leg equals the reactance of capacitor CM. This is a parallel resonance or antiresonance condition of the crystal. At, this frequency, the crystal offers a very high impedance to the external circuit. The, impedance versus frequency of the crystal is shown in Fig. 18.32. In order to use the, crystal properly, it must be connected in a circuit so that its low impedance in the series-resonant operating mode or high impedance in the antiresonant operating mode, is selected., , Figure 18.31 Electrical equivalent, circuit of a crystal., , Figure 18.32 Crystal impedance, versus frequency., , Series-Resonant Circuits, To excite a crystal for operation in the series-resonant mode, it may be connected as, a series element in a feedback path. At the series-resonant frequency of the crystal,, its impedance is smallest and the amount of (positive) feedback is largest. A typical, transistor circuit is shown in Fig. 18.33. Resistors R1, R2, and RE provide a voltagedivider stabilized dc bias circuit. Capacitor CE provides ac bypass of the emitter re18.9 Crystal Oscillator, , 777
Page 804 :
Af, , Figure 18.33 Crystal-controlled oscillator using crystal in series-feedback path:, (a) BJT circuit; (b) FET circuit., , sistor, and the RFC coil provides for dc bias while decoupling any ac signal on the, power lines from affecting the output signal. The voltage feedback from collector to, base is a maximum when the crystal impedance is minimum (in series-resonant mode)., The coupling capacitor CC has negligible impedance at the circuit operating frequency, but blocks any dc between collector and base., The resulting circuit frequency of oscillation is set, then, by the series-resonant, frequency of the crystal. Changes in supply voltage, transistor device parameters, and, so on have no effect on the circuit operating frequency, which is held stabilized by, the crystal. The circuit frequency stability is set by the crystal frequency stability,, which is good., , Parallel-Resonant Circuits, Since the parallel-resonant impedance of a crystal is a maximum value, it is connected, in shunt. At the parallel-resonant operating frequency, a crystal appears as an inductive reactance of largest value. Figure 18.34 shows a crystal connected as the induc-, , Figure 18.34 Crystal-controlled, oscillator operating in parallel-resonant, mode., , 778, , Chapter 18, , Feedback and Oscillator Circuits
Page 805 :
Af, tor element in a modified Colpitts circuit. The basic dc bias circuit should be evident., Maximum voltage is developed across the crystal at its parallel-resonant frequency., The voltage is coupled to the emitter by a capacitor voltage divider—capacitors C1, and C2., A Miller crystal-controlled oscillator circuit is shown in Fig. 18.35. A tuned LC, circuit in the drain section is adjusted near the crystal parallel-resonant frequency. The, maximum gate–source signal occurs at the crystal antiresonant frequency controlling, the circuit operating frequency., , Figure 18.35 Miller crystal-controlled oscillator., , Crystal Oscillator, An op-amp can be used in a crystal oscillator as shown in Fig. 18.36. The crystal is, connected in the series-resonant path and operates at the crystal series-resonant frequency. The present circuit has a high gain so that an output square-wave signal results as shown in the figure. A pair of Zener diodes is shown at the output to provide, output amplitude at exactly the Zener voltage (VZ)., , Figure 18.36 Crystal oscillator using op-amp., , 18.9 Crystal Oscillator, , 779
Page 806 :
Af, 18.10 UNIJUNCTION OSCILLATOR, A particular device, the unijunction transistor can be used in a single-stage oscillator, circuit to provide a pulse signal suitable for digital-circuit applications. The unijunction transistor can be used in what is called a relaxation oscillator as shown by the, basic circuit of Fig. 18.37. Resistor RT and capacitor CT are the timing components, that set the circuit oscillating rate. The oscillating frequency may be calculated using, Eq. (18.48), which includes the unijunction transistor intrinsic stand-off ratio as a, factor (in addition to RT and CT) in the oscillator operating frequency., , Figure 18.37 Basic unijunction, oscillator circuit., , 1, fo , RT CT ln[1/(1 )], , (18.48), , Typically, a unijunction transistor has a stand-off ratio from 0.4 to 0.6. Using a value, of 0.5, we get, 1.44, 1.44, 1, fo , RT CT ln[1/(1 0.5)], RT CT ln 2, RT C T, 1.5, , RT CT, , (18.49), , Capacitor CT is charged through resistor RT toward supply voltage VBB. As long as, the capacitor voltage VE is below a stand-off voltage (VP) set by the voltage across, B1 B2 and the transistor stand-off ratio , VP VB1VB2 VD, , (18.50), , the unijunction emitter lead appears as an open circuit. When the emitter voltage, across capacitor CT exceeds this value (VP), the unijunction circuit fires, discharging, the capacitor, after which a new charge cycle begins. When the unijunction fires, a, voltage rise is developed across R1 and a voltage drop is developed across R2 as shown, in Fig. 18.38. The signal at the emitter is a sawtooth voltage waveform that at base 1, is a positive-going pulse and at base 2 is a negative-going pulse. A few circuit variations of the unijunction oscillator are provided in Fig. 18.39., 780, , Chapter 18, , Feedback and Oscillator Circuits
Page 808 :
Af, PROBLEMS, , § 18.2 Feedback Connection Types, 1., , Calculate the gain of a negative-feedback amplifier having A 2000 and 1/10., , 2., , If the gain of an amplifier changes from a value of 1000 by 10%, calculate the gain change, if the amplifier is used in a feedback circuit having 1/20., , 3., , Calculate the gain, input, and output impedances of a voltage-series feedback amplifier having A 300, Ri 1.5 k, Ro 50 k, and 1/15., , § 18.3 Practical Feedback Circuits, * 4. Calculate the gain with and without feedback for an FET amplifier as in Fig. 18.7 for circuit, values R1 800 k, R2 200 , Ro 40 k, RD 8 k, and gm 5000 S., 5., , For a circuit as in Fig. 18.11 and the following circuit values, calculate the circuit gain and, the input and output impedances with and without feedback: RB 600 k, RE 1.2 k, RC, 4.7 k, and 75. Use VCC 16 V., , § 18.6 Phase-Shift Oscillator, 6., , An FET phase-shift oscillator having gm 6000 S, rd 36 k, and feedback resistor R , 12 k is to operate at 2.5 kHz. Select C for specified oscillator operation., , 7., , Calculate the operating frequency of a BJT phase-shift oscillator as in Fig. 18.21b for R 6, k, C 1500 pF, and RC 18 k., , § 18.7, 8., , Wien Bridge Oscillator, , Calculate the frequency of a Wien bridge oscillator circuit (as in Fig. 18.23) when R 10 k, and C 2400 pF., , § 18.8 Tuned Oscillator Circuit, 9., , For an FET Colpitts oscillator as in Fig. 18.26 and the following circuit values determine the, circuit oscillation frequency: C1 750 pF, C2 2500 pF, and L 40 H., , 10., , For the transistor Colpitts oscillator of Fig. 18.27 and the following circuit values, calculate, the oscillation frequency: L 100 H, LRFC 0.5 mH, C1 0.005 F, C2 0.01 F, and, CC 10 F., , 11., , Calculate the oscillator frequency for an FET Hartley oscillator as in Fig. 18.29 for the following circuit values: C 250 pF, L1 1.5 mH, L 2 1.5 mH, and M 0.5 mH., , 12., , Calculate the oscillation frequency for the transistor Hartley circuit of Fig. 18.30 and the following circuit values: LRFC 0.5 mH, L1 750 H, L2 750 H, M 150 H, and C , 150 pF., , § 18.9 Crystal Oscillator, 13., , Draw circuit diagrams of (a) a series-operated crystal oscillator and (b) a shunt-excited crystal oscillator., , § 18.10 Unijunction Oscillator, 14., , Design a unijunction oscillator circuit for operation at (a) 1 kHz and (b) 150 kHz., , *, , Please Note: Asterisks indicate more difficult problems., , 782, , Chapter 18, , Feedback and Oscillator Circuits
Page 809 :
V.R., , CHAPTER, , Power Supplies, (Voltage Regulators), , 19, , 19.1 INTRODUCTION, The present chapter introduces the operation of power supply circuits built using filters, rectifiers, and then voltage regulators. (Refer to Chapter 2 for the initial description of diode rectifier circuits.) Starting with an ac voltage, a steady dc voltage, is obtained by rectifying the ac voltage, then filtering to a dc level and, finally, regulating to obtain a desired fixed dc voltage. The regulation is usually obtained from an, IC voltage regulator unit, which takes a dc voltage and provides a somewhat lower, dc voltage, which remains the same even if the input dc voltage varies or the output, load connected to the dc voltage changes., A block diagram containing the parts of a typical power supply and the voltage, at various points in the unit is shown in Fig. 19.1. The ac voltage, typically 120 V, rms, is connected to a transformer, which steps that ac voltage down to the level for, the desired dc output. A diode rectifier then provides a full-wave rectified voltage that, is initially filtered by a simple capacitor filter to produce a dc voltage. This resulting, dc voltage usually has some ripple or ac voltage variation. A regulator circuit can use, this dc input to provide a dc voltage that not only has much less ripple voltage but, also remains the same dc value even if the input dc voltage varies somewhat or the, load connected to the output dc voltage changes. This voltage regulation is usually, obtained using one of a number of popular voltage regulator IC units., , Figure 19.1 Block diagram showing parts of a power supply., , 19.2 GENERAL FILTER CONSIDERATIONS, A rectifier circuit is necessary to convert a signal having zero average value into one, that has a nonzero average. The output resulting from a rectifier is a pulsating dc voltage and not yet suitable as a battery replacement. Such a voltage could be used in,, 783
Page 810 :
V.R., , say, a battery charger, where the average dc voltage is large enough to provide a charging current for the battery. For dc supply voltages, as those used in a radio, stereo, system, computer, and so on, the pulsating dc voltage from a rectifier is not good, enough. A filter circuit is necessary to provide a steadier dc voltage., , Filter Voltage Regulation and Ripple Voltage, Before going into the details of a filter circuit, it would be appropriate to consider the, usual methods of rating filter circuits so that we can compare a circuit’s effectiveness, as a filter. Figure 19.2 shows a typical filter output voltage, which will be used to define some of the signal factors. The filtered output of Fig. 19.2 has a dc value and, some ac variation (ripple). Although a battery has essentially a constant or dc output, voltage, the dc voltage derived from an ac source signal by rectifying and filtering, will have some ac variation (ripple). The smaller the ac variation with respect to the, dc level, the better the filter circuit’s operation., , Figure 19.2 Filter voltage, waveform showing dc and ripple, voltages., , Consider measuring the output voltage of a filter circuit using a dc voltmeter and, an ac (rms) voltmeter. The dc voltmeter will read only the average or dc level of the, output voltage. The ac (rms) meter will read only the rms value of the ac component, of the output voltage (assuming the ac signal is coupled through a capacitor to block, out the dc level)., Definition: Ripple, ripple voltage (rms), Vr(rms), r , 100%, dc voltage, Vdc, , EXAMPLE 19.1, , (19.1), , Using a dc and ac voltmeter to measure the output signal from a filter circuit, we obtain readings of 25 V dc and 1.5 V rms. Calculate the ripple of the filter output voltage., , Solution, Vr(rms), 1.5 V, r, 100% 100% 6%, Vdc, 25 V, , VOLTAGE REGULATION, Another factor of importance in a power supply is the amount the dc output voltage changes over a range of circuit operation. The voltage provided at the output under no-load condition (no current drawn from the supply) is reduced when load current is drawn from the supply (under load). The amount the dc voltage changes, 784, , Chapter 19, , Power Supplies (Voltage Regulators)
Page 811 :
V.R., , between the no-load and load conditions is described by a factor called voltage regulation., Definition: Voltage regulation, no-load voltage full-load voltage, Voltage regulation , full-load voltage, VNL VFL, 100%, %V.R. , VFL, , (19.2), , A dc voltage supply provides 60 V when the output is unloaded. When connected to, a load, the output drops to 56 V. Calculate the value of voltage regulation., , EXAMPLE 19.2, , Solution, VNL VFL, 60 V 56 V, Eq. (19.2): %V.R. , 100% 100% 7.1%, 56 V, VFL, If the value of full-load voltage is the same as the no-load voltage, the voltage, regulation calculated is 0%, which is the best expected. This means that the supply, is a perfect voltage source for which the output voltage is independent of the current, drawn from the supply. The smaller the voltage regulation, the better the operation of, the voltage supply circuit., RIPPLE FACTOR OF RECTIFIED SIGNAL, Although the rectified voltage is not a filtered voltage, it nevertheless contains a, dc component and a ripple component. We will see that the full-wave rectified signal, has a larger dc component and less ripple than the half-wave rectified voltage., For a half-wave rectified signal, the output dc voltage is, Vdc 0.318Vm, , (19.3), , The rms value of the ac component of the output signal can be calculated (see Appendix B) to be, Vr(rms) 0.385Vm, , (19.4), , The percent ripple of a half-wave rectified signal can then be calculated as, Vr(rms), 0.385Vm, r, 100% , 100% 121%, Vdc, 0.318Vm, , (19.5), , For a full-wave rectified voltage the dc value is, Vdc 0.636Vm, , (19.6), , The rms value of the ac component of the output signal can be calculated (see Appendix B) to be, Vr(rms) 0.308Vm, , (19.7), , The percent ripple of a full-wave rectified signal can then be calculated as, Vr(rms), 0.308Vm, r, 100% , 100% 48%, Vdc, 0.636Vm, , (19.8), , In summary, a full-wave rectified signal has less ripple than a half-wave rectified signal and is thus better to apply to a filter., 19.2, , General Filter Considerations, , 785
Page 812 :
V.R., , 19.3 CAPACITOR FILTER, A very popular filter circuit is the capacitor-filter circuit shown in Fig. 19.3. A capacitor is connected at the rectifier output, and a dc voltage is obtained across the capacitor. Figure 19.4a shows the output voltage of a full-wave rectifier before the signal is filtered, while Fig. 19.4b shows the resulting waveform after the filter capacitor, is connected at the rectifier output. Notice that the filtered waveform is essentially a, dc voltage with some ripple (or ac variation)., , Figure 19.3 Simple capacitor, filter., , Figure 19.4 Capacitor filter operation: (a) full-wave rectifier voltage; (b) filtered, output voltage., , Figure 19.5a shows a full-wave bridge rectifier and the output waveform obtained, from the circuit when connected to a load (RL). If no load were connected across the, capacitor, the output waveform would ideally be a constant dc level equal in value to, the peak voltage (Vm) from the rectifier circuit. However, the purpose of obtaining a, , Figure 19.5 Capacitor filter:, (a) capacitor filter circuit; (b) output, voltage waveform., , 786, , Chapter 19, , Power Supplies (Voltage Regulators)
Page 813 :
V.R., , dc voltage is to provide this voltage for use by various electronic circuits, which then, constitute a load on the voltage supply. Since there will always be a load on the filter output, we must consider this practical case in our discussion., , Output Waveform Times, Figure 19.5b shows the waveform across a capacitor filter. Time T1 is the time during which diodes of the full-wave rectifier conduct, charging the capacitor up to the, peak rectifier voltage, Vm. Time T2 is the time interval during which the rectifier voltage drops below the peak voltage, and the capacitor discharges through the load. Since, the charge–discharge cycle occurs for each half-cycle for a full-wave rectifier, the period of the rectified waveform is T/2, one-half the input signal frequency. The filtered, voltage, as shown in Fig. 19.6, shows the output waveform to have a dc level Vdc and, a ripple voltage Vr (rms) as the capacitor charges and discharges. Some details of, these waveforms and the circuit elements are considered next., , Figure 19.6 Approximate, output voltage of capacitor filter, circuit., , RIPPLE VOLTAGE, Vr (RMS), Appendix B provides the details for determining the value of the ripple voltage, in terms of the other circuit parameters. The ripple voltage can be calculated from, 2.4 Idc, 2.4Vdc, Ic, Vr (rms) d, , , C, RLC, 43 fC, , (19.9), , where Idc is in milliamperes, C is in microfarads, and RL is in kilohms., Calculate the ripple voltage of a full-wave rectifier with a 100-F filter capacitor connected to a load drawing 50 mA., , EXAMPLE 19.3, , Solution, 2.4(50), Eq. (19.9): Vr(rms) 1.2 V, 100, , DC VOLTAGE, Vdc, From Appendix B, we can express the dc value of the waveform across the filter, capacitor as, 19.3 Capacitor Filter, , 787
Page 814 :
V.R., , Ic, 4.17Idc, Vdc Vm d, Vm , 4fC, C, , (19.10), , where Vm is the peak rectifier voltage, Idc is the load current in milliamperes, and C, is the filter capacitor in microfarads., , EXAMPLE 19.4, , If the peak rectified voltage for the filter circuit of Example 19.3 is 30 V, calculate, the filter dc voltage., , Solution, 4.17Idc, 4.17(50), Eq. (19.10): Vdc Vm , 30 27.9 V, C, 100, , Filter Capacitor Ripple, Using the definition of ripple [Eq. (19.1)], Eq. (19.9), and Eq. (19.10), with Vdc , Vm, we can obtain the expression for the output waveform ripple of a full-wave rectifier and filter-capacitor circuit., Vr(rms), 2.4 Idc, 2.4, 100% , r, 100% 100%, CVdc, Vdc, RLC, , (19.11), , where Idc is in milliamperes, C is in microfarads, Vdc is in volts, and RL is in kilohms., , EXAMPLE 19.5, , Calculate the ripple of a capacitor filter for a peak rectified voltage of 30 V, capacitor C 50 F, and a load current of 50 mA., , Solution, 2.4 Idc, 2.4(50), Eq. (19.11): r , 100% 100% 4.3%, CVdc, 100(27.9), We could also calculate the ripple using the basic definition, Vr (rms), 1.2 V, 100% 100% 4.3%, r, Vdc, 27.9 V, , Diode Conduction Period and Peak Diode Current, From the previous discussion, it should be clear that larger values of capacitance provide less ripple and higher average voltage, thereby providing better filter action. From, this one might conclude that to improve the performance of a capacitor filter it is only, necessary to increase the size of the filter capacitor. The capacitor, however, also affects the peak current drawn through the rectifying diodes, and as will be shown next,, the larger the value of the capacitor, the larger the peak current drawn through the, rectifying diodes., Recall that the diodes conduct during period T1 (see Fig. 19.5), during which time, the diode must provide the necessary average current to charge the capacitor. The, shorter this time interval, the larger the amount of the charging current. Figure 19.7, shows this relation for a half-wave rectified signal (it would be the same basic oper788, , Chapter 19, , Power Supplies (Voltage Regulators)
Page 815 :
V.R., , Figure 19.7 Output voltage, and diode current waveforms:, (a) small C; (b) large C., , ation for full-wave). Notice that for smaller values of capacitor, with T1 larger, the, peak diode current is less than for larger values of filter capacitor., Since the average current drawn from the supply must equal the average diode, current during the charging period, the following relation can be used (assuming constant diode current during charge time):, T, Idc 1 Ipeak, T, from which we obtain, T, Ipeak Idc, T1, , (19.12), , where T1 diode conduction time, T 1/f ( f 2 60 for full-wave), Idc average current drawn from filter, Ipeak peak current through conducting diodes, , 19.4 RC FILTER, It is possible to further reduce the amount of ripple across a filter capacitor by using, an additional RC filter section as shown in Fig. 19.8. The purpose of the added RC, section is to pass most of the dc component while attenuating (reducing) as much of, , R, Rectifier, output, , C1, , Capacitor, filter, , RL, , C2, , Additional RC, filter, , Load, , Figure 19.8 RC filter stage., , 19.4 RC Filter, , 789
Page 816 :
V.R., , the ac component as possible. Figure 19.9 shows a full-wave rectifier with capacitor, filter followed by an RC filter section. The operation of the filter circuit can be analyzed using superposition for the dc and ac components of signal., , Figure 19.9 Full-wave rectifier and RC filter circuit., , DC Operation of RC Filter Section, Figure 19.10a shows the dc equivalent circuit to use in analyzing the RC filter circuit, of Fig. 19.9. Since both capacitors are open-circuit for dc operation, the resulting output dc voltage is, RL, Vdc V, dc, R RL, , (19.13), , Figure 19.10 (a) Dc and (b) ac, equivalent circuits of RC filter., , EXAMPLE 19.6, , Calculate the dc voltage across a 1-k load for an RC filter section (R 120, C 10 F). The dc voltage across the initial filter capacitor is Vdc 60 V., , Solution, RL, 1000, Eq. (19.13): Vdc , Vdc (60 V) 53.6 V, R RL, 120 1000, , 790, , Chapter 19, , Power Supplies (Voltage Regulators), , ,
Page 817 :
V.R., , AC Operation of RC Filter Section, Figure 19.10b shows the ac equivalent circuit of the RC filter section. Due to the voltage-divider action of the capacitor ac impedance and the load resistor, the ac component of voltage resulting across the load is, XC, Vr (rms), Vr(rms) , R, , (19.14), , For a full-wave rectifier with ac ripple at 120 Hz, the impedance of a capacitor can, be calculated using, 1.3, XC , C, , (19.15), , where C is in microfarads and XC is in kilohms., Calculate the dc and ac components of the output signal across load RL in the circuit, of Fig. 19.11. Calculate the ripple of the output waveform., , EXAMPLE 19.7, , Figure 19.11 RC filter circuit for Example 19.7., , Solution, DC Calculation:, , RL, 5k, Eq. (19.13): Vdc , Vdc (150 V) 136.4 V, R RL, 500 5 k, AC Calculation:, , The RC section capacitive impedance is, 1.3, 1.3, Eq. (19.15): XC 0.13 k, C, 10, , 130, , The ac component of the output voltage, calculated using Eq. (19.14), is, XC, 130, Vr (rms) (15 V) 3.9 V, Vr(rms) , R, 500, The ripple of the output waveform is then, Vr(rms), 3.9 V, 100% 100% 2.86%, r, Vdc, 136.4 V, , 19.4 RC Filter, , 791
Page 818 :
V.R., , 19.5 DISCRETE TRANSISTOR VOLTAGE, REGULATION, Two types of transistor voltage regulators are the series voltage regulator and the shunt, voltage regulator. Each type of circuit can provide an output dc voltage that is regulated or maintained at a set value even if the input voltage varies or if the load connected to the output changes., , Series Voltage Regulation, The basic connection of a series regulator circuit is shown in the block diagram of, Fig. 19.12. The series element controls the amount of the input voltage that gets to, the output. The output voltage is sampled by a circuit that provides a feedback voltage to be compared to a reference voltage., , Figure 19.12 Series regulator, block diagram., , 1. If the output voltage increases, the comparator circuit provides a control signal to, cause the series control element to decrease the amount of the output voltage—, thereby maintaining the output voltage., 2. If the output voltage decreases, the comparator circuit provides a control signal to, cause the series control element to increase the amount of the output voltage., SERIES REGULATOR CIRCUIT, A simple series regulator circuit is shown in Fig. 19.13. Transistor Q1 is the series control element, and Zener diode DZ provides the reference voltage. The regulating operation can be described as follows:, 1. If the output voltage decreases, the increased base-emitter voltage causes transistor Q1 to conduct more, thereby raising the output voltage—maintaining the output constant., 2. If the output voltage increases, the decreased base-emitter voltage causes transistor Q1 to conduct less, thereby reducing the output voltage—maintaining the output constant., , Figure 19.13 Series regulator, circuit., , 792, , Chapter 19, , Power Supplies (Voltage Regulators)
Page 819 :
V.R., , Calculate the output voltage and Zener current in the regulator circuit of Fig. 19.14, for RL 1 k ., , EXAMPLE 19.8, , Figure 19.14 Circuit for, Example 19.8., , Solution, Vo VZ VBE 12 V 0.7 V 11.3 V, VCE Vi Vo 20 V 11.3 V 8.7 V, 20 V 12 V, 8V, IR 36.4 mA, 220, 220, For RL 1 k ,, 11.3 V, Vo, IL , 11.3 mA, 1k, RL, I, 11.3 mA, IB C 226 A, 50, IZ IR IB 36.4 mA 226 A 36 mA, IMPROVED SERIES REGULATOR, An improved series regulator circuit is that of Fig. 19.15. Resistors R1 and R2 act, as a sampling circuit, Zener diode DZ providing a reference voltage, and transistor Q2, then controls the base current to transistor Q1 to vary the current passed by transistor Q1 to maintain the output voltage constant., If the output voltage tries to increase, the increased voltage sampled by R1 and, R2, increased voltage V2, causes the base-emitter voltage of transistor Q2 to go up, Q1, Vi, (unregulated, voltage), , Vo, (regulated, voltage), , R4, R1, , –, Q2, , Vz, , RL, , +, , +, VBE2, , R3, , V2, , R2, , –, Figure 19.15 Improved series regulator circuit., , 19.5 Discrete Transistor Voltage Regulation, , 793
Page 820 :
V.R., , (since VZ remains fixed). If Q2 conducts more current, less goes to the base of transistor Q1, which then passes less current to the load, reducing the output voltage—, thereby maintaining the output voltage constant. The opposite takes place if the output voltage tries to decrease, causing less current to be supplied to the load, to keep, the voltage from decreasing., The voltage V2 provided by sensing resistors R1 and R2 must equal the sum of the, base-emitter voltage of Q2 and the Zener diode, that is,, R2, VBE2 VZ V2 , Vo, R1 R2, , (19.16), , Solving Eq. (19.16) for the regulated output voltage, Vo,, R1 R2, Vo , (VZ VBE2), R2, , EXAMPLE 19.9, , (19.17), , What regulated output voltage is provided by the circuit of Fig. 19.15 for the following circuit elements: R1 20 k , R2 30 k , and VZ 8.3 V?, , Solution, From Eq. (19.17), the regulated output voltage will be, 20 k 30 k, Vo (8.3 V 0.7 V) 15 V, 30 k, , OP-AMP SERIES REGULATOR, Another version of series regulator is that shown in Fig. 19.16. The op-amp compares the Zener diode reference voltage with the feedback voltage from sensing resistors R1 and R2. If the output voltage varies, the conduction of transistor Q1 is controlled to maintain the output voltage constant. The output voltage will be maintained, at a value of, , , , , , R, Vo 1 1 VZ, R2, , Figure 19.16 Op-amp series regulator circuit., , 794, , Chapter 19, , Power Supplies (Voltage Regulators), , (19.18)
Page 821 :
V.R., , Calculate the regulated output voltage in the circuit of Fig. 19.17., , EXAMPLE 19.10, , Figure 19.17 Circuit for, Example 19.10., , Solution, , , , , , 30 k, Eq. (19.18): Vo 1 6.2 V 24.8 V, 10 k, CURRENT-LIMITING CIRCUIT, One form of short-circuit or overload protection is current limiting, as shown in, Fig. 19.18. As load current IL increases, the voltage drop across the short-circuit sensing resistor RSC increases. When the voltage drop across RSC becomes large enough,, it will drive Q2 on, diverting current from the base of transistor Q1, thereby reducing, the load current through transistor Q1, preventing any additional current to load RL., The action of components RSC and Q2 provides limiting of the maximum load current., , Figure 19.18 Current-limiting voltage regulator., , FOLDBACK LIMITING, Current limiting reduces the load voltage when the current becomes larger than, the limiting value. The circuit of Fig. 19.19 provides foldback limiting, which reduces, both the output voltage and output current protecting the load from overcurrent, as, well as protecting the regulator., 19.5 Discrete Transistor Voltage Regulation, , 795
Page 822 :
V.R., , Figure 19.19 Foldback-limiting, series regulator circuit., , Foldback limiting is provided by the additional voltage-divider network of R4 and, R5 in the circuit of Fig. 19.19 (over that of Fig. 19.17). The divider circuit senses the, voltage at the output (emitter) of Q1. When IL increases to its maximum value, the, voltage across RSC becomes large enough to drive Q2 on, thereby providing current, limiting. If the load resistance is made smaller, the voltage driving Q2 on becomes, less, so that IL drops when VL also drops in value—this action being foldback limiting. When the load resistance is returned to its rated value, the circuit resumes its, voltage regulation action., , Shunt Voltage Regulation, A shunt voltage regulator provides regulation by shunting current away from the load, to regulate the output voltage. Figure 19.20 shows the block diagram of such a voltage regulator. The input unregulated voltage provides current to the load. Some of the, current is pulled away by the control element to maintain the regulated output voltage across the load. If the load voltage tries to change due to a change in the load,, the sampling circuit provides a feedback signal to a comparator, which then provides, a control signal to vary the amount of the current shunted away from the load. As the, output voltage tries to get larger, for example, the sampling circuit provides a feedback signal to the comparator circuit, which then provides a control signal to draw, increased shunt current, providing less load current, thereby keeping the regulated, voltage from rising., , Figure 19.20 Block diagram, of shunt voltage regulator., , BASIC TRANSISTOR SHUNT REGULATOR, A simple shunt regulator circuit is shown in Fig. 19.21. Resistor RS drops the unregulated voltage by an amount that depends on the current supplied to the load, RL., The voltage across the load is set by the Zener diode and transistor base-emitter volt796, , Chapter 19, , Power Supplies (Voltage Regulators)
Page 823 :
V.R., , Figure 19.21 Transistor shunt, voltage regulator., , age. If the load resistance decreases, a reduced drive current to the base of Q1 results,, shunting less collector current. The load current is thus larger, thereby maintaining, the regulated voltage across the load. The output voltage to the load is, VL VZ VBE, , (19.19), , Determine the regulated voltage and circuit currents for the shunt regulator of Fig., 19.22., , EXAMPLE 19.11, , Figure 19.22 Circuit for Example 19.11., , Solution, The load voltage is, Eq. (19.19): VL 8.2 V 0.7 V 8.9 V, For the given load,, VL, 8.9 V, IL , 89 mA, RL, 100, With the unregulated input voltage at 22 V, the current through RS is, Vi VL, 22 V 8.9 V, IS , 109 mA, RS, 120, so that the collector current is, IC IS IL 109 mA 89 mA 20 mA, (The current through the Zener and transistor base–emitter is smaller than IC by the, transistor beta.), , 19.5 Discrete Transistor Voltage Regulation, , 797
Page 824 :
V.R., , IMPROVED SHUNT REGULATOR, The circuit of Fig. 19.23 shows an improved shunt voltage regulator circuit. The, Zener diode provides a reference voltage so that the voltage across R1 senses the output voltage. As the output voltage tries to change, the current shunted by transistor, Q1 is varied to maintain the output voltage constant. Transistor Q2 provides a larger, base current to transistor Q1 than the circuit of Fig. 19.21, so that the regulator handles a larger load current. The output voltage is set by the Zener voltage and that, across the two transistor base–emitters,, Vo VL VZ VBE2 VBE1, , (19.20), , Figure 19.23 Improved shunt voltage regulator circuit., , SHUNT VOLTAGE REGULATOR USING OP-AMP, Figure 19.24 shows another version of a shunt voltage regulator using an op-amp, as voltage comparator. The Zener voltage is compared to the feedback voltage obtained from voltage divider R1 and R2 to provide the control drive current to shunt element Q1. The current through resistor RS is thus controlled to drop a voltage across, RS so that the output voltage is maintained., , Figure 19.24 Shunt voltage regulator using op-amp., , Switching Regulation, A type of regulator circuit that is quite popular for its efficient transfer of power to, the load is the switching regulator. Basically, a switching regulator passes voltage to, 798, , Chapter 19, , Power Supplies (Voltage Regulators)
Page 825 :
V.R., , the load in pulses, which are then filtered to provide a smooth dc voltage. Figure 19.25, shows the basic components of such a voltage regulator. The added circuit complexity is well worth the improved operating efficiency obtained., , Output-input, voltage differential, , +, Unregulated, input voltage, Vi, , IN, , Voltage, regulator, GND, , Load current, IL, , OUT, , +, Regulated, output voltage, Vo, , Load, , –, , –, Input voltage, range, ∆Vo, , Load regulation, Line regulation, , Figure 19.25 Block representation of three-terminal voltage regulator., , 19.6 IC VOLTAGE REGULATORS, Voltage regulators comprise a class of widely used ICs. Regulator IC units contain, the circuitry for reference source, comparator amplifier, control device, and overload, protection all in a single IC. Although the internal construction of the IC is somewhat, different from that described for discrete voltage regulator circuits, the external operation is much the same. IC units provide regulation of either a fixed positive voltage, a fixed negative voltage, or an adjustably set voltage., A power supply can be built using a transformer connected to the ac supply line, to step the ac voltage to a desired amplitude, then rectifying that ac voltage, filtering, with a capacitor and RC filter, if desired, and finally regulating the dc voltage using, an IC regulator. The regulators can be selected for operation with load currents from, hundreds of milliamperes to tens of amperes, corresponding to power ratings from, milliwatts to tens of watts., , Three-Terminal Voltage Regulators, Figure 19.25 shows the basic connection of a three-terminal voltage regulator IC to, a load. The fixed voltage regulator has an unregulated dc input voltage, Vi, applied to, one input terminal, a regulated output dc voltage, Vo, from a second terminal, with, the third terminal connected to ground. For a selected regulator, IC device specifications list a voltage range over which the input voltage can vary to maintain a regulated output voltage over a range of load current. The specifications also list the amount, of output voltage change resulting from a change in load current (load regulation) or, in input voltage (line regulation)., , Fixed Positive Voltage Regulators, The series 78 regulators provide fixed regulated voltages from 5 to 24 V. Figure 19.26, shows how one such IC, a 7812, is connected to provide voltage regulation with output from this unit of 12 V dc. An unregulated input voltage Vi is filtered by capacitor C1 and connected to the IC’s IN terminal. The IC’s OUT terminal provides a regulated 12 V, which is filtered by capacitor C2 (mostly for any high-frequency noise)., 19.6, , IC Voltage Regulators, , 799
Page 826 :
V.R., , Figure 19.26 Connection of, 7812 voltage regulator., , The third IC terminal is connected to ground (GND). While the input voltage may, vary over some permissible voltage range and the output load may vary over some, acceptable range, the output voltage remains constant within specified voltage variation limits. These limitations are spelled out in the manufacturer’s specification sheets., A table of positive voltage regulator ICs is provided in Table 19.1., TABLE 19.1 Positive Voltage Regulators in 7800 Series, IC Part, , Output Voltage (V), , Minimum Vi (V), , 7805, 7806, 7808, 7810, 7812, 7815, 7818, 7824, , 5, 6, 8, 10, 12, 15, 18, 24, , 7.3, 8.3, 10.5, 12.5, 14.6, 17.7, 21.0, 27.1, , The connection of a 7812 in a complete voltage supply is shown in the connection of Fig. 19.27. The ac line voltage (120 V rms) is stepped down to 18 V rms across, each half of the center-tapped transformer. A full-wave rectifier and capacitor filter, then provides an unregulated dc voltage, shown as a dc voltage of about 22 V, with, ac ripple of a few volts as input to the voltage regulator. The 7812 IC then provides, an output that is a regulated 12 V dc., , Figure 19.27 12 V power supply., , 800, , Chapter 19, , Power Supplies (Voltage Regulators)
Page 827 :
V.R., , POSITIVE VOLTAGE REGULATOR SPECIFICATIONS, The specifications sheet of voltage regulators is typified by that shown in Fig. 19.28, for the group of series 7800 positive voltage regulators. Some consideration of a few, of the more important parameters should be made., , Output, Common, Input, , Absolute maximum ratings:, Input voltage, 40 V, Continuous total dissipation 2 W, Operating free-air, temperature range −65 to 150°C, , Nominal, output, voltage, , Regulator, , 5V, 6V, 8V, 10 V, 12 V, 15 V, 18 V, 24 V, , 7805, 7806, 7808, 7810, 7812, 7815, 7818, 7824, , µA 7812C electrical characteristics:, Parameter, , Min., , Typ., , Max., , Units, , Output voltage, Input regulation, Ripple rejection, Output regulation, Output resistance, Dropout voltage, Short-circuit output current, Peak output current, , 11.5, , 12, 3, 71, 4, 0.018, 2.0, 350, 2.2, , 12.5, 120, , V, mV, dB, mV, Ω, V, mA, A, , 55, , 100, , Figure 19.28 Specification sheet data for voltage regulator ICs., , Output voltage: The specification for the 7812 shows that the output voltage, is typically 12 V but could be as low as 11.5 V or as high as 12.5 V., Output regulation: The output voltage regulation is seen to be typically 4 mV,, to a maximum of 100 mV (at output currents from 0.25 to 0.75 A). This information, specifies that the output voltage can typically vary only 4 mV from the rated 12 V dc., Short-circuit output current: The amount of current is limited to typically 0.35, A if the output were to be short-circuited (presumably by accident or by another faulty, component)., Peak output current: While the rated maximum current is 1.5 A for this series, of IC, the typical peak output current that might be drawn by a load is 2.2 A. This, shows that although the manufacturer rates the IC as capable of providing 1.5 A, one, could draw somewhat more current (possibly for a short period of time)., Dropout voltage: The dropout voltage, typically 2 V, is the minimum amount, of voltage across the input–output terminals that must be maintained if the IC is to, operate as a regulator. If the input voltage drops too low or the output rises so that at, least 2 V is not maintained across the IC input–output, the IC will no longer provide, voltage regulation. One therefore maintains an input voltage large enough to assure, that the dropout voltage is provided., 19.6, , IC Voltage Regulators, , 801
Page 828 :
V.R., , Fixed Negative Voltage Regulators, The series 7900 ICs provide negative voltage regulators, similar to those providing, positive voltages. A list of negative voltage regulator ICs is provided in Table 19.2., As shown, IC regulators are available for a range of fixed negative voltages, the selected IC providing the rated output voltage as long as the input voltage is maintained, greater than the minimum input value. For example, the 7912 provides an output of, 12 V as long as the input to the regulator IC is more negative than 14.6 V., TABLE 19.2 Negative Voltage Regulators in 7900 Series, , EXAMPLE 19.12, , IC Part, , Output Voltage (V), , Minimum Vi (V), , 7905, 7906, 7908, 7909, 7912, 7915, 7918, 7924, , 5, 6, 8, 9, 12, 15, 18, 24, , 7.3, 8.4, 10.5, 11.5, 14.6, 17.7, 20.8, 27.1, , Draw a voltage supply using a full-wave bridge rectifier, capacitor filter, and IC regulator to provide an output of 5 V., , Solution, The resulting circuit is shown in Fig. 19.29., , Figure 19.29, , EXAMPLE 19.13, , 5-V power supply., , For a transformer output of 15 V and a filter capacitor of 250 F, calculate the minimum input voltage when connected to a load drawing 400 mA., , Solution, The voltages across the filter capacitor are, 2.4Idc, 2.4(400), Vr(peak) 3, Vr(rms) 3, , 3 6.65 V, C, 250, Vdc Vm Vr(peak) 15 V 6.65 V 8.35 V, 802, , Chapter 19, , Power Supplies (Voltage Regulators)
Page 829 :
V.R., , Since the input swings around this dc level, the minimum input voltage can drop to, as low as, Vi(low) Vdc Vr(peak) 15 V 6.65 V 8.35 V, Since this voltage is greater than the minimum required for the IC regulator (from, Table 19.1, Vi 7.3 V), the IC can provide a regulated voltage to the given load., Determine the maximum value of load current at which regulation is maintained for, the circuit of Fig. 19.29., , EXAMPLE 19.14, , Solution, To maintain Vi(min), , 7.3 V,, , Vr (peak), , Vm Vi(min) 15 V 7.3 V 7.7 V, , so that, Vr(peak), 7.7 V, Vr (rms) 4.4 V, 3, 1.73, The value of load current is then, Vr (rms)C, (4.4 V)(250), Idc , 458 mA, 2.4, 2.4, Any current above this value is too large for the circuit to maintain the regulator output at 5 V., , Adjustable Voltage Regulators, Voltage regulators are also available in circuit configurations that allow the user to, set the output voltage to a desired regulated value. The LM317, for example, can be, operated with the output voltage regulated at any setting over the range of voltage, from 1.2 to 37 V. Figure 19.30 shows how the regulated output voltage of an LM317, can be set., Resistors R1 and R2 set the output to any desired voltage over the adjustment range, (1.2 to 37 V). The output voltage desired can be calculated using, , , , , , R2, IadjR2, Vo Vref 1 , R1, , (19.21), , with typical IC values of, Vref 1.25 V, , and, , Iadj 100 A, , Figure 19.30 Connection of, LM317 adjustable-voltage, regulator., , 19.6, , IC Voltage Regulators, , 803
Page 830 :
V.R., , EXAMPLE 19.15, , Determine the regulated voltage in the circuit of Fig. 19.30 with R1 240, R2 2.4 k ., , and, , Solution, , , , , , 2.4 k, Eq. (19.21): Vo 1.25 V 1 (100 A)(2.4 k ), 240, 13.75 V 0.24 V 13.99 V, , EXAMPLE 19.16, , Determine the regulated output voltage of the circuit in Fig. 19.31., , Figure 19.31 Positive adjustable-voltage regulator for Example 19.16., , Solution, The output voltage calculated using Eq. (19.21) is, , , , , , 1.8 k, Vo 1.25 V 1 (100 A)(1.8 k ) 10.8 V, 240, A check of the filter capacitor voltage shows that an input–output difference of 2 V, can be maintained up to at least 200 mA load current., , 19.7 PSPICE WINDOWS, Program 19.1—Op-Amp Series Regulator, The op-amp series regulator circuit of Fig. 19.16 can be analyzed using PSpice Windows Design Center, with the resulting schematic drawn as shown in Fig. 19.32. The, Analysis Setup was used to provide a dc voltage sweep from 8 to 15 V in 0.5-V increments. Diode D1 provides a Zener voltage of 4.7 V (VZ 4.7), and transistor Q1, is set to beta 100. Using Eq. (19.18),, , , , , , , , , , R1, 1k, VO 1 , VZ 1 4.7 V 9.4 V, R2, 1k, Notice in Fig. 19.32 that the regulated output voltage is 9.25 V when the input is 10, V. Figure 19.33 shows the PROBE output for the dc voltage sweep. Notice also that, after the input goes above about 9 V, the output is held regulated at about 9.3 V., 804, , Chapter 19, , Power Supplies (Voltage Regulators)
Page 831 :
V.R., , Figure 19.32 Op-amp series regulator drawn using PSpice Design Center., , Figure 19.33 Probe output showing voltage regulation of Fig. 19.32., , 19.7, , PSpice Windows, , 805
Page 832 :
V.R., , Program 19.2—Shunt Voltage Regulator Using Op-Amp, The shunt voltage regulator circuit of Fig. 19.34 was drawn using PSpice Windows, Design Center. With the Zener voltage set at 4.7 V and transistor beta set at 100, the, output is 9.255 V when the input is 10 V. A dc sweep from 8 V to 15 V is shown in, the PROBE output in Fig. 19.35. The circuit provides good voltage regulation for inputs from about 9.5 to over 14 V, the output being held at the regulated value of about, 9.3 V., , Figure 19.34 Shunt voltage, regulator using op-amp (drawn, using PSpice Design Center)., , Figure 19.35 Probe output for, dc voltage sweep of Fig. 19.34., , 806, , Chapter 19, , Power Supplies (Voltage Regulators)
Page 833 :
V.R., , PROBLEMS, , § 19.2 General Filter Considerations, 1. What is the ripple factor of a sinusoidal signal having peak ripple of 2 V on an average of 50 V?, 2. A filter circuit provides an output of 28 V unloaded and 25 V under full-load operation. Calculate the percent voltage regulation., 3. A half-wave rectifier develops 20 V dc. What is the value of the ripple voltage?, 4. What is the rms ripple voltage of a full-wave rectifier with output voltage 8 V dc?, , § 19.3 Capacitor Filter, 5. A simple capacitor filter fed by a full-wave rectifier develops 14.5 V dc at 8.5% ripple factor., What is the output ripple voltage (rms)?, 6. A full-wave rectified signal of 18 V peak is fed into a capacitor filter. What is the voltage regulation of the filter if the output is 17 V dc at full load?, 7. A full-wave rectified voltage of 18 V peak is connected to a 400-F filter capacitor. What are, the ripple and dc voltages across the capacitor at a load of 100 mA?, 8. A full-wave rectifier operating from the 60-Hz ac supply produces a 20-V peak rectified voltage. If a 200-F capacitor is used, calculate the ripple at a load of 120 mA., 9. A full-wave rectifier (operating from a 60-Hz supply) drives a capacitor-filter circuit (C 100, F), which develops 12 V dc when connected to a 2.5-k load. Calculate the output voltage, ripple., 10. Calculate the size of the filter capacitor needed to obtain a filtered voltage having 15% ripple, at a load of 150 mA. The full-wave rectified voltage is 24 V dc, and the supply is 60 Hz., *, , 11. A 500-F capacitor provides a load current of 200 mA at 8% ripple. Calculate the peak rectified, voltage obtained from the 60-Hz supply and the dc voltage across the filter capacitor., 12. Calculate the size of the filter capacitor needed to obtain a filtered voltage with 7% ripple at a, load of 200 mA. The full-wave rectified voltage is 30 V dc, and the supply is 60 Hz., 13. Calculate the percent ripple for the voltage developed across a 120-F filter capacitor when, providing a load current of 80 mA. The full-wave rectifier operating from the 60-Hz supply develops a peak rectified voltage of 25 V., , § 19.4 RC Filter, 14. An RC filter stage is added after a capacitor filter to reduce the percent of ripple to 2%. Calculate the ripple voltage at the output of the RC filter stage providing 80 V dc., *, , *, , 15. An RC filter stage (R 33 , C 120 F) is used to filter a signal of 24 V dc with 2 V rms, operating from a full-wave rectifier. Calculate the percent ripple at the output of the RC section for a 100-mA load. Also, calculate the ripple of the filtered signal applied to the RC stage., 16. A simple capacitor filter has an input of 40 V dc. If this voltage is fed through an RC filter section (R 50 , C 40 F), what is the load current for a load resistance of 500 ?, 17. Calculate the rms ripple voltage at the output of an RC filter section that feeds a 1-k load, when the filter input is 50 V dc with 2.5-V rms ripple from a full-wave rectifier and capacitor, filter. The RC filter section components are R 100 and C 100 F., 18. If the no-load output voltage for Problem 17 is 50 V, calculate the percent voltage regulation, with a 1-k load., , § 19.5 Discrete Transistor Voltage Regulation, *, , 19. Calculate the output voltage and Zener diode current in the regulator circuit of Fig. 19.36., 20. What regulated output voltage results in the circuit of Fig. 19.37?, , Problems, , 807
Page 834 :
V.R., , Figure 19.36 Problem 19, , Figure 19.37, , Problem 20, , 21. Calculate the regulated output voltage in the circuit of Fig. 19.38., , Figure 19.38, , Problem 21, , 22. Determine the regulated voltage and circuit currents for the shunt regulator of Fig. 19.39., , Figure 19.39, , Problem 22, , § 19.6 IC Voltage Regulators, 23. Draw the circuit of a voltage supply comprised of a full-wave bridge rectifier, capacitor filter,, and IC regulator to provide an output of 12 V., *, , 24. Calculate the minimum input voltage of the full-wave rectifier and filter capacitor network in, Fig. 19.40 when connected to a load drawing 250 mA., , Figure 19.40 Problem 24, , 808, , Chapter 19, , Power Supplies (Voltage Regulators)
Page 835 :
V.R., *, , 25. Determine the maximum value of load current at which regulation is maintained for the circuit, of Fig. 19.41., , Figure 19.41 Problem 25, , 26. Determine the regulated voltage in the circuit of Fig. 19.30 with R1 240, , and R2 1.8 k ., , 27. Determine the regulated output voltage from the circuit of Fig. 19.42., , Figure 19.42 Problem 27, , § 19.7 PSpice Windows, *, , 28. Modify the circuit of Fig. 19.32 to include a load resistor, RL. Keeping the input voltage fixed, at 10 V, do a sweep of the load resistor from 100 to 20 k , showing the output voltage using Probe., , *, , 29. For the circuit of Fig. 19.34, do a sweep showing the output voltage for RL varied from 5 k, to 20 k ., , *, , 30. Run a PSpice analysis of the circuit of Fig. 19.19 for VZ 4.7 V, beta (Q1) beta (Q2) 100,, and vary Vi from 5 V to 20 V., *Please Note: Asterisks indicate more difficult problems., , Problems, , 809
Page 836 :
CHAPTER, , 20, , Other, Two-Terminal, Devices, 20.1 INTRODUCTION, There are a number of two-terminal devices having a single p-n junction like the semiconductor or Zener diode but with different modes of operation, terminal characteristics, and areas of application. A number, including the Schottky, tunnel, varactor,, photodiode, and solar cell, will be introduced in this chapter. In addition, twoterminal devices of a different construction, such as the photoconductive cell,, LCD (liquid-crystal display), and thermistor, will be examined., , 20.2 SCHOTTKY BARRIER (HOT-CARRIER), DIODES, In recent years, there has been increasing interest in a two-terminal device referred, to as a Schottky-barrier, surface-barrier, or hot-carrier diode. Its areas of application, were first limited to the very high frequency range due to its quick response time (especially important at high frequencies) and a lower noise figure (a quantity of real, importance in high-frequency applications). In recent years, however, it is appearing, more and more in low-voltage/high-current power supplies and ac-to-dc converters., Other areas of application of the device include radar systems, Schottky TTL logic, for computers, mixers and detectors in communication equipment, instrumentation,, and analog-to-digital converters., Its construction is quite different from the conventional p-n junction in that a metalsemiconductor junction is created such as shown in Fig. 20.1. The semiconductor is, , Figure 20.1 Passivated, hot-carrier diode., , 810
Page 837 :
normally n-type silicon (although p-type silicon is sometimes used), while a host of, different metals, such as molybdenum, platinum, chrome, or tungsten, are used. Different construction techniques will result in a different set of characteristics for the, device, such as increased frequency range, lower forward bias, and so on. Priorities, do not permit an examination of each technique here, but information will usually be, provided by the manufacturer. In general, however, Schottky diode construction results in a more uniform junction region and a high level of ruggedness., In both materials, the electron is the majority carrier. In the metal, the level of minority carriers (holes) is insignificant. When the materials are joined, the electrons in, the n-type silicon semiconductor material immediately flow into the adjoining metal,, establishing a heavy flow of majority carriers. Since the injected carriers have a very, high kinetic energy level compared to the electrons of the metal, they are commonly, called “hot carriers.” In the conventional p-n junction, there was the injection of minority carriers into the adjoining region. Here the electrons are injected into a region, of the same electron plurality. Schottky diodes are therefore unique in that conduction is entirely by majority carriers. The heavy flow of electrons into the metal creates a region near the junction surface depleted of carriers in the silicon material—, much like the depletion region in the p-n junction diode. The additional carriers in, the metal establish a “negative wall” in the metal at the boundary between the two, materials. The net result is a “surface barrier” between the two materials, preventing, any further current. That is, any electrons (negatively charged) in the silicon material, face a carrier-free region and a “negative wall” at the surface of the metal., The application of a forward bias as shown in the first quadrant of Fig. 20.2 will, reduce the strength of the negative barrier through the attraction of the applied positive potential for electrons from this region. The result is a return to the heavy flow, of electrons across the boundary, the magnitude of which is controlled by the level, of the applied bias potential. The barrier at the junction for a Schottky diode is less, than that of the p-n junction device in both the forward- and reverse-bias regions. The, result is therefore a higher current at the same applied bias in the forward- and, reverse-bias regions. This is a desirable effect in the forward-bias region but highly, undesirable in the reverse-bias region., The exponential rise in current with forward bias is described by Eq. (1.4) but, with dependent on the construction technique (1.05 for the metal whisker type of, , Figure 20.2, , Comparison of characteristics of hot-carrier and p-n junction diodes., , 20.2, , Schottky Barrier (Hot-Carrier) Diodes, , 811
Page 838 :
construction, which is somewhat similar to the germanium diode). In the reverse-bias, region, the current Is is due primarily to those electrons in the metal passing into the, semiconductor material. One of the areas of continuing research on the Schottky diode, centers on reducing the high leakage currents that result with temperatures over 100°C., Through design, improvement units are now becoming available that have a temperature range from 65 to 150°C. At room temperature, Is is typically in the microampere range for low-power units and milliampere range for high-power devices,, although it is typically larger than that encountered using conventional p-n junction, devices with the same current limits. In addition, the PIV of Schottky diodes is usually significantly less than that of a comparable p-n junction unit. Typically, for a, 50-A unit, the PIV of the Schottky diode would be about 50 V as compared to 150 V, for the p-n junction variety. Recent advances, however, have resulted in Schottky, diodes with PIVs greater than 100 V at this current level. It is obvious from the characteristics of Fig. 20.2 that the Schottky diode is closer to the ideal set of characteristics than the point contact and has levels of VT less than the typical silicon semiconductor p-n junction. The level of VT for the “hot-carrier” diode is controlled to a, large measure by the metal employed. There exists a required trade-off between temperature range and level of VT. An increase in one appears to correspond to a resulting increase in the other. In addition, the lower the range of allowable current levels,, the lower the value of VT. For some low-level units, the value of VT can be assumed, to be essentially zero on an approximate basis. For the middle and high range, however, a value of 0.2 V would appear to be a good representative value., The maximum current rating of the device is presently limited to about 75 A, although 100-A units appear to be on the horizon. One of the primary areas of application of this diode is in switching power supplies that operate in the frequency range, of 20 kHz or more. A typical unit at 25°C may be rated at 50 A at a forward voltage, of 0.6 V with a recovery time of 10 ns for use in one of these supplies. A p-n junction device with the same current limit of 50 A may have a forward voltage drop, of 1.1 V and a recovery time of 30 to 50 ns. The difference in forward voltage may, not appear significant, but consider the power dissipation difference: Phot carrier , (0.6 V)(50 A) 30 W compared to Pp-n (1.1 V)(50 A) 55 W, which is a measurable difference when efficiency criteria must be met. There will, of course, be a, higher dissipation in the reverse-bias region for the Schottky diode due to the higher, leakage current, but the total power loss in the forward- and reverse-bias regions is, still significantly improved as compared to the p-n junction device., Recall from our discussion of reverse recovery time for the semiconductor diode, that the injected minority carriers accounted for the high level of trr (the reverse recovery time). The absence of minority carriers at any appreciable level in the Schottky diode results in a reverse recovery time of significantly lower levels, as indicated above. This is the primary reason Schottky diodes are so effective at, frequencies approaching 20 GHz, where the device must switch states at a very high, rate. For higher frequencies the point-contact diode, with its very small junction, area, is still employed., The equivalent circuit for the device (with typical values) and a commonly used, symbol appear in Fig. 20.3. A number of manufacturers prefer to use the standard, diode symbol for the device since its function is essentially the same. The inductance, LP and capacitance CP are package values, and rB is the series resistance, which includes the contact and bulk resistance. The resistance rd and capacitance CJ are values defined by equations introduced in earlier sections. For many applications, an excellent approximate equivalent circuit simply includes an ideal diode in parallel with, the junction capacitance as shown in Fig. 20.4., A number of hot-carrier rectifiers manufactured by Motorola Semiconductor Products, Inc., appear in Fig. 20.5 with their specifications and terminal identification., , 812, , Chapter 20, , Other Two-Terminal Devices
Page 839 :
Figure 20.4 Approximate, equivalent circuit for the Schottky, diode., Figure 20.3 Schottky (hot-carrier), diode: (a) equivalent circuit;, (b) symbol., , Io, Average rectified forward current (amperes), Case, , 0.5 A, , 1.0 A, , 3.0 A, , 51-02, (DO-7), Glass, , 59-04, Plastic, , 267, Plastic, , 3.0 A, , 5.0 A, , 15 A, , 25 A, , 60, Metal, , 40 A, , 257, (DO-4), Metal, , 257, (DO-5), Metal, , 430-2, (DO-21), Metal, , Anode, VRRM, Cathode:, (Volts), MBR020 IN5817, MBR030 IN5818, , 20, 30, 35, 40, , IN5819, IFSM, (Amps), , 5.0, , 100, , MBR120P IN5820 MBR320P MBR320M IN5823 IN5826 MBR1520, MBR130P IN5821 MBR330P MBR330M IN5824 IN5827 MBR1530, MBR135P, MBR335P MBR335M, MBR1535, MBR140P IN5822 MBR340P MBR340M IN5825 IN5828 MBR1540, 50, , 250, , 200, , 500, , 500, , 125°C, , 125°C, , 125°C, , 125°C, , 125°C, , Max VF @, IFM = Io, , 0.50 V, , *0.60 V, , 0.65 V, , *0.525 V, , 0.60 V, , 125°C, , 125°C, , IN5832 MBR4020 MBR4020PF, IN5833 MBR4030 MBR4030PF, MBR4035 MBR4035PF, IN5834 MBR4040, , 500, , 500, , 800, , 800, , 800, , 800, , 800, , 85, , 80, , 85, , 80, , 75, , 70, , 50, , 125°C, , 125°C, , 125°C, , 125°C, , 125°C, , 125°C, , 125°C, , 0.55 V, , *0.48 V, , 0.55 V, , *0.59 V, , 0.63 V, , 0.63 V, , TC @ Rated Io, (°C), TJ Max, , IN5829 MBR2520, IN5830 MBR2530, MBR2535, IN5831 MBR2540, , 0.45 V@5A *0.38 V *0.50 V, , . . . Schottky barrier devices, ideal for use in low-voltage, high-frequency power supplies and as free-wheeling diodes., These units feature very low forward voltages and switching times estimated at less than 10 ns. They are offered in, current ranges of 0.5 to 5.0 amperes and in voltages to 40., VRRM −respective peak reverse voltage, IFSM −forward current, surge peak, IFM −forward current, maximum, , Figure 20.5 Motorola Schottky barrier devices. (Courtesy Motorola Semiconductor Products, Incorporated.), , Note that the maximum forward voltage drop VF does not exceed 0.65 V for any of, the devices, while this was essentially VT for a silicon diode., Three sets of curves for the Hewlett-Packard 5082-2300 series of general-purpose, Schottky barrier diodes are provided in Fig. 20.6. Note at T 100°C in Fig. 20.6a, that VF is only 0.1 V at a current of 0.01 mA. Note also that the reverse current has, been limited to nanoamperes in Fig. 20.6b and the capacitance to 1 pF in Fig. 20.6c, to ensure a high switching rate., , 20.2, , Schottky Barrier (Hot-Carrier) Diodes, , 813
Page 840 :
IF, 10 µA, 100 µA, 1.0 mA, 10 mA, 100 mA, , −2.3 mV/°C, −1.8 mV/°C, −1.3 mV/°C, −0.7 mV/°C, −0.2 mV/°C, , 1000, 500, , 10, , Reverse current (nA), , Forward current (mA), , 100, , Temperature, coefficient, , 1, T = 100°C, T = 25°C, T = −50°C, , .1, , 0.1, , 0, , 100, 50, , 2301, 2302, 2305, 10, , 100 200 300 400 500 600 700, , 2900, 2303, , 0, , Forward voltage (mV), , 5, , 10, , 15, , Reverse voltage (V), , I-V Curve Showing Typical Temperature Variation for 5082-2300, Series Schottky Diodes., , 5082-2300 Series Typical, Reverse Current vs. Reverse, Voltage at TA = 25°C., , (a), , (b), , 1.2, , Capacitance (pF), , 1.0, 0.8, 0.6, , 2900, 2303, , 0.4, , 2301, 2302, 2305, , 0.2, 0, , 0, , 4, , 8, , 12, , 16, , 20, , VR −Reverse voltage (V), 5082-2300 Series Typical, Capacitance vs. Reverse, Voltage at TA = 25°C., , Figure 20.6 Characteristic curves for HewlettPackard 5082-2300 series of general-purpose, Schottky barrier diodes. (Courtesy Hewlett-Packard, Corporation.), , (c), , 20.3 VARACTOR (VARICAP) DIODES, Varactor [also called varicap, VVC (voltage-variable capacitance), or tuning] diodes, are semiconductor, voltage-dependent, variable capacitors. Their mode of operation, depends on the capacitance that exists at the p-n junction when the element is reversebiased. Under reverse-bias conditions, it was established that there is a region of uncovered charge on either side of the junction that together the regions make up the, depletion region and define the depletion width Wd. The transition capacitance (CT), established by the isolated uncovered charges is determined by, A, CT , Wd, 814, , Chapter 20, , Other Two-Terminal Devices, , (20.1)
Page 841 :
where is the permittivity of the semiconductor materials, A the p-n junction area,, and Wd the depletion width., As the reverse-bias potential increases, the width of the depletion region increases,, which in turn reduces the transition capacitance. The characteristics of a typical commercially available varicap diode appear in Fig. 20.7. Note the initial sharp decline, in CT with increase in reverse bias. The normal range of VR for VVC diodes is limited to about 20 V. In terms of the applied reverse bias, the transition capacitance is, given approximately by, K, CT n, (VT VR), , (20.2), , where K constant determined by the semiconductor material and construction, technique, VT knee potential as defined in Section 1.6, VR magnitude of the applied reverse-bias potential, n 12 for alloy junctions and 13 for diffused junctions, , Figure 20.7 Varicap characteristics:, C (pF) versus VR., , In terms of the capacitance at the zero-bias condition C(0), the capacitance as a, function of VR is given by, C(0), CT (VR) n, (1 VR/VT), , (20.3), , The symbols most commonly used for the varicap diode and a first approximation for its equivalent circuit in the reverse-bias region are shown in Fig. 20.8. Since, , Figure 20.8, (b) symbols., , Varicap diode: (a) equivalent circuit in the reverse-bias region;, , 20.3, , Varactor (Varicap) Diodes, , 815
Page 842 :
we are in the reverse-bias region, the resistance in the equivalent circuit is very large, in magnitude—typically 1 M or larger—while RS, the geometric resistance of the, diode, is, as indicated in Fig. 20.8, very small. The magnitude of CT will vary from, about 2 to 100 pF depending on the varicap considered. To ensure that RR is as large, (for minimum leakage current) as possible, silicon is normally used in varicap diodes., The fact that the device will be employed at very high frequencies requires that we, include the inductance LS even though it is measured in nanohenries. Recall that, XL 2 fL and a frequency of 10 GHz with LS 1 nH will result in an XLS , 2 fL (6.28)(1010 Hz)(109 F) 62.8 . There is obviously, therefore, a frequency, limit associated with the use of each varicap diode., Assuming the proper frequency range and a low value of RS and XLS compared to, the other series elements, then the equivalent circuit for the varicap of Fig. 20.8a can, be replaced by the variable capacitor alone. The complete data sheet and its characteristic curves appear in Figs. 20.9 and 20.10, respectively. The C3/C25 ratio in Fig. 20.9, , BB 139, VHF/FM VARACTOR DIODE, DIFFUSED SILICON PLANAR, • C3/C25 . . . 5.0-6.5, • MATCHED SETS (Note 2), , DC-35 OUTLINE, , ABSOLUTE MAXIMUM RATINGS (Note 1), , 1.0, (25.40) MIN, , Temperatures, Storage Temperature Range, Maximum Junction Operating Temperature, Lead Temperature, , −55°C to +150°C, +150°C, +260°C, , Maximum Voltage, WIV, Working Inverse Voltage, , 0.180 (4.57), 0.140 (3.56), , 30 V, , 0.021 (0.533), 0.019 (0.483) DIA, , 0.075 (1.91), 0.060 (1.52) DIA, , NOTES:, Copper clad steel leads, tin plated, Gold plated leads available, Hermetically sealed glass package, Package weight is 0.14 gram, , ELECTRICAL CHARACTERISTICS (25°C Ambient Temperature unless otherwise noted), SYMBOL, BV, IR, , CHARACTERISTIC, Breakdown Voltage, Reverse Current, , C, , Capacitance, , C3/C25, Q, RS, LS, fo, , Capacitance Ratio, Figure of Merit, Series Resistance, Series Inductance, Series Resonant Frequency, , MIN, 30, , 4.3, 5.0, , TYP, 10, 0.1, 29, 5.1, 5.7, 150, 0.35, 2.5, 1.4, , MAX UNITS, V, nA, 50, µA, 0.5, pF, pF, 6.0, 6.5, Ω, nH, GHz, , TEST CONDITIONS, IR = 100 µA, VR = 28 V, VR = 28 V, TA = 60°C, VR = 3.0 V, f = 1 MHz, VR = 25 V, f = 1 MHz, VR = 3 V/25 V, f = 1 MHz, VR = 3.0 V, f = 100 MHz, C = 10 pF, f = 600 MHz, 1.5 mm from case, VR = 25 V, , NOTES;, 1. These ratings are limiting values above which the serviceability of the diodes may be impaired., 2. The capacitance diffrence between any two diodes in one set is less than 3% over the reverse voltage range of 0.5 V to 28 V, , Figure 20.9 Electrical characteristics for a VHF/FM Fairchild varactor diode., (Courtesy Fairchild Camera and Instrument Corporation.), , 816, , Chapter 20, , Other Two-Terminal Devices
Page 843 :
Figure 20.10 Characteristic curves for a VHF/FM Fairchild varactor diode., (Courtesy Fairchild Camera and Instrument Corporation.), , is the ratio of capacitance levels at reverse-bias potentials of 3 and 25 V. It provides a, quick estimate of how much the capacitance will change with reverse-bias potential., The figure of merit is a quantity of consideration in the application of the device and is, a measure of the ratio of energy stored by the capacitive device per cycle to the energy, dissipated (or lost) per cycle. Since energy loss is seldom considered a positive attribute,, the higher its relative value the better. The resonant frequency of the device is deterL, C and affects the range of application of the device., mined by fo 1/2 , In Fig. 20.10, most quantities are self-explanatory. However, the capacitance temperature coefficient is defined by, C, TCC , C0(T1 T0), , 100%, , %/°C, , (20.4), , where C is the change in capacitance due to the temperature change T1 T0 and, C0 is the capacitance at T0 for a particular reverse-bias potential. For example, Fig., 20.9 indicates that C0 29 pF with VR 3 V and T0 25°C. A change in capacitance C could then be determined using Eq. (20.4) simply by substituting the new, temperature T1 and the TCC as determined from the graph ( 0.013). At a new VR,, the value of TCC would change accordingly. Returning to Fig. 20.9, note that the maximum frequency appearing is 600 MHz. At this frequency,, 20.3, , Varactor (Varicap) Diodes, , 817
Page 844 :
XL 2 fL (6.28)(600, , 106 Hz)(2.5, , 109 F) 9.42 , , normally a quantity of sufficiently small magnitude to be ignored., Some of the high-frequency (as defined by the small capacitance levels) areas of, application include FM modulators, automatic-frequency-control devices, adjustable, bandpass filters, and parametric amplifiers., In Fig. 20.11, the varactor diode is employed in a tuning network. That is, the resL, T, onant frequency of the parallel L-C combination is determined by fp 1/2 , 2C, (high-Q system) with the level of C T CT CC determined by the applied reversebias potential VDD. The coupling capacitor CC is present to provide isolation between, the shorting effect of L2 and the applied bias. The selected frequencies of the tuned, network are then passed on to the high input amplifier for further amplification., , Transformer, To high-input, impedance amplifier, CC, L1, , −VDD, , L2, CT, , Tank, circuit, , Figure 20.11, , Tuning network employing a varactor diode., , 20.4 POWER DIODES, There are a number of diodes designed specifically to handle the high-power and hightemperature demands of some applications. The most frequent use of power diodes, occurs in the rectification process, in which ac signals (having zero average value), are converted to ones having an average or dc level. As noted in Chapter 2, when used, in this capacity, diodes are normally referred to as rectifiers., The majority of the power diodes are constructed using silicon because of its, higher current, temperature, and PIV ratings. The higher current demands require that, the junction area be larger, to ensure that there is a low forward diode resistance. If, the forward resistance were too large, the I2R losses would be excessive. The current, capability of power diodes can be increased by placing two or more in parallel, and, the PIV rating can be increased by stacking the diodes in series., Various types of power diodes and their current rating have been provided in Fig., 20.12a. The high temperatures resulting from the heavy current require, in many cases,, that heat sinks be used to draw the heat away from the element. A few of the various, types of heat sinks available are shown in Fig. 20.12b. If heat sinks are not employed,, stud diodes are designed to be attached directly to the chassis, which in turn will act, as the heat sink., 818, , Chapter 20, , Other Two-Terminal Devices
Page 845 :
Figure 20.12, Corporation.), , Power diodes and heat sinks. (Courtesy International Rectifier, , 20.5 TUNNEL DIODES, The tunnel diode was first introduced by Leo Esaki in 1958. Its characteristics, shown, in Fig. 20.13, are different from any diode discussed thus far in that it has a negativeresistance region. In this region, an increase in terminal voltage results in a reduction, in diode current., The tunnel diode is fabricated by doping the semiconductor materials that will, form the p-n junction at a level one hundred to several thousand times that of a typical semiconductor diode. This will result in a greatly reduced depletion region, of, the order of magnitude of 106 cm, or typically about 1100 the width of this region for, a typical semiconductor diode. It is this thin depletion region that many carriers can, “tunnel” through, rather than attempt to surmount, at low forward-bias potentials that, accounts for the peak in the curve of Fig. 20.13. For comparison purposes, a typical, , Figure 20.13 Tunnel diode, characteristics., , 20.5, , Tunnel Diodes, , 819
Page 846 :
semiconductor diode characteristic has been superimposed on the tunnel-diode characteristic of Fig. 20.13., This reduced depletion region results in carriers “punching through” at velocities, that far exceed those available with conventional diodes. The tunnel diode can therefore be used in high-speed applications such as in computers, where switching times, in the order of nanoseconds or picoseconds are desirable., You will recall from Section 1.14 that an increase in the doping level will drop, the Zener potential. Note the effect of a very high doping level on this region in Fig., 20.13. The semiconductor materials most frequently used in the manufacture of tunnel diodes are germanium and gallium arsenide. The ratio IP/IV is very important for, computer applications. For germanium, it is typically 101, while for gallium arsenide,, it is closer to 201., The peak current, IP, of a tunnel diode can vary from a few microamperes to several hundred amperes. The peak voltage, however, is limited to about 600 mV. For, this reason, a simple VOM with an internal dc battery potential of 1.5 V can severely, damage a tunnel diode if applied improperly., The tunnel diode equivalent circuit in the negative-resistance region is provided, in Fig. 20.14, with the symbols most frequently employed for tunnel diodes. The values for each parameter are for the 1N2939 tunnel diode whose specifications appear, in Table 20.1. The inductor LS is due mainly to the terminal leads. The resistor RS is, due to the leads, ohmic contact at the lead–semiconductor junction, and the semiconductor materials themselves. The capacitance C is the junction diffusion capacitance, and the R is the negative resistance of the region. The negative resistance finds, application in oscillators to be described later., , Figure 20.14, , Tunnel diode: (a) equivalent circuit; (b) symbols., , TABLE 20.1 Specifications: Ge 1N2939, Minimum, Absolute maximum ratings (25°C), Forward current (55 to 100°C), Reverse current (55 to 100°C), Electrical characteristics (25°C)(18-in. leads), IP, IV, VP, VV, Reverse voltage (IR 1.0 mA), Forward peak point current voltage, Vfp, IP/IV, R, C, LS, RS, , 820, , Chapter 20, , Other Two-Terminal Devices, , Typical, , Maximum, , 5 mA, 10 mA, 0.9, 50, , 450, , 1.0, 0.1, 60, 350, 500, 10, 152, 5, 6, 1.5, , 1.1 mA, 0.14 mA, 65, mV, mV, 30 mV, 600, mV, , 15, 4.0, , , pF, nH,
Page 847 :
Note the lead length of 18 in. included in the specifications. An increase in this, length will cause LS to increase. In fact, it was given for this device that LS will vary, 1 to 12 nH, depending on lead length. At high frequencies (XLS 2 fLS), this factor, can take its toll., The fact that Vfp 500 mV (typ.) and Iforward (max.) 5 mA indicates that tunnel diodes are low-power devices [PD (0.5 V)(5 mA) 2.5 mW], which is also excellent for computer applications. A rendering of the device appears in Fig. 20.15., Although the use of tunnel diodes in present-day high-frequency systems has been, dramatically stalled by manufacturing techniques that suggest alternatives to the tunnel diode, its simplicity, linearity, low power drain, and reliability ensure its continued life and application. The basic construction of an advance design tunnel diode, appears in Fig. 20.16 with a photograph of the actual junction., , Figure 20.15 A Ge IN2939, tunnel diode. (Courtesy Powerex,, Inc.), , (b), Figure 20.16 Tunnel diode: (a) construction; (b) photograph. (Courtesy COM, SAT Technical Review, P. F. Varadi and T. D. Kirkendall.), , In Fig. 20.17, the chosen supply voltage and load resistance have defined a load, line that intersects the tunnel diode characteristics at three points. Keep in mind that, the load line is determined solely by the network and the characteristics by the device. The intersections at a and b are referred to as stable operating points, due to the, positive resistance characteristic. That is, at either of these operating points, a slight, disturbance in the network will not set the network into oscillations or result in a significant change in the location of the Q-point. For instance, if the defined operating, point is at b, a slight increase in supply voltage E will move the operating point up, the curve since the voltage across the diode will increase. Once the disturbance has, , Figure 20.17, , Tunnel diode and resulting load line., , 20.5, , Tunnel Diodes, , 821
Page 848 :
passed, the voltage across the diode and the associated diode current will return to, the levels defined by the Q-point at b. The operating point defined by c is an unstable one because a slight change in the voltage across or current through the diode will, result in the Q-point moving to either a or b. For instance, the slightest increase in E, will cause the voltage across the tunnel diode to increase above its level at c. In this, region, however, an increase in VT will cause a decrease in IT and a further increase, in VT. This increased level in VT will result in a continuing decrease in IT, and so on., The result is an increase in VT and a change in IT until the stable operating point at, b is established. A slight drop in supply voltage would result in a transition to stability at point a. In other words, point c can be defined as the operating point using, the load-line technique, but once the system is energized, it will eventually stabilize, at location a or b., The availability of a negative resistance region can be put to good use in the design of oscillators, switching networks, pulse generators, and amplifiers., In Fig. 20.18a, a negative-resistance oscillator was constructed using a tunnel, diode. The choice of network elements is designed to establish a load line such as, shown in Fig. 20.18b. Note that the only intersection with the characteristics is in the, unstable negative-resistance region—a stable operating point is not defined. When the, power is turned on, the terminal voltage of the supply will build up from 0 V to a final value of E volts. Initially, the current IT will increase from 0 mA to IP, resulting, in a storage of energy in the inductor in the form of a magnetic field. However, once, IP is reached, the diode characteristics suggest that the current IT must now decrease, with increase in voltage across the diode. This is a contradiction to the fact that, , IT, , 1, , R, , L, , +, , iT, , 2, , Q-point, , vT, , E, , 4, , –, , 0, , 3, vT, , E, , (a), , (b), , υT, 2, , 2, , 3, , 1, , 4, , 3, 4, , 1, , 1, t, , (c), , 822, , Figure 20.18, , Negative-resistance oscillator., , Chapter 20, , Other Two-Terminal Devices
Page 849 :
E ITR IT (RT), E IT (R RT), less less, If both elements of the equation above were to decrease, it would be impossible for, the supply voltage to reach its set value. Therefore, for the current IT to continue rising,, the point of operation must shift from point 1 to point 2. However, at point 2, the voltage VT has jumped to a value greater than the applied voltage (point 2 is to the right of, any point on the network load line). To satisfy Kirchhoff’s voltage law, the polarity of, the transient voltage across the coil must reverse and the current begin to decrease as, shown from 2 to 3 on the characteristics. When VT drops to VV, the characteristics suggest that the current IT will begin to increase again. This is unacceptable since VT is still, more than the applied voltage and the coil is discharging through the series circuit. The, point of operation must shift to point 4 to permit a continuation of the decrease in IT., However, once at point 4, the potential levels are such that the tunnel current can again, increase from 0 mA to IP as shown on the characteristics. The process will repeat itself, again and again, never settling in on the operating point defined for the unstable region., The resulting voltage across the tunnel diode appears in Fig. 20.18c and will continue, as long as the dc supply is energized. The result is an oscillatory output established by, a fixed supply and a device with a negative-resistance characteristic. The waveform of, Fig. 20.18c has extensive application in timing and computer logic circuitry., A tunnel diode can also be used to generate a sinusoidal voltage using simply a, dc supply and a few passive elements. In Fig. 20.19a, the closing of the switch will, result in a sinusoidal voltage that will decrease in amplitude with time. Depending on, the elements employed, the time period can be from one almost instantaneous to one, measurable in minutes using typical parameter values. This damping of the oscillatory output with time is due to the dissipative characteristics of the resistive elements., By placing a tunnel diode in series with the tank circuit as shown in Fig. 20.19c, the, negative resistance of the tunnel diode will offset the resistive characteristics of the, tank circuit, resulting in the undamped response appearing in the same figure. The, , , , , , and, , E, E, , υC, , υC, , Rl, , Rl, C, , C, t, , L, , (b), , t, , L, , (c), , "Tank", circuit, (a), , Figure 20.19, , Sinusoidal oscillator., , 20.5, , Tunnel Diodes, , 823
Page 850 :
design must continue to result in a load line that will intersect the characteristics only, in the negative-resistance region. In another light, the sinusoidal generator of Fig., 20.19 is simply an extension of the pulse oscillator of Fig. 20.18, with the addition, of the capacitor to permit an exchange of energy between the inductor and the capacitor during the various phases of the cycle depicted in Fig. 20.18b., , 20.6 PHOTODIODES, The interest in light-sensitive devices has been increasing at an almost exponential, rate in recent years. The resulting field of optoelectronics will be receiving a great, deal of research interest as efforts are made to improve efficiency levels. Through the, advertising media, the layperson has become quite aware that light sources offer a, unique source of energy. This energy, transmitted as discrete packages called photons,, has a level directly related to the frequency of the traveling light wave as determined, by the following equation:, W hf, , joules, , (20.5), , where , h is called Planck’s constant and is equal to 6.624 1034 joule-second. It, clearly states that since , h is a constant, the energy associated with incident light, waves is directly related to the frequency of the traveling wave., The frequency is, in turn, directly related to the wavelength (distance between successive peaks) of the traveling wave by the following equation:, v, , f, , (20.6), , wavelength, meters, v velocity of light, 3 108 m/s, f frequency of the traveling wave, hertz, The wavelength is usually measured in angstrom units (Å) or micrometers (m),, where, where, , 1 Å 1010 m, , 1 m 106 m, , and, , The wavelength is important because it will determine the material to be used in, the optoelectronic device. The relative spectral response for Ge, Si, and selenium is, provided in Fig. 20.20. The visible-light spectrum has also been included with an indication of the wavelength associated with the various colors., The number of free electrons generated in each material is proportional to the intensity of the incident light. Light intensity is a measure of the amount of luminous, flux falling in a particular surface area. Luminous flux is normally measured in lumens (lm) or watts. The two units are related by, 1 lm 1.496, , 1010 W, , The light intensity is normally measured in lm/ft2, footcandles (fc), or W/m2, where, 1 lm/ft2 1 fc 1.609, , 109 W/m2, , The photodiode is a semiconductor p-n junction device whose region of operation is limited to the reverse-bias region. The basic biasing arrangement, construction,, and symbol for the device appear in Fig. 20.21., Recall from Chapter 1 that the reverse saturation current is normally limited to a, few microamperes. It is due solely to the thermally generated minority carriers in the, 824, , Chapter 20, , Other Two-Terminal Devices
Page 851 :
Figure 20.20 Relative spectral response for Si, Ge, and selenium as compared to, the human eye., , n- and p-type materials. The application of light to the junction will result in a transfer of energy from the incident traveling light waves (in the form of photons) to the, atomic structure, resulting in an increased number of minority carriers and an increased level of reverse current. This is clearly shown in Fig. 20.22 for different intensity levels. The dark current is that current that will exist with no applied illumination. Note that the current will only return to zero with a positive applied bias equal, to VT. In addition, Fig. 20.21 demonstrates the use of a lens to concentrate the light, on the junction region. Commercially available photodiodes appear in Fig. 20.23., , Figure 20.21 Photodiode: (a), basic biasing arrangement and, construction; (b) symbol., , Figure 20.22 Photodiode, characteristics., , 20.6 Photodiodes, , 825
Page 852 :
Figure 20.23, , Photodiodes (Courtesy EG&G VACTEC, Inc.), , The almost equal spacing between the curves for the same increment in luminous, flux reveals that the reverse current and luminous flux are almost linearly related. In, other words, an increase in light intensity will result in a similar increase in reverse, current. A plot of the two to show this linear relationship appears in Fig. 20.24 for a, fixed voltage V of 20 V. On the relative basis, we can assume that the reverse current is essentially zero in the absence of incident light. Since the rise and fall times, (change-of-state parameters) are very small for this device (in the nanosecond range),, the device can be used for high-speed counting or switching applications. Returning, to Fig. 20.20, we note that Ge encompasses a wider spectrum of wavelengths than Si., This would make it suitable for incident light in the infrared region as provided by, lasers and IR (infrared) light sources, to be described shortly. Of course, Ge has a, higher dark current than silicon, but it also has a higher level of reverse current. The, level of current generated by the incident light on a photodiode is not such that it, could be used as a direct control, but it can be amplified for this purpose., , Figure 20.24 I (A) versus fc, (at V 20 V) for the photodiode, of Fig. 20.22., , 826, , Chapter 20, , Other Two-Terminal Devices
Page 853 :
In Fig. 20.25, the photodiode is employed in an alarm system. The reverse current I will continue to flow as long as the light beam is not broken. If interrupted,, I drops to the dark current level and sounds the alarm. In Fig. 20.26, a photodiode, is used to count items on a conveyor belt. As each item passes the light beam is broken, I drops to the dark current level and the counter is increased by one., , Figure 20.25, system., , Using a photodiode in an alarm, , Figure 20.26, operation., , Using a photodiode in a counter, , 20.7 PHOTOCONDUCTIVE CELLS, The photoconductive cell is a two-terminal semiconductor device whose terminal resistance will vary (linearly) with the intensity of the incident light. For obvious reasons, it is frequently called a photoresistive device. A typical photoconductive cell and, the most widely used graphical symbol for the device appear in Fig. 20.27., , (a), , (b), , Figure 20.27 Photoconductive, cell: (a) appearance; (b) symbol., [(a) Courtesy International, Rectifier Corporation.], , The photoconductive materials most frequently used include cadmium sulfide, (CdS) and cadmium selenide (CdSe). The peak spectral response of CdS occurs at, approximately 5100 Å and for CdSe at 6150 Å (note Fig. 20.20). The response time, of CdS units is about 100 ms, and 10 ms for CdSe cells. The photoconductive cell, does not have a junction like the photodiode. A thin layer of the material connected, between terminals is simply exposed to the incident light energy., 20.7, , Photoconductive Cells, , 827
Page 854 :
As the illumination on the device increases in intensity, the energy state of a larger, number of electrons in the structure will also increase because of the increased availability of the photon packages of energy. The result is an increasing number of relatively “free” electrons in the structure and a decrease in the terminal resistance. The, sensitivity curve for a typical photoconductive device appears in Fig. 20.28. Note the, linearity (when plotted using a log-log scale) of the resulting curve and the large, change in resistance (100 k → 100 ) for the indicated change in illumination., , Figure 20.28, , Photoconductive cell-terminal characteristics (GE type B425)., , One rather simple, but interesting, application of the device appears in Fig. 20.29., The purpose of the system is to maintain Vo at a fixed level even though Vi may fluctuate from its rated value. As indicated in the figure, the photoconductive cell, bulb,, and resistor all form part of this voltage-regulator system. If Vi should drop in magnitude for any number of reasons, the brightness of the bulb would also decrease. The, decrease in illumination would result in an increase in the resistance (R ) of the photoconductive cell to maintain Vo at its rate level as determined by the voltage-divider, rule, that is,, R Vi, Vo , R R1, , (20.7), , Figure 20.29 Voltage regulator, employing a photoconductive cell., , In an effort to demonstrate the wealth of material available on each device from, manufacturers, consider the CdS (cadmium sulfide) photoconductive cell described, in Fig. 20.30. Note again the concern with temperature and response time., 828, , Chapter 20, , Other Two-Terminal Devices
Page 855 :
100, 90, 80, , % Sensitivity, , 70, 60, 50, 40, 30, 20, 10, 0, 4000 Å, , 6000 Å, , 8000 Å 10,000 Å, , Wavelength (Å), , Variation of Conductance, With Temperature and Light, Footcandles, , 0.01, , 0.1, , 103, 98, 100, 98, 90, , 104, 102, 100, 102, 106, , Temperature, −25°C, 0, 25°C, 50°C, 75°C, , 1.0, , 10, , 100, , 104, 102, 100, 103, 108, , 102, 100, 100, 104, 109, , 106, 103, 100, 99, 104, , % Conductance, , Response Time Versus Light, Footcandles, , 0.01, , 0.1, , 1.0, , 10, , 100, , Rise (seconds), Decay (seconds), , 0.5, 0.125, , 0.095, 0.021, , 0.022, 0.005, , 0.005, 0.002, , 0.002, 0.001, , Figure 20.30 Characteristics of a Clairex CdS photoconductive cell. (Courtesy, Clairex Electronics.), , 20.8 IR EMITTERS, Infrared-emitting diodes are solid-state gallium arsenide devices that emit a beam of, radiant flux when forward-biased. The basic construction of the device is shown in, Fig. 20.31. When the junction is forward-biased, electrons from the n-region will recombine with excess holes of the p-material in a specially designed recombination, region sandwiched between the p- and n-type materials. During this recombination, process, energy is radiated away from the device in the form of photons. The generated photons will either be reabsorbed in the structure or leave the surface of the device as radiant energy, as shown in Fig. 20.31., The radiant flux in mW versus the dc forward current for a typical device appears, in Fig. 20.32. Note the almost linear relationship between the two. An interesting pattern for such devices is provided in Fig. 20.33. Note the very narrow pattern for de20.9 IR Emitters, , Figure 20.31 General structure, of a semiconductor IR-emitting, diode. (Courtesy RCA Solid State, Division.), , 829
Page 856 :
Figure 20.32 Typical radiant flux versus dc forward, current for an IR-emitting diode. (Courtesy RCA Solid, State Division.), , Figure 20.33 Typical radiant intensity patterns of RCA IRemitting diodes. (Courtesy RCA Solid State Division.), , vices with an internal collimating system. One such device appears in Fig. 20.34, with, its internal construction and graphical symbol. A few areas of application for such devices include card and paper-tape readers, shaft encoders, data-transmission systems,, and intrusion alarms., , Figure 20.34 RCA IR-emitting, diode: (a) construction; (b) photo;, (c) symbol. (Courtesy RCA Solid, State Division.), , 830, , Approx. 2X, actual size, (b), , Chapter 20, , Other Two-Terminal Devices
Page 857 :
20.9 LIQUID-CRYSTAL DISPLAYS, The liquid-crystal display (LCD) has the distinct advantage of having a lower power, requirement than the LED. It is typically in the order of microwatts for the display,, as compared to the same order of milliwatts for LEDs. It does, however, require an, external or internal light source and is limited to a temperature range of about 0° to, 60°C. Lifetime is an area of concern because LCDs can chemically degrade. The types, receiving the major interest today are the field-effect and dynamic-scattering units., Each will be covered in some detail in this section., A liquid crystal is a material (normally organic for LCDs) that will flow like a, liquid but whose molecular structure has some properties normally associated with, solids. For the light-scattering units, the greatest interest is in the nematic liquid crystal, having the crystal structure shown in Fig. 20.35. The individual molecules have, a rodlike appearance as shown in the figure. The indium oxide conducting surface is, transparent, and under the condition shown in the figure, the incident light will simply pass through and the liquid-crystal structure will appear clear. If a voltage (for, commercial units the threshold level is usually between 6 and 20 V) is applied across, the conducting surfaces, as shown in Fig. 20.36, the molecular arrangement is disturbed, with the result that regions will be established with different indices of refraction. The incident light is therefore reflected in different directions at the interface between regions of different indices of refraction (referred to as dynamic, scattering—first studied by RCA in 1968) with the result that the scattered light has, a frosted-glass appearance. Note in Fig. 20.36, however, that the frosted look occurs, , Figure 20.35, , Nematic liquid crystal with no applied bias., , Figure 20.36, , Nematic liquid crystal with applied bias., , 20.9, , Liquid-Crystal Displays, , 831
Page 858 :
Figure 20.37, digit display., , LCD eight-segment, , only where the conducting surfaces are opposite each other and the remaining areas, remain translucent., A digit on an LCD display may have the segment appearance shown in Fig. 20.37., The black area is actually a clear conducting surface connected to the terminals below for external control. Two similar masks are placed on opposite sides of a sealed, thick layer of liquid-crystal material. If the number 2 were required, the terminals 8,, 7, 3, 4, and 5 would be energized, and only those regions would be frosted while the, other areas would remain clear., As indicated earlier, the LCD does not generate its own light but depends on an, external or internal source. Under dark conditions, it would be necessary for the unit, to have its own internal light source either behind or to the side of the LCD. During, the day, or in lighted areas, a reflector can be put behind the LCD to reflect the light, back through the display for maximum intensity. For optimum operation, current watch, manufacturers are using a combination of the transmissive (own light source) and reflective modes called transflective., The field-effect or twisted nematic LCD has the same segment appearance and, thin layer of encapsulated liquid crystal, but its mode of operation is very different., Similar to the dynamic-scattering LCD, the field-effect LCD can be operated in the, reflective or transmissive mode with an internal source. The transmissive display appears in Fig. 20.38. The internal light source is on the right, and the viewer is on the, left. This figure is most noticeably different from Fig. 20.35 in that there is an addition of a light polarizer. Only the vertical component of the entering light on the right, can pass through the vertical-light polarizer on the right. In the field-effect LCD, either the clear conducting surface to the right is chemically etched or an organic film, is applied to orient the molecules in the liquid crystal in the vertical plane, parallel, to the cell wall. Note the rods to the far right in the liquid crystal. The opposite conducting surface is also treated to ensure that the molecules are 90° out of phase in the, direction shown (horizontal) but still parallel to the cell wall. In between the two walls, of the liquid crystal there is a general drift from one polarization to the other, as shown, in the figure. The left-hand light polarizer is also such that it permits the passage of, only the vertically polarized incident light. If there is no applied voltage to the conducting surfaces, the vertically polarized light enters the liquid-crystal region and follows the 90° bending of the molecular structure. Its horizontal polarization at the lefthand vertical light polarizer does not allow it to pass through, and the viewer sees a, uniformly dark pattern across the entire display. When a threshold voltage is applied, (for commercial units from 2 to 8 V), the rodlike molecules align themselves with the, field (perpendicular to the wall) and the light passes directly through without the 90°, shift. The vertically incident light can then press directly through the second vertically polarized screen, and a light area is seen by the viewer. Through proper excita-, , Figure 20.38 Transmissive, field-effect LCD with no applied, bias., , 832, , Chapter 20, , Other Two-Terminal Devices
Page 859 :
tion of the segments of each digit, the pattern will appear as shown in Fig. 20.39. The, reflective-type field-effect LCD is shown in Fig. 20.40. In this case, the horizontally, polarized light at the far left encounters a horizontally polarized filter and passes, through to the reflector, where it is reflected back into the liquid crystal, bent back, to the other vertical polarization, and returned to the observer. If there is no applied, voltage, there is a uniformly lit display. The application of a voltage results in a vertically incident light encountering a horizontally polarized filter at the left, which it, will not be able to pass through and will be reflected. A dark area results on the crystal, and the pattern as shown in Fig. 20.41 appears., , Figure 20.40 Reflective field-effect, LCD with no applied bias., , Figure 20.39 Reflective-type, LCD. (Courtesy RCA Solid State, Division.), , Figure 20.41 Transmissive-type, LCD. (Courtesy RCA Solid State, Division.), , Field-effect LCDs are normally used when a source of energy is a prime factor, (e.g., in watches, portable instrumentation, etc.) since they absorb considerably less, power than the light-scattering types—the microwatt range compared to the lowmilliwatt range. The cost is typically higher for field-effect units, and their height is, limited to about 2 in. while light-scattering units are available up to 8 in. in height., A further consideration in displays is turn-on and turn-off time. LCDs are characteristically much slower then LEDs. LCDs typically have response times in the, range 100 to 300 ms, while LEDs are available with response times below 100 ns., However, there are numerous applications, such as in a watch, where the difference, between 100 ns and 100 ms (110 of a second) is of little consequence. For such applications, the lower power demand of LCDs is a very attractive characteristic. The lifetime of LCD units is steadily increasing beyond the 10,000 hours limit. Since the, color generated by LCD units is dependent on the source of illumination, there is a, greater range of color choice., , 20.10 SOLAR CELLS, In recent years, there has been increasing interest in the solar cell as an alternative, source of energy. When we consider that the power density received from the sun at, sea level is about 100 mW/cm2 (1 kW/m2), it is certainly an energy source that requires further research and development to maximize the conversion efficiency from, solar to electrical energy., The basic construction of a silicon p-n junction solar cell appears in Fig. 20.42., As shown in the top view, every effort is made to ensure that the surface area perpendicular to the sun is a maximum. Also, note that the metallic conductor connected, to the p-type material and the thickness of the p-type material are such that they ensure that a maximum number of photons of light energy will reach the junction. A, photon of light energy in this region may collide with a valence electron and impart, to it sufficient energy to leave the parent atom. The result is a generation of free electrons and holes. This phenomenon will occur on each side of the junction. In the, 20.10, , Solar Cells, , 833
Page 860 :
Figure 20.42 Solar cell: (a), cross section; (b) top view., , p-type material, the newly generated electrons are minority carriers and will move, rather freely across the junction as explained for the basic p-n junction with no applied bias. A similar discussion is true for the holes generated in the n-type material., The result is an increase in the minority-carrier flow, which is opposite in direction, to the conventional forward current of a p-n junction. This increase in reverse current, is shown in Fig. 20.43. Since V 0 anywhere on the vertical axis and represents a, short-circuit condition, the current at this intersection is called the short-circuit current and is represented by the notation ISC. Under open-circuit conditions (id 0),, the photovoltaic voltage VOC will result. This is a logarithmic function of the illumination, as shown in Fig. 20.44. VOC is the terminal voltage of a battery under no-load, (open-circuit) conditions. Note, however, in the same figure that the short-circuit current is a linear function of the illumination. That is, it will double for the same increase in illumination ( fC1 and 2fC1 in Fig. 20.44) while the change in VOC is less for, this region. The major increase in VOC occurs for lower-level increases in illumination. Eventually, a further increase in illumination will have very little effect on VOC,, although ISC will increase, causing the power capabilities to increase., Selenium and silicon are the most widely used materials for solar cells, although, gallium arsenide, indium arsenide, and cadmium sulfide, among others, are also used., , Figure 20.43 Short-circuit current and open-circuit voltage versus light intensity for a solar cell., , 834, , Chapter 20, , Figure 20.44, cell., , Other Two-Terminal Devices, , VOC and ISC versus illumination for a solar
Page 861 :
The wavelength of the incident light will affect the response of the p-n junction to, the incident photons. Note in Fig. 20.45 how closely the selenium cell response curve, matches that of the eye. This fact has widespread application in photographic equipment such as exposure meters and automatic exposure diaphragms. Silicon also overlaps the visible spectrum but has its peak at the 0.8 m (8000 Å) wavelength, which, is in the infrared region. In general, silicon has a higher conversion efficiency, greater, stability, and is less subject to fatigue. Both materials have excellent temperature characteristics. That is, they can withstand extreme high or low temperatures without a, significant drop-off in efficiency. Typical solar cells, with their electrical characteristics, appear in Fig. 20.46., % Response, 100, , 75, Selenium, , Silicon, , 50, Visible, spectrum, 25, , 0, , 2000, , 4000, , 6000, , 8000, , 10,000 12,000, , λ (Å), , Figure 20.45 Spectral response, of Se, Si, and the naked eye., Figure 20.46 Typical solar cells, and their electrical characteristics., (Courtesy EG&G VACTEC, Inc.), , 20.10, , Solar Cells, , 835
Page 862 :
A very recent innovation in the use of solar cells appears in Fig. 20.47. The series arrangement of solar cells permits a voltage beyond that of a single element. The, performance of a typical four-cell array appears in the same figure. At a current of, approximately 2.6 mA, the output voltage is about 1.6 V, resulting in an output power, of 4.16 mW. The Schottky barrier diode is included to prevent battery current drain, through the power converter. That is, the resistance of the Schottky diode is so high, to charge flowing down through ( to ) the power converter that it will appear as, an open circuit to the rechargeable battery and not draw current from it., , Figure 20.47 International Rectifier four-cell array: (a) appearance; (b) characteristics. (Courtesy International Rectifier Corporation.), , It might be of interest to note that the Lockheed Missiles and Space Company, is working on a grant from the National Aeronautics and Space Administration to, develop a massive solar-array wing for the space shuttle. The wing will measure, 13.5 ft by 105 ft when extended and will contain 41 panels, each carrying 3060 silicon solar cells. The wing can generate a total of 12.5 kW of electrical power., The efficiency of operation of a solar cell is determined by the electrical power, output divided by the power provided by the light source. That is,, Po(electrical), , , Pi(light energy), , Pmax(device), 100% , (area in cm2)(100 mW/cm2), , 100%, , (20.8), , Typical levels of efficiency range from 10% to 40%—a level that should improve, measurably if the present interest continues. A typical set of output characteristics for, silicon solar cells of 10% efficiency with an active area of 1 cm2 appears in Fig. 20.48., Note the optimum power locus and the almost linear increase in output current with, luminous flux for a fixed voltage., 836, , Chapter 20, , Other Two-Terminal Devices
Page 863 :
Figure 20.48 Typical output, characteristics for silicon solar cells, of 10% efficiency having an active, area of 1 cm2. Cell temperature, is 30°C., , 20.11 THERMISTORS, The thermistor is, as the name implies, a temperature-sensitive resistor; that is, its terminal resistance is related to its body temperature. It is not a junction device and is, constructed of Ge, Si, or a mixture of oxides of cobalt, nickel, strontium, or manganese. The compound employed will determine whether the device has a positive or, negative temperature coefficient., The characteristics of a representative thermistor with a negative temperature, coefficient are provided in Fig. 20.49, with the commonly used symbol for the device. Note in particular that at room temperature (20°C) the resistance of the thermistor is approximately 5000 , while at 100°C (212°F) the resistance has decreased to, 100 . A temperature span of 80°C has therefore resulted in a 501 change in resis-, , Figure 20.49 Thermistor:, (a) typical set of characteristics;, (b) symbol., , 20.11, , Thermistors, , 837
Page 864 :
tance. It is typically 3% to 5% per degree change in temperature. There are fundamentally two ways to change the temperature of the device: internally and externally., A simple change in current through the device will result in an internal change in, temperature. A small applied voltage will result in a current too small to raise the, body temperature above that of the surroundings. In this region, as shown in Fig., 20.50, the thermistor will act like a resistor and have a positive temperature coefficient. However, as the current increases, the temperature will rise to the point where, the negative temperature coefficient will appear as shown in Fig. 20.50. The fact that, the rate of internal flow can have such an effect on the resistance of the device introduces a wide vista of applications in control, measuring techniques, and so on. An, external change would require changing the temperature of the surrounding medium, or immersing the device in a hot or cold solution., , 10, 6, , 10, 7, , 10, , 1, , 1, 0., , 100, , Resistance (Ω), 10, 8, , Power (mW), , Potential (V), , Ambient 0°C, 25°C, , 10, , 60°C, 1.0, , 0.1, 10−7, , 10−6, , 10−5, , 10−4, , Current (A), , 10−3, , Figure 20.50 Steady-state, voltage–current characteristics, of Fenwal Electronics BK65VI, Thermistor. (Courtesy Fenwal, Electronics, Incorporated.), , A photograph of a number of commercially available thermistors is provided in, Fig. 20.51. A simple temperature-indicating circuit appears in Fig. 20.52. Any increase, in the temperature of the surrounding medium will result in a decrease in the resistance of the thermistor and an increase in the current IT. An increase in IT will, , Figure 20.51 Various types of thermistors: (1) beads; (2) glass probes; (3), iso-curve interchangeable probes and beads; (4) disks; (5) washers; (6) rods;, (7) specially mounted beads; (8) vacuum and gas-filled probes; (9) special, probe assemblies. (Courtesy Fenwal Electronics, Incorporated.), , 838, , Chapter 20, , Other Two-Terminal Devices
Page 865 :
Figure 20.52, circuit., , Temperature-indicating, , produce an increased movement deflection, which when properly calibrated will, accurately indicate the higher temperature. The variable resistance was added for, calibration purposes., , PROBLEMS, , § 20.2 Schottky Barrier (Hot-Carrier) Diodes, 1. (a) Describe in your own words how the construction of the hot-carrier diode is significantly, different from the conventional semiconductor diode., (b) In addition, describe its mode of operation., 2. (a) Consult Fig. 20.2. How would you compare the dynamic resistances of the diodes in the, forward-bias regions?, (b) How do the levels of Is and VZ compare?, 3. Referring to Fig. 20.5, how does the maximum surge current IFSM relate to the average rectified forward current? Is it typically greater than 201? Why is it possible to have such high levels of current? What noticeable difference is there in construction as the current rating increases?, 4. Referring to Fig. 20.6a, at what temperature is the forward voltage drop 300 mV at a current, of 1 mA? Which current levels have the highest levels of temperature coefficients? Assume a, linear progression between temperature levels., *, , 5. For the curve of Fig. 20.6b denoted 2900/2303, determine the percent change in IR for a change, in reverse voltage from 5 to 10 V. At what reverse voltage would you expect to reach a reverse, current of 1 A? Note the log scale for IR ., , *, , 6. Determine the percent change in capacitance between 0 and 2 V for the 2900/2303 curve of, Fig. 20.6c. How does this compare to the change between 8 and 10 V?, , §, , 20.3 Varactor (Varicap) Diodes, , 7. (a) Determine the transition capacitance of a diffused junction varicap diode at a reverse potential of 4.2 V if C(0) 80 pF and VT 0.7 V., (b) From the information of part (a), determine the constant K in Eq. (20.2)., 8. (a) For a varicap diode having the characteristics of Fig. 20.7, determine the difference in capacitance between reverse-bias potentials of 3 and 12 V., (b) Determine the incremental rate of change ( C/ Vr) at V 8 V. How does this value compare with the incremental change determined at 2 V?, *, , 9. (a) The resonant frequency of a series RLC network is determined by f0 1/(2 L, C, ). Using, the value of f0 and LS provided in Fig. 20.9, determine the value of C., (b) How does the value calculated in part (a) compare with that determined by the curve in, Fig. 20.10 at VR 25 V?, , 10. Referring to Fig. 20.10, determine the ratio of capacitance at VR 3 V to VR 25 V and compare to the value of C3/C25 given in Fig. 20.9 (maximum 6.5)., 11. Determine T1 for a varactor diode if C0 22 pF, TCC 0.02%/°C, and C 0.11 pF due to, an increase in temperature above T0 25°C., 12. What region of VR would appear to have the greatest change in capacitance per change in reverse voltage for the BB139 varactor diode of Figs. 20.9 and 20.10? Be aware that the scales, are nonlinear., *13., , If Q XL/R 2 fL/R, determine the figure of merit (Q) at 600 MHz using the fact that, RS 0.35 and LS 2.5 nH. Comment on the change in Q with frequency and the support, or nonsupport of the curve in Fig. 20.10., Problems, , 839
Page 866 :
§, , 20.4 Power Diodes, , 14. Consult a manufacturer’s data book and compare the general characteristics of a high-power, device (10 A) to a low-power unit (100 mA). Is there a significant change in the data and, characteristics provided? Why?, , §, , 20.5 Tunnel Diodes, , 15. What are the essential differences between a semiconductor junction diode and a tunnel diode?, *16. Note in the equivalent circuit of Fig. 20.14 that the capacitor appears in parallel with the negative resistance. Determine the reactance of the capacitor at 1 MHz and 100 MHz if C 5 pF,, and determine the total impedance of the parallel combination (with R 152 ) at each frequency. Is the magnitude of the inductive reactance anything to be overly concerned about at, either of these frequencies if LS 6 nH?, *17. Why do you believe the maximum reverse current rating for the tunnel diode can be greater, than the forward current rating? (Hint: Note the characteristics and consider the power rating.), 18. Determine the negative resistance for the tunnel diode of Fig. 20.13 between VT 0.1 V and, VT 0.3 V., 19. Determine the stable operating points for the network of Fig. 20.17 if E 2 V, R 0.39 k,, and the tunnel diode of Fig. 20.13 is employed. Use typical values from Table 20.1., *20. For E 0.5 V and R 51 , sketch vT for the network of Figure 20.18 and the tunnel diode, of Fig. 20.13., 21. Determine the frequency of oscillation for the network of Fig. 20.19 if L 5 mH, Rl 10 ,, and C 1 F., , §, , 20.6 Photodiodes, , 22. Determine the energy associated with the photons of green light if the wavelength is 5000 Å., Give your answer in joules and electron volts., 23. (a) Referring to Fig. 20.20, what would appear to be the frequencies associated with the upper, and lower limits of the visible spectrum?, (b) What is the wavelength in microns associated with the peak relative response of silicon?, (c) If we define the bandwidth of the spectral response of each material to occur at 70% of its, peak level, what is the bandwidth of silicon?, 24. Referring to Fig. 20.22, determine I if V 30 V and the light intensity is 4, , 109 W/m2., , 25. (a) Which material of Fig. 20.20 would appear to provide the best response to yellow, red,, green, and infrared (less than 11,000 Å) light sources?, (b) At a frequency of 0.5 1015 Hz, which color has the maximum spectral response?, *26. Determine the voltage drop across the resistor of Fig. 20.21 if the incident flux is 3000 fc,, V 25 V, and R 100 k. Use the characteristics of Fig. 20.22., , §, , 20.7 Photoconductive Cells, , *27. What is the approximate rate of change of resistance with illumination for a photoconductive, cell with the characteristics of Fig. 20.28 for the ranges (a) 0.1 → 1 k, (b) 1 → 10 k, and, (c) 10 → k? (Note that this is a log scale.) Which region has the greatest rate of change in, resistance with illumination?, 28. What is the “dark current” of a photodiode?, 29. If the illumination on the photoconductive diode in Fig. 20.29 is 10 fc, determine the magnitude of Vi to establish 6 V across the cell if R1 is equal to 5 k. Use the characteristics of Fig., 20.28., *30. Using the data provided in Fig. 20.30, sketch a curve of percent conductance versus temperature for 0.01, 1.0, and 100 fc. Are there any noticeable effects?, *31. (a) Sketch a curve of rise time versus illumination using the data from Fig. 20.30., (b) Repeat part (a) for the decay time., (c) Discuss any noticeable effects of illumination in parts (a) and (b)., , 840, , Chapter 20, , Other Two-Terminal Devices
Page 867 :
32. Which colors is the CdS unit of Fig. 20.30 most sensitive to?, , §, , 20.8 IR Emitters, , 33. (a) Determine the radiant flux at a dc forward current of 70 mA for the device of Fig. 20.32., (b) Determine the radiant flux in lumens at a dc forward current of 45 mA., *34. (a) Through the use of Fig. 20.33, determine the relative radiant intensity at an angle of 25°, for a package with a flat glass window., (b) Plot a curve of relative radiant intensity versus degrees for the flat package., *35. If 60 mA of dc forward current is applied to an SG1010A IR emitter, what will be the incident, radiant flux in lumens 5° off the center if the package has an internal collimating system? Refer to Figs. 20.32 and 20.33., , §, , 20.9 Liquid-Crystal Displays, , 36. Referring to Fig. 20.37, which terminals must be energized to display number 7?, 37. In your own words, describe the basic operation of an LCD., 38. Discuss the relative differences in mode of operation between an LED and an LCD display., 39. What are the relative advantages and disadvantages of an LCD display as compared to an LED, display?, , §, , 20.10 Solar Cells, , 40. A 1-cm by 2-cm solar cell has a conversion efficiency of 9%. Determine the maximum power, rating of the device., *41. If the power rating of a solar cell is determined on a very rough scale by the product VOC ISC,, is the greatest rate of increase obtained at lower or higher levels of illumination? Explain your, reasoning., 42. (a) Referring to Fig. 20.48, what power density is required to establish a current of 24 mA at, an output voltage of 0.25 V?, (b) Why is 100 mW/cm2 the maximum power density in Fig. 20.48?, (c) Determine the output current if the power is 40 mW/cm2 and the output voltage is 0.3 V., *43. (a) Sketch a curve of output current versus power density at an output voltage of 0.15 V using, the characteristics of Fig. 20.48., (b) Sketch a curve of output voltage versus power density at a current of 19 mA., (c) Is either of the curves from parts (a) and (b) linear within the limits of the maximum power, limitation?, , §, , 20.11 Thermistors, , *44. For the thermistor of Fig. 20.49, determine the dynamic rate of change in specific resistance, with temperature at T 20°C. How does this compare to the value determined at T 300°C?, From the results, determine whether the greatest change in resistance per unit change in temperature occurs at lower or higher levels of temperature. Note the vertical log scale., 45. Using the information provided in Fig. 20.49, determine the total resistance of a 2-cm length, of the material having a perpendicular surface area of 1 cm2 at a temperature of 0°C. Note the, vertical log scale., 46. (a), , Referring to Fig. 20.50, determine the current at which a 25°C sample of the material, changes from a positive to negative temperature coefficient. (Figure 20.50 is a log scale.), (b) Determine the power and resistance levels of the device (Fig. 20.50) at the peak of the, 0°C curve., (c) At a temperature of 25°C, determine the power rating if the resistance level is 1 M., , 47. In Fig. 20.52, V 0.2 V and Rvariable 10 . If the current through the sensitive movement is, 2 mA and the voltage drop across the movement is 0 V, what is the resistance of the thermistor?, *Please Note: Asterisks indicate more difficult problems., , Problems, , 841
Page 868 :
CHAPTER, , 21, , pnpn, and Other Devices, 21.1 INTRODUCTION, In this chapter, a number of important devices not discussed in detail in earlier chapters are introduced. The two-layer semiconductor diode has led to three-, four-, and, even five-layer devices. A family of four-layer pnpn devices will first be considered:, SCR (silicon-controlled rectifier), SCS (silicon-controlled switch), GTO (gate turnoff switch), LASCR (light-activated SCR), followed by an increasingly important device—the UJT (unijunction transistor). Those four-layer devices with a control mechanism are commonly referred to as thyristors, although the term is most frequently, applied to the SCR (silicon-controlled rectifier). The chapter closes with an introduction to the phototransistor, opto-isolators, and the PUT (programmable unijunction transistor)., , pnpn DEVICES, 21.2 SILICON-CONTROLLED RECTIFIER, Within the family of pnpn devices, the silicon-controlled rectifier (SCR) is unquestionably of the greatest interest today. It was first introduced in 1956 by Bell Telephone Laboratories. A few of the more common areas of application for SCRs include relay controls, time-delay circuits, regulated power suppliers, static switches,, motor controls, choppers, inverters, cycloconverters, battery chargers, protective circuits, heater controls, and phase controls., In recent years, SCRs have been designed to control powers as high as 10 MW, with individual ratings as high as 2000 A at 1800 V. Its frequency range of application has also been extended to about 50 kHz, permitting some high-frequency applications such as induction heating and ultrasonic cleaning., , 21.3 BASIC SILICON-CONTROLLED, RECTIFIER OPERATION, As the terminology indicates, the SCR is a rectifier constructed of silicon material, with a third terminal for control purposes. Silicon was chosen because of its high temperature and power capabilities. The basic operation of the SCR is different from the, fundamental two-layer semiconductor diode in that a third terminal, called a gate, de842
Page 869 :
termines when the rectifier switches from the open-circuit to short-circuit state. It is, not enough to simply forward-bias the anode-to-cathode region of the device. In the, conduction region, the dynamic resistance of the SCR is typically 0.01 to 0.1 . The, reverse resistance is typically 100 k or more., The graphic symbol for the SCR is shown in Fig. 21.1 with the corresponding, connections to the four-layer semiconductor structure. As indicated in Fig. 21.1a, if, forward conduction is to be established, the anode must be positive with respect to, the cathode. This is not, however, a sufficient criterion for turning the device on. A, pulse of sufficient magnitude must also be applied to the gate to establish a turn-on, gate current, represented symbolically by IGT., , Figure 21.1, , (a) SCR symbol; (b) basic construction., , A more detailed examination of the basic operation of an SCR is best effected, by splitting the four-layer pnpn structure of Fig. 21.1b into two three-layer transistor structures as shown in Fig. 21.2a and then considering the resultant circuit of, Fig. 21.2b., , Figure 21.2 SCR two-transistor, equivalent circuit., , Note that one transistor for Fig. 21.2 is an npn device while the other is a pnp, transistor. For discussion purposes, the signal shown in Fig. 21.3a will be applied, to the gate of the circuit of Fig. 21.2b. During the interval 0 → t1,Vgate 0 V, the, circuit of Fig. 21.2b will appear as shown in Fig. 21.3b (Vgate 0 V is equivalent, to the gate terminal being grounded as shown in the figure). For VBE2 Vgate 0, V, the base current IB2 0 and IC2 will be approximately ICO. The base current of, Q1, IB1 IC2 ICO, is too small to turn Q1 on. Both transistors are therefore in the, “off ” state, resulting in a high impedance between the collector and emitter of each, transistor and the open-circuit representation for the controlled rectifier as shown, in Fig. 21.3c., 21.3 Basic Silicon-Controlled Rectifier Operation, , 843
Page 870 :
Vgate, , IA ≅ ICO, , VG, , E1, , E1, IB1, , Q1, t3, , –VG, , t1, , t4, , t2, , IC2 = ICO, , IB2, Vgate = 0 V, , Q2, , +, VBE2, , (a), , Figure 21.3, , High impedance, (open-circuit), approximation, , –, , E2, , (b), , E2, , (c), , “Off” state of the SCR., , At t t1, a pulse of VG volts will appear at the SCR gate. The circuit conditions, established with this input are shown in Fig. 21.4a. The potential VG was chosen sufficiently large to turn Q2 on (VBE2 VG). The collector current of Q2 will then rise, to a value sufficiently large to turn Q1 on (IB1 IC2). As Q1 turns on, IC1 will increase,, resulting in a corresponding increase in IB2. The increase in base current for Q2 will, result in a further increase in IC2. The net result is a regenerative increase in the collector current of each transistor. The resulting anode-to-cathode resistance (RSCR , V/IA) is then small because IA is large, resulting in the short-circuit representation for, the SCR as indicated in Fig. 21.4b. The regenerative action described above results, in SCRs having typical turn-on times of 0.1 to 1 s. However, high-power devices in, the range 100 to 400 A may have 10- to 25-s turn-on times., V, IA, E1, IA, , IB1, , V, E1, , Q1, IC1, , IC2, , IB2, , +, , Q2, , +, VBE2, , VG, , –, , –, , Low impedance, (short-circuit, approximation), , IK (cathode) ≅ IA, , E2, , (a), , E2, , (b), , Figure 21.4, the SCR., , “On” state of, , In addition to gate triggering, SCRs can also be turned on by significantly raising the temperature of the device or raising the anode-to-cathode voltage to the, breakover value shown on the characteristics of Fig. 21.7., The next question of concern is: How long is the turn-off time and how is turnoff accomplished? An SCR cannot be turned off by simply removing the gate signal,, and only a special few can be turned off by applying a negative pulse to the gate terminal as shown in Fig. 21.3a at t t3., , 844, , Chapter 21, , pnpn and Other Devices
Page 871 :
The two general methods for turning off an SCR are categorized as the anode, current interruption and the forced-commutation technique., The two possibilities for current interruption are shown in Fig. 21.5. In Fig. 21.5a, IA, is zero when the switch is opened (series interruption), while in Fig. 21.5b, the same, condition is established when the switch is closed (shunt interruption)., IA = 0, IA = 0, , (a), , (b), , Figure 21.5 Anode current, interruption., , Forced commutation is the “forcing” of current through the SCR in the direction, opposite to forward conduction. There are a wide variety of circuits for performing, this function, a number of which can be found in the manuals of major manufacturers in this area. One of the more basic types is shown in Fig. 21.6. As indicated in, the figure, the turn-off circuit consists of an npn transistor, a dc battery VB, and a, pulse generator. During SCR conduction, the transistor is in the “off” state, that is, IB, 0 and the collector-to-emitter impedance is very high (for all practical purposes an, open circuit). This high impedance will isolate the turn-off circuitry from affecting, the operation of the SCR. For turn-off conditions, a positive pulse is applied to the, base of the transistor, turning it heavily on, resulting in a very low impedance from, collector to emitter (short-circuit representation). The battery potential will then appear directly across the SCR as shown in Fig. 21.6b, forcing current through it in the, reverse direction for turn-off. Turn-off times of SCRs are typically 5 to 30 s., , Figure 21.6, , Forced-commutation technique., , 21.4 SCR CHARACTERISTICS, AND RATINGS, The characteristics of an SCR are provided in Fig. 21.7 for various values of gate current. The currents and voltages of usual interest are indicated on the characteristic. A, brief description of each follows., , 21.4 SCR Characteristics and Ratings, , 845
Page 872 :
IA, , A, , VF, , +, IA, , –, , K, Forward conduction, region, , IG, , IG 2, Reverse breakdown, voltage, , IG 1, , Holding, IH, current, VF3, , Reverse blocking, region, , Figure 21.7, , IG = 0, , VF2, , VF1, , Forward blocking, region, , V(BR)F*, Forward, breakover, voltage, , VF, , SCR characteristics., , 1. Forward breakover voltage V(BR)F* is that voltage above which the SCR enters the, conduction region. The asterisk (*) is a letter to be added that is dependent on the, condition of the gate terminal as follows:, O open circuit from G to K, S short circuit from G to K, R resistor from G to K, V fixed bias (voltage) from G to K, 2. Holding current (IH) is that value of current below which the SCR switches from, the conduction state to the forward blocking region under stated conditions., 3. Forward and reverse blocking regions are the regions corresponding to the opencircuit condition for the controlled rectifier which block the flow of charge (current) from anode to cathode., 4. Reverse breakdown voltage is equivalent to the Zener or avalanche region of the, fundamental two-layer semiconductor diode., It should be immediately obvious that the SCR characteristics of Fig. 21.7 are, very similar to those of the basic two-layer semiconductor diode except for the horizontal offshoot before entering the conduction region. It is this horizontal jutting region that gives the gate control over the response of the SCR. For the characteristic, having the solid blue line in Fig. 21.7 (IG 0), VF must reach the largest required, breakover voltage (V(BR)F*) before the “collapsing” effect will result and the SCR can, enter the conduction region corresponding to the on state. If the gate current is increased to IG1, as shown in the same figure by applying a bias voltage to the gate terminal, the value of VF required for the conduction (VF1) is considerably less. Note, also that IH drops with increase in IG. If increased to IG2, the SCR will fire at very, low values of voltage (VF3) and the characteristics begin to approach those of the basic p-n junction diode. Looking at the characteristics in a completely different sense,, for a particular VF voltage, say VF2 (Fig. 21.7), if the gate current is increased from, IG 0 to IG1 or more, the SCR will fire., 846, , Chapter 21, , pnpn and Other Devices
Page 873 :
The gate characteristics are provided in Fig. 21.8. The characteristics of Fig. 21.8b, are an expanded version of the shaded region of Fig. 21.8a. In Fig. 21.8a, the three, gate ratings of greatest interest, PGFM, IGFM, and VGFM are indicated. Each is included, on the characteristics in the same manner employed for the transistor. Except for portions of the shaded region, any combination of gate current and voltage that falls, within this region will fire any SCR in the series of components for which these characteristics are provided. Temperature will determine which sections of the shaded region must be avoided. At 65°C the minimum current that will trigger the series of, SCRs is 100 mA, while at 150°C only 20 mA are required. The effect of temperature on the minimum gate voltage is usually not indicated on curves of this type since, gate potentials of 3 V or more are usually obtained easily. As indicated on Fig. 21.8b,, a minimum of 3 V is indicated for all units for the temperature range of interest., Other parameters usually included on the specification sheet of an SCR are the, turn-on time (ton), turn-off time (toff), junction temperature (TJ), and case temperature, (TC), all of which should by now be, to some extent, self-explanatory., Min. gate current, required to trigger, all units at, +150°C +25°C, , −65°C, Min. gate, voltage, required to, trigger all units, , 3, , 10, Max. allowable, instantaneous gate, power − 12.0 W, Preferred, firing area, 6, , 4, Notes (1) Junction temperature −65°C to +150°C, (2) Shaded areas represent locus, of possible trigger points from, −65°C to +150°C, PGFM = 12 W, IGFM = 20 A, VGFM = 10 V, , 3, 2, 1, 0, , 0.1, , 0.4, , 0.8, , 1.2, , 1.6, , 2.0, , 2, , 1, Max. gate voltage, that will not trigger, any units at, 150°C = 0.15 V, 0, , IG (A), , 50, Instantaneous gate current, , 100 IG (mA), (0.1A), , (b), , (a), , Figure 21.8, , Instantaneous gate voltage (V), , Instantaneous gate voltage (V), , 8, , SCR gate characteristics (GE series C38)., , 21.5 SCR CONSTRUCTION AND, TERMINAL IDENTIFICATION, The basic construction of the four-layer pellet of an SCR is shown in Fig. 21.9a. The, complete construction of a thermal fatigue-free, high-current SCR is shown in Fig., 21.9b. Note the position of the gate, cathode, and anode terminals. The pedestal acts, as a heat sink by transferring the heat developed to the chassis on which the SCR is, mounted. The case construction and terminal identification of SCRs will vary with, the application. Other case-construction techniques and the terminal identification of, each are indicated in Fig. 21.10., 21.5 SCR Construction and Terminal Identification, , 847
Page 874 :
Figure 21.9 (a) Alloy-diffused SCR pellet; (b) thermal fatigue-free SCR construction. (Courtesy General Electric Company.), , Figure 21.10 SCR case construction and terminal identification. [(a) Courtesy, General Electric Company; (b) and (c) courtesy International Rectifier Corporation.], , 21.6 SCR APPLICATIONS, A few of the possible applications for the SCR are listed in the introduction to the, SCR (Section 21.2). In this section, we consider five: a static switch, phase-control, system, battery charger, temperature controller, and single-source emergency-lighting, system., A half-wave series static switch is shown in Fig. 21.11a. If the switch is closed, as shown in Fig. 21.11b, a gate current will flow during the positive portion of the, input signal, turning the SCR on. Resistor R1 limits the magnitude of the gate cur848, , Chapter 21, , pnpn and Other Devices
Page 875 :
IL, RL, , A, , + +, , R1, , RL, , D1, Mechanical, electrical, or electromechanical, switch, , K, , G, , –, , +, , A, , R1, D1, , VF, , –K, , –, , G, IG, , (b), , (a), , Figure 21.11, , Half-wave series static switch., , rent. When the SCR turns on, the anode-to cathode voltage (VF) will drop to the conduction value, resulting in a greatly reduced gate current and very little loss in the, gate circuitry. For the negative region of the input signal, the SCR will turn off since, the anode is negative with respect to the cathode. The diode D1 is included to prevent a reversal in gate current., The waveforms for the resulting load current and voltage are shown in Fig. 21.11b., The result is a half-wave-rectified signal through the load. If less than 180° conduction is desired, the switch can be closed at any phase displacement during the positive portion of the input signal. The switch can be electronic, electromagnetic, or mechanical, depending on the application., A circuit capable of establishing a conduction angle between 90° and 180° is, shown in Fig. 21.12a. The circuit is similar to that of Fig. 21.11a except for the addition of a variable resistor and the elimination of the switch. The combination of the, resistors R and R1 will limit the gate current during the positive portion of the input, signal. If R1 is set to its maximum value, the gate current may never reach turn-on, magnitude. As R1 is decreased from the maximum, the gate current will increase from, the same input voltage. In this way, the required turn-on gate current can be established in any point between 0° and 90° as shown in Fig. 21.12b. If R1 is low, the SCR, will fire almost immediately, resulting in the same action as that obtained from the, circuit of Fig. 21.11a (180° conduction). However, as indicated above, if R1 is increased, a larger input voltage (positive) will be required to fire the SCR. As shown, in Fig. 21.12b, the control cannot be extended past a 90° phase displacement since, the input is at its maximum at this point. If it fails to fire at this and lesser values of, input voltage on the positive slope of the input, the same response must be expected, from the negatively sloped portion of the signal waveform. The operation here is normally referred to in technical terms as half-wave variable-resistance phase control. It, is an effective method of controlling the rms current and therefore power to the load., RL, , R, , A, , R1, 0° 90°, 90° conduction, , K, , G, IG, (a), , Figure 21.12, , (b), , Half-wave variable-resistance phase control., , 21.6 SCR Applications, , 849
Page 876 :
A third popular application of the SCR is in a battery-charging regulator. The fundamental components of the circuit are shown in Fig. 21.13. You will note that the, control circuit has been blocked off for discussion purposes., As indicated in the figure, D1 and D2 establish a full-wave-rectified signal across, SCR1 and the 12-V battery to be charged. At low battery voltages, SCR2 is in the, “off ” state for reasons to be explained shortly. With SCR2 open, the SCR1 controlling circuit is exactly the same as the series static switch control discussed earlier in, this section. When the full-wave-rectified input is sufficiently large to produce the required turn-on gate current (controlled by R1), SCR1 will turn on and charging of the, battery will commence. At the start of charging, the low battery voltage will result in, a low voltage VR as determined by the simple voltage-divider circuit. Voltage VR is, in turn too small to cause 11.0-V Zener conduction. In the off state, the Zener is effectively an open circuit, maintaining SCR2 in the “off ” state since the gate current, is zero. The capacitor C1 is included to prevent any voltage transients in the circuit, from accidentally turning on SCR2. Recall from your fundamental study of circuit, analysis that the voltage cannot change instantaneously across a capacitor. In this way,, C1 prevents transient effects from affecting the SCR., , Control mechanism, 117 V, ac, , D1, SCR1, GE, C20F, , R1, , 47 Ω, (2 W), V2, , D2, 47 Ω (2 W), , R2, , 47 Ω, (2 W), , R4, , 12 -V, battery, , R5, 750 Ω, (1 W), , 11 V, , +, VR, , –, , Figure 21.13, , SCR2, GE, C5U, C1, , R3, , 50 µF, , 1 kΩ, , Battery-charging regulator., , As charging continues, the battery voltage rises to a point where VR is sufficiently, high to both turn on the 11.0-V Zener and fire SCR2. Once SCR2 has fired, the shortcircuit representation for SCR2 will result in a voltage-divider circuit determined by, R1 and R2 that will maintain V2 at a level too small to turn SCR1 on. When this occurs, the battery is fully charged and the open-circuit state of SCR1 will cut off the, charging current. Thus the regulator recharges the battery whenever the voltage drops, and prevents overcharging when fully charged., The schematic diagram of a 100-W heater control using an SCR appears in Fig., 21.14. It is designed such that the 100-W heater will turn on and off as determined, by thermostats. Mercury-in-glass thermostats are very sensitive to temperature change., In fact, they can sense changes as small as 0.1°C. It is limited in application, however, in that it can handle only very low levels of current—below 1 mA. In this application, the SCR serves as a current amplifier in a load-switching element. It is not, 850, , Chapter 21, , pnpn and Other Devices
Page 877 :
100-W heater load, CR1, CR2, , GE C58, or, C106B, , SCR1, 120 V ac, 60 Hz, CR3, , 0.1 µF, , CR4, , GE A14B, CR1−CR4, , R1, 510 kΩ, Twist leads to minimize, pickup, , Hg in glass thermostat, (such as vap. air div. 206-44, series; princo #T141, or, equivalent), , Figure 21.14 Temperature controller., (Courtesy General Electric, Semiconductor Products Division.), , an amplifier in the sense that it magnifies the current level of the thermostat. Rather, it is a device whose higher current level is controlled by the behavior of the thermostat., It should be clear that the bridge network is connected to the ac supply through, the 100-W heater. This will result in a full-wave-rectified voltage across the SCR., When the thermostat is open, the voltage across the capacitor will charge to a gatefiring potential through each pulse of the rectified signal. The charging time constant, is determined by the RC product. This will trigger the SCR during each half-cycle of, the input signal, permitting a flow of charge (current) to the heater. As the temperature rises, the conductive thermostat will short-circuit the capacitor, eliminating the, possibility of the capacitor charging to the firing potential and triggering the SCR., The 510-k resistor will then contribute to maintaining a very low current (less than, 250 A) through the thermostat., The last application for the SCR to be described is shown in Fig. 21.15. It is a, single-source emergency-lighting system that will maintain the charge on a 6-V battery to ensure its availability and also provide dc energy to a bulb if there is a power, shortage. A full-wave-rectified signal will appear across the 6-V lamp due to diodes, D2 and D1. The capacitor C1 will charge to a voltage slightly less than a difference, between the peak value of the full-wave-rectified signal and the dc voltage across R2, established by the 6-V battery. In any event, the cathode of SCR1 is higher than the, , Figure 21.15 Single-source emergency-lighting system. (Courtesy General Electric Semiconductor Products Division.), , 21.6 SCR Applications, , 851
Page 878 :
anode and the gate-to-cathode voltage is negative, ensuring that the SCR is nonconducting. The battery is being charged through R1 and D1 at a rate determined by R1., Charging will only take place when the anode of D1 is more positive than its cathode. The dc level of the full-wave-rectified signal will ensure that the bulb is lit when, the power is on. If the power should fail, the capacitor C1 will discharge through D1,, R1, and R3 until the cathode of SCR1 is less positive than the anode. At the same time,, the junction of R2 and R3 will become positive and establish sufficient gate-to-cathode voltage to trigger the SCR. Once fired, the 6-V battery would discharge through, the SCR1 and energize the lamp and maintain its illumination. Once power is restored,, the capacitor C1 will recharge and re-establish the nonconducting state of SCR1 as, described above., , 21.7 SILICON-CONTROLLED SWITCH, The silicon-controlled switch (SCS), like the silicon-controlled rectifier, is a four-layer, pnpn device. All four semiconductor layers of the SCS are available due to the addition of an anode gate, as shown in Fig. 21.16a. The graphic symbol and transistor, equivalent circuit are shown in the same figure. The characteristics of the device are, essentially the same as those for the SCR. The effect of an anode gate current is very, similar to that demonstrated by the gate current in Fig. 21.7. The higher the anode, gate current, the lower the required anode-to-cathode voltage to turn the device on., The anode gate connection can be used to turn the device either on or off. To turn, on the device, a negative pulse must be applied to the anode gate terminal, while a, positive pulse is required to turn off the device. The need for the type of pulse indicated above can be demonstrated using the circuit of Fig. 21.16c. A negative pulse at, the anode gate will forward-bias the base-to-emitter junction of Q1, turning it on. The, resulting heavy collector current IC1 will turn on Q2, resulting in a regenerative action and the on state for the SCS device. A positive pulse at the anode gate will, reverse-bias the base-to-emitter junction of Q1, turning it off, resulting in the opencircuit “off ” state of the device. In general, the triggering (turn-on) anode gate current is larger in magnitude than the required cathode gate current. For one representative SCS device, the triggering anode gate current is 1.5 mA while the required, cathode gate current is 1 A. The required turn-on gate current at either terminal is, affected by many factors. A few include the operating temperature, anode-to-cathode, voltage, load placement, and type of cathode, gate-to-cathode or anode gate-to-anode, connection (short-circuit, open-circuit, bias, load, etc.). Tables, graphs, and curves are, normally available for each device to provide the type of information indicated above., , Figure 21.16 Silicon-controlled switch (SCS): (a) basic construction; (b) graphic, symbol; (c) equivalent transistor circuit., , 852, , Chapter 21, , pnpn and Other Devices
Page 879 :
Three of the more fundamental types of turn-off circuits for the SCS are shown, in Fig. 21.17. When a pulse is applied to the circuit of Fig. 21.17a, the transistor conducts heavily, resulting in a low-impedance ( short-circuit) characteristic between, collector and emitter. This low-impedance branch diverts anode current away from, the SCS, dropping it below the holding value and consequently turning it off. Similarly, the positive pulse at the anode gate of Fig. 21.17b will turn the SCS off by the, mechanism described earlier in this section. The circuit of Fig. 21.17c can be turned, either off or on by a pulse of the proper magnitude at the cathode gate. The turn-off, characteristic is possible only if the correct value of RA is employed. It will control, the amount of regenerative feedback, the magnitude of which is critical for this type, of operation. Note the variety of positions in which the load resistor RL can be placed., There are a number of other possibilities that can be found in any comprehensive, semiconductor handbook or manual., , Figure 21.17, , SCS turn-off techniques., , An advantage of the SCS over a corresponding SCR is the reduced turn-off time,, typically within the range 1 to 10 s for the SCS and 5 to 30 s for the SCR. Some, of the remaining advantages of the SCS over an SCR include increased control and, triggering sensitivity and a more predictable firing situation. At present, however, the, SCS is limited to low power, current, and voltage ratings. Typical maximum anode, currents range from 100 to 300 mA with dissipation (power) ratings of 100 to 500 mW., A few of the more common areas of application include a wide variety of computer circuits (counters, registers, and timing circuits), pulse generators, voltage sensors, and oscillators. One simple application for an SCS as a voltage-sensing device, is shown in Fig. 21.18. It is an alarm system with n inputs from various stations. Any, single input will turn that particular SCS on, resulting in an energized alarm relay and, light in the anode gate circuit to indicate the location of the input (disturbance)., , Figure 21.18, , 21.7 Silicon-Controlled Switch, , SCS alarm circuit., , 853
Page 880 :
Figure 21.19 Alarm circuit., (Courtesy General Electric, Semiconductor Products, Division.), , One additional application of the SCS is in the alarm circuit of Fig. 21.19. RS represents a temperature-, light-, or radiation-sensitive resistor, that is, an element whose, resistance will decrease with the application of any of the three energy sources listed, above. The cathode gate potential is determined by the divider relationship established, by RS and the variable resistor. Note that the gate potential is at approximately 0 V if, RS equals the value set by the variable resistor since both resistors will have 12 V, across them. However, if RS decreases, the potential of the junction will increase until the SCS is forward-biased, causing the SCS to turn on and energize the alarm, relay., The 100-k resistor is included to reduce the possibility of accidental triggering, of the device through a phenomenon known as rate effect. It is caused by the stray, capacitance levels between gates. A high-frequency transient can establish sufficient, base current to turn the SCS on accidentally. The device is reset by pressing the reset button, which in turn opens the conduction path of the SCS and reduces the anode current to zero., Sensitivity to temperature-, light-, or radiation-sensitive resistors whose resistance, increases due to the application of any of the three energy sources described above can, be accommodated by simply interchanging the location of RS and the variable resistor. The terminal identification of an SCS is shown in Fig. 21.20 with a packaged SCS., , Figure 21.20 Silicon-controlled, switch (SCS): (a) device; (b) terminal, identification. (Courtesy General, Electric Company.), , 21.8 GATE TURN-OFF SWITCH, The gate turn-off switch (GTO) is the third pnpn device to be introduced in this chapter. Like the SCR, however, it has only three external terminals, as indicated in Fig., 21.21a. Its graphical symbol is also shown in Fig. 21.21b. Although the graphical, symbol is different from either the SCR or the SCS, the transistor equivalent is exactly the same and the characteristics are similar., The most obvious advantage of the GTO over the SCR or SCS is the fact that it, can be turned on or off by applying the proper pulse to the cathode gate (without the, , Figure 21.21 Gate turn-off, switch (GTO): (a) basic, construction; (b) symbol., , 854, , Chapter 21, , pnpn and Other Devices
Page 881 :
anode gate and associated circuitry required for the SCS). A consequence of this turnoff capability is an increase in the magnitude of the required gate current for triggering. For an SCR and GTO of similar maximum rms current ratings, the gate-triggering current of a particular SCR is 30 A while the triggering current of the GTO is, 20 mA. The turn-off current of a GTO is slightly larger than the required triggering, current. The maximum rms current and dissipation ratings of GTOs manufactured today are limited to about 3 A and 20 W, respectively., A second very important characteristic of the GTO is improved switching characteristics. The turn-on time is similar to the SCR (typically 1 s), but the turn-off, time of about the same duration (1 s) is much smaller than the typical turn-off time, of an SCR (5 to 30 s). The fact that the turn-off time is similar to the turn-on time, rather than considerably larger permits the use of this device in high-speed applications., A typical GTO and its terminal identification are shown in Fig. 21.22. The GTO, gate input characteristics and turn-off circuits can be found in a comprehensive manual or specification sheet. The majority of the SCR turn-off circuits can also be used, for GTOs., Some of the areas of application for the GTO include counters, pulse generators,, multivibrators, and voltage regulators. Figure 21.23 is an illustration of a simple sawtooth generator employing a GTO and a Zener diode., , Figure 21.23, , Figure 21.22 Typical GTO and, its terminal identification., (Courtesy General Electric, Company.), , GTO sawtooth generator., , When the supply is energized, the GTO will turn on, resulting in the short-circuit, equivalent from anode to cathode. The capacitor C1 will then begin to charge toward, the supply voltage as shown in Fig. 21.23. As the voltage across the capacitor C1, charges above the Zener potential, a reversal in gate-to-cathode voltage will result,, establishing a reversal in gate current. Eventually, the negative gate current will be, large enough to turn the GTO off. Once the GTO turns off, resulting in the opencircuit representation, the capacitor C1 will discharge through the resistor R3. The, discharge time will be determined by the circuit time constant R3C1. The proper, choice of R3 and C1 will result in the sawtooth waveform of Fig. 21.23. Once the output potential Vo drops below VZ, the GTO will turn on and the process will repeat., , 21.9 LIGHT-ACTIVATED SCR, The next in the series of pnpn devices is the light-activated SCR (LASCR). As indicated by the terminology, it is an SCR whose state is controlled by the light falling, upon a silicon semiconductor layer of the device. The basic construction of an LASCR, is shown in Fig. 21.24a. As indicated in Fig. 21.24a, a gate lead is also provided to, permit triggering the device using typical SCR methods. Note also in the figure that, 21.9 Light-Activated SCR, , 855
Page 882 :
Figure 21.24, , Light-activated SCR (LASCR): (a) basic construction; (b) symbols., , the mounting surface for the silicon pellet is the anode connection for the device. The, graphical symbols most commonly employed for the LASCR are provided in Fig., 21.24b. The terminal identification and a typical LASCR appear in Fig. 21.25a., Some of the areas of application for the LASCR include optical light controls,, relays, phase control, motor control, and a variety of computer applications. The, , Figure 21.25 LASCR: (a) appearance and terminal identification; (b) lighttriggering characteristics. (Courtesy General Electric Company.), , 856, , Chapter 21, , pnpn and Other Devices
Page 883 :
maximum current (rms) and power (gate) ratings for LASCRs commercially available today are about 3 A and 0.1 W. The characteristics (light triggering) of a representative LASCR are provided in Fig. 21.25b. Note in this figure that an increase, in junction temperature results in a reduction in light energy required to activate, the device., One interesting application of an LASCR is in the AND and OR circuits of Fig., 21.26. Only when light falls on LASCR1 and LASCR2 will the short-circuit representation for each be applicable and the supply voltage appear across the load. For, the OR circuit, light energy applied to LASCR1 or LASCR2 will result in the supply, voltage appearing across the load., , Load, , Load, , LASCR1, , LASCR1, , LASCR2, , Supply, , Supply, , LASCR2, , (a), , (b), , Figure 21.26 LASCR optoelectronic logic circuitry: (a) AND gate: input to, LASCR1 and LASCR2 required for energization of the load; (b) OR gate: input to, either LASCR1 or LASCR2 will energize the load., , The LASCR is most sensitive to light when the gate terminal is open. Its sensitivity can be reduced and controlled somewhat by the insertion of a gate resistor, as, shown in Fig. 21.26., A second application of the LASCR appears in Fig. 21.27. It is the semiconductor analog of an electromechanical relay. Note that it offers complete isolation between the input and switching element. The energizing current can be passed through, a light-emitting diode or a lamp, as shown in the figure. The incident light will cause, the LASCR to turn on and permit a flow of charge (current) through the load as established by the dc supply. The LASCR can be turned off using the reset switch S1., This system offers the additional advantages over an electromechanical switch of long, life, microsecond response, small size, and the elimination of contact bounce., , S1, Load, dc input, , ac or dc, input, , +, dc, , –, , Figure 21.27 Latching relay., (Courtesy Powerex, Inc.), , 21.9 Light-Activated SCR, , 857
Page 884 :
21.10 SHOCKLEY DIODE, The Shockley diode is a four-layer pnpn diode with only two external terminals, as, shown in Fig. 21.28a with its graphical symbol. The characteristics (Fig. 21.28b) of, the device are exactly the same as those encountered for the SCR with IG 0. As indicated by the characteristics, the device is in the off state (open-circuit representation) until the breakover voltage is reached, at which time avalanche conditions develop and the device turns on (short-circuit representation)., IA, Anode, , IA, , +, , Anode, , p, n, , VF, , p, , IBR, , n, , VBR, , –, , Cathode, , (b), , (a), , Figure 21.28, , Figure 21.29 Shockley diode, application—trigger switch for an, SCR., , VF, , Cathode, , Shockley diode: (a) basic construction and symbol; (b) characteristics., , One common application of the Shockley diode is shown in Fig. 21.29, where it, is employed as a trigger switch for an SCR. When the circuit is energized, the voltage across the capacitor will begin to change toward the supply voltage. Eventually,, the voltage across the capacitor will be sufficiently high to first turn on the Shockley, diode and then the SCR., , 21.11 DIAC, The diac is basically a two-terminal parallel-inverse combination of semiconductor, layers that permits triggering in either direction. The characteristics of the device, presented in Fig. 21.30a, clearly demonstrate that there is a breakover voltage in either, Anode 1, , Anode 1, I, , Anode 2, , VBR, , IBR, , Anode 2, , Anode 1, IBR, , VBR V, , n1, , p1, n2, , p2, , Figure 21.30 Diac:, (a) characteristics; (b) symbols, and basic construction. (Courtesy, General Electric Company.), , 858, , n3, Anode 2, , (a), , Chapter 21, , pnpn and Other Devices, , (b)
Page 885 :
direction. This possibility of an on condition in either direction can be used to its, fullest advantage in ac applications., The basic arrangement of the semiconductor layers of the diac is shown in Fig., 21.30b, along with its graphical symbol. Note that neither terminal is referred to as, the cathode. Instead, there is an anode 1 (or electrode 1) and an anode 2 (or electrode, 2). When anode 1 is positive with respect to anode 2, the semiconductor layers of, particular interest are p1n2p2 and n3. For anode 2 positive with respect to anode 1, the, applicable layers are p2n2p1 and n1., For the unit appearing in Fig. 21.30, the breakdown voltages are very close in, magnitude but may vary from a minimum of 28 V to a maximum of 42 V. They are, related by the following equation provided in the specification sheet:, VBR1 VBR2 0.1VBR2, , (21.1), , The current levels (IBR1 and IBR2) are also very close in magnitude for each device. For the unit of Fig. 21.30, both current levels are about 200 A 0.2 mA., The use of the diac in a proximity detector appears in Fig. 21.31. Note the use of, an SCR in series with the load and the programmable unijunction transistor (to be, described in Section 21.13) connected directly to the sensing electrode., , Figure 21.31 Proximity detector, or touch switch. (Courtesy, Powerex, Inc.), , As the human body approaches the sensing electrode, the capacitance between the, electrode and ground will increase. The programmable UJT (PUT) is a device that, will fire (enter the short-circuit state) when the anode voltage (VA) is at least 0.7 V, (for silicon) greater than the gate voltage (VG). Before the programmable device turns, on, the system is essentially as shown in Fig. 21.32. As the input voltage rises, the, , Figure 21.32 Effect of capacitive, element on the behavior of the, network of Fig. 21.31., , 21.11 Diac, , 859
Page 886 :
diac voltage VG will follow as shown in the figure until the firing potential is reached., It will then turn on and the diac voltage will drop substantially, as shown. Note that, the diac is in essentially an open-circuit state until it fires. Before the capacitive element is introduced, the voltage VG will be the same as the input. As indicated in the, figure, since both VA and VG follow the input, VA can never be greater than VG by 0.7, V and turn on the device. However, as the capacitive element is introduced, the voltage VG will begin to lag the input voltage by an increasing angle, as indicated in the, figure. There is therefore a point established where VA can exceed VG by 0.7 V and, cause the programmable device to fire. A heavy current is established through the, PUT at this point, raising the voltage VK and turning on the SCR. A heavy SCR current will then exist through the load, reacting to the presence of the approaching, person., A second application of the diac appears in the next section (Fig. 21.34) as we, consider an important power-control device: the triac., , 21.12 TRIAC, The triac is fundamentally a diac with a gate terminal for controlling the turn-on conditions of the bilateral device in either direction. In other words, for either direction, the gate current can control the action of the device in a manner very similar to that, demonstrated for an SCR. The characteristics, however, of the triac in the first and, third quadrants are somewhat different from those of the diac, as shown in Fig. 21.33c., Note the holding current in each direction not present in the characteristics of the, diac., The graphical symbol for the device and the distribution of the semiconductor layers are provided in Fig. 21.33 with photographs of the device. For each possible direction of conduction, there is a combination of semiconductor layers whose state will, be controlled by the signal applied to the gate terminal., One fundamental application of the triac is presented in Fig. 21.34. In this capacity, it is controlling the ac power to the load by switching on and off during the, positive and negative regions of input sinusoidal signal. The action of this circuit during the positive portion of the input signal is very similar to that encountered for the, Shockley diode in Fig. 21.29. The advantage of this configuration is that during the, negative portion of the input signal, the same type of response will result since both, the diac and triac can fire in the reverse direction. The resulting waveform for the current through the load is provided in Fig. 21.34. By varying the resistor R, the conduction angle can be controlled. There are units available today that can handle in excess of 10-kW loads., , Figure 21.33 Triac: (a) symbol;, (b) basic construction;, (c) characteristics; (d) photographs., , 860, , Chapter 21, , pnpn and Other Devices
Page 887 :
Figure 21.33, , Figure 21.34, , Continued, , Triac application: phase (power) control., , OTHER DEVICES, 21.13 UNIJUNCTION TRANSISTOR, Recent interest in the unijunction transistor (UJT) has, like that for the SCR, been increasing at an exponential rate. Although first introduced in 1948, the device did not, become commercially available until 1952. The low cost per unit combined with the, excellent characteristics of the device have warranted its use in a wide variety of applications. A few include oscillators, trigger circuits, sawtooth generators, phase control, timing circuits, bistable networks, and voltage- or current-regulated supplies. The, fact that this device is, in general, a low-power-absorbing device under normal operating conditions is a tremendous aid in the continual effort to design relatively efficient systems., 21.13 Unijunction Transistor, , 861
Page 888 :
The UJT is a three-terminal device having the basic construction of Fig. 21.35. A, slab of lightly doped (increased resistance characteristic) n-type silicon material has, two base contacts attached to both ends of one surface and an aluminum rod alloyed, to the opposite surface. The p-n junction of the device is formed at the boundary of, the aluminum rod and the n-type silicon slab. The single p-n junction accounts for, the terminology unijunction. It was originally called a duo (double) base diode due, to the presence of two base contacts. Note in Fig. 21.35 that the aluminum rod is alloyed to the silicon slab at a point closer to the base 2 contact than the base 1 contact and that the base 2 terminal is made positive with respect to the base 1 terminal, by VBB volts. The effect of each will become evident in the paragraphs to follow., B2, , p-n junction, E, , Ohmic base, contact, , VBB, , Aluminum rod, , n-type high resistivity, silicon slad, , Figure 21.36 Symbol and basic, biasing arrangement for the, unijunction transistor., , Figure 21.35 Unijunction transistor, (UJT): basic construction., , B1, , The symbol for the unijunction transistor is provided in Fig. 21.36. Note that the, emitter leg is drawn at an angle to the vertical line representing the slab of n-type material. The arrowhead is pointing in the direction of conventional current (hole) flow, when the device is in the forward-biased, active, or conducting state., The circuit equivalent of the UJT is shown in Fig. 21.37. Note the relative simplicity of this equivalent circuit: two resistors (one fixed, one variable) and a single, diode. The resistance RB1 is shown as a variable resistor since its magnitude will vary, with the current IE. In fact, for a representative unijunction transistor, RB1 may vary, from 5 k down to 50 for a corresponding change of IE from 0 to 50 A. The interbase resistance RBB is the resistance of the device between terminals B1 and B2, when IE 0. In equation form,, RBB (RB1 RB2)IE 0, , (21.2), , (RBB is typically within the range of 4 to 10 k.) The position of the aluminum rod, of Fig. 21.35 will determine the relative values of RB1 and RB2 with IE 0. The magnitude of VRB (with IE 0) is determined by the voltage-divider rule in the following manner:, 1, , B2, , +, , RB2, E, , IE, , –, , RBB = RB1 + RB2, , +, , +, VE, , VBB, , VD, , RB1, , ηVBB, , IE = 0, , –, 862, , Chapter 21, , pnpn and Other Devices, , –, B1, , IE = 0, , Figure 21.37 UJT, equivalent circuit.
Page 889 :
VRB , 1, , The Greek letter, fined by, , , , RB1 VBB, VBB, RB1 RB2, , IE0, , (21.3), , (eta) is called the intrinsic stand-off ratio of the device and is de-, , , , R B1, RB1 RB2, , , , IE0, , , , R B1, RBB, , (21.4), , For applied emitter potentials (VE) greater than VRB ( VBB) by the forward voltage drop of the diode VD (0.35 → 0.70 V), the diode will fire. Assume the short-circuit representation (on an ideal basis), and IE will begin to flow through RB1. In equation form, the emitter firing potential is given by, 1, , VP VBB VD, , (21.5), , The characteristics of a representative unijunction transistor are shown for VBB , 10 V in Fig. 21.38. Note that for emitter potentials to the left of the peak point, the, magnitude of IE is never greater than IEO (measured in microamperes). The current, IEO corresponds very closely with the reverse leakage current ICO of the conventional, bipolar transistor. This region, as indicated in the figure, is called the cutoff region., Once conduction is established at VE VP, the emitter potential VE will drop with, increase in IE. This corresponds exactly with the decreasing resistance RB1 for increasing current IE, as discussed earlier. This device, therefore, has a negative resistance region that is stable enough to be used with a great deal of reliability in the, areas of application listed earlier. Eventually, the valley point will be reached, and, any further increase in IE will place the device in the saturation region. In this region,, the characteristics approach that of the semiconductor diode in the equivalent circuit, of Fig. 21.37., The decrease in resistance in the active region is due to the holes injected into the, n-type slab from the aluminum p-type rod when conduction is established. The increased hole content in the n-type material will result in an increase in the number of, free electrons in the slab, producing an increase in conductivity (G) and a corresponding, , Figure 21.38, , UJT static emitter-characteristic curve., , 21.13 Unijunction Transistor, , 863
Page 890 :
drop in resistance (R ↓ 1/G ↑). Three other important parameters for the unijunction transistor are IP, VV, and IV. Each is indicated on Fig. 21.38. They are all selfexplanatory., The emitter characteristics as they normally appear are provided in Fig. 21.39., Note that IEO (A) is not in evidence since the horizontal scale is in milliamperes., The intersection of each curve with the vertical axis is the corresponding value of VP., For fixed values of and VD, the magnitude of VP will vary as VBB, that is,, VP ↑ VBB↑ VD, ↑_____|____↑, fixed, , Figure 21.39, , Typical static emitter-characteristic curves for a UJT., , A typical set of specifications for the UJT is provided in Fig. 21.40b. The discussion of the last few paragraphs should make each quantity readily recognizable., The terminal identification is provided in the same figure with a photograph of a representative UJT. Note that the base terminals are opposite each other while the emitter terminal is between the two. In addition, the base terminal to be tied to the higher, potential is closer to the extension on the lip of the casing., One rather common application of the UJT is in the triggering of other devices, such as the SCR. The basic elements of such a triggering circuit are shown in Fig., 21.41. The resistor R1 must be chosen to ensure that the load line determined by R1, passes through the device characteristics in the negative resistance region, that is, to, the right of the peak point but to the left of the valley point as shown in Fig. 21.42., If the load line fails to pass to the right of the peak point, the device cannot turn on., An equation for R1 that will ensure a turn-on condition can be established if we consider the peak point at which IR1 IP and VE VP. (The equality IR1 IP is valid, since the charging current of the capacitor, at this instant, is zero. That is, the capacitor is at this particular instant changing from a charging to a discharging state.) Then, 864, , Chapter 21, , pnpn and Other Devices
Page 892 :
or to ensure turning off,, R1, , V VV, IV, , (21.7), , The range of R1 is therefore limited by, V VV, IV, , R1, , V VP, IP, , (21.8), , The resistance R2 must be chosen small enough to ensure that the SCR is not, turned on by the voltage VR2 of Fig. 21.43 when IE 0 A. The voltage VR2 is then, given by:, Figure 21.43 Triggering, network when IE 0 A., , VR2 , , R2V, R2 RBB, , , , (21.9), , IE0 A, , The capacitor C will determine, as we shall see, the time interval between triggering, pulses and the time span of each pulse., At the instant the dc supply voltage V is applied, the voltage vE vC will charge, toward V volts from VV as shown in Fig. 21.44 with a time constant R1C., , Figure 21.44 (a) Charging and discharging phases for trigger network of Fig., 21.41; (b) equivalent network when UJT turns on., , The general equation for the charging period is, vC VV (V VV)(1 et/R1C), , (21.10), , As noted in Fig. 21.44, the voltage across R2 is determined by Eq. (21.9) during this, charging period. When vC vE VP, the UJT will enter the conduction state and the, capacitor will discharge through RB1 and R2 at a rate determined by the time constant, (RB1 R2)C., 866, , Chapter 21, , pnpn and Other Devices
Page 893 :
The discharge equation for the voltage vC vE is the following:, vC VPet/(RB, , R2)C, , 1, , (21.11), , Equation (21.11) is complicated somewhat by the fact that RB1 will decrease with, increasing emitter current and the other elements of the network, such as R1 and V,, will affect the discharge rate and final level. However, the equivalent network appears, as shown in Fig. 21.44 and the magnitudes of R1 and RB2 are typically such that a, Thévenin network for the network surrounding the capacitor C will be only slightly, affected by these two resistors. Even though V is a reasonably high voltage, the voltage-divider contribution to the Thévenin voltage can be ignored on an approximate, basis., Using the reduced equivalent of Fig. 21.45 for the discharge phase will result in, the following approximation for the peak value of VR2:, R2(VP 0.7), R2 RB1, , VR2 , , (21.12), , The period t1 of Fig. 21.44 can be determined in the following manner:, vC (charging) VV (V VV)(1 et/R1C), VV V VV (V VV)et/R1C, V (V VV)et/R1C, t1/R1C, , when vC VP, t t1, and VP V (V VV)e, , Figure 21.45 Reduced equivalent network when UJT turns on., , , or, , VP V, et1/R1C, V VV, and, , e t1/R1C , , V VP, V VV, , Using logs, we have, V VP, V VV, , loge et1/R1C loge, and, , with, , V VP, t1, loge, V VV, R1C, t1 R1C loge, , V VV, V VP, , (21.13), , For the discharge period the time between t1 and t2 can be determined from Eq., (21.11) as follows:, vC (discharging) VP et/(RB R2)C, 1, , Establishing t1 as t 0 gives us, vC VV at t t2, and, or, , VV VPet 2/(RB, , 1, , et2/(RB, , 1, , R2)C, , R2)C, , , , VV, VP, 21.13 Unijunction Transistor, , 867
Page 894 :
Using logs yields, t2, V, loge V, (RB1 R2)C, VP, t2 (RB1 R2)C loge, , and, , VP, VV, , (21.14), , The period of time to complete one cycle is defined by T in Fig. 21.44. That is,, T t1 t 2, , (21.15), , If the SCR were dropped from the configuration, the network would behave as a, relaxation oscillator, generating the waveform of Fig. 21.44. The frequency of oscillation is determined by, fosc , In many systems, t1, , 1, T, , (21.16), , t2 and, T t1 R1C loge, , Since V, , VV in many instances,, T t1 R1C loge, R1C loge, , but, , or, , 868, , V, V VP, 1, 1 VP/V, , VP/V if we ignore the effects of VD in Eq. (21.5) and, T R1C loge, , EXAMPLE 21.2, , V VV, V VP, , f, , 1, 1, , 1, R1C loge [1/(1 )], , (21.17), , Given the relaxation oscillator of Fig. 21.46:, (a) Determine RB1 and RB2 at IE 0 A., (b) Calculate VP, the voltage necessary to turn on the UJT., (c) Determine whether R1 is within the permissible range of values as determined by, Eq. (21.8) to ensure firing of the UJT., (d) Determine the frequency of oscillation if RB1 100 during the discharge, phase., (e) Sketch the waveform of vC for a full cycle., (f) Sketch the waveform of vR2 for a full cycle., Chapter 21, , pnpn and Other Devices
Page 896 :
VP, VV, 8, (0.1 k 0.1 k)(0.1 pF) loge, 1, 6, (0.02 10 )(2.08), 41.6 s, and, T t1 t2 5.05 ms 0.0416 ms, t2 (RB1 R2)C loge, , 5.092 ms, fosc , , with, , 1, 1, , 196 Hz, T, 5.092 ms, , Using Eq. (21.17) gives us, 1, R1C loge [1/(1 )], 1, , 5 103 loge 2.5, , f, , 218 Hz, (e) See Fig. 21.48., , υC, 5τ = 5R1C, V = 12 V, τ = R1C, VP = 8 V, , VV = 1 V, 0, , 5.05 ms, , t, Interval = 41.6 µs, , Figure 21.48 The voltage vC for, the relaxation oscillator of Fig., 21.46., , 5.05 ms 5.0916 ms, , (f) During the charging phase, (Eq. 21.9), VR2 , , R2V, 0.1 k(12 V), , 0.235 V, R2 RBB, 0.1 k 5 k, , When vC VP (Eq. 21.12), VR2 , , 0.1 k(8 V 0.7 V), R2(VP 0.7 V), , 0.1 k 0.1 k, R2 RB1, , 3.65 V, The plot of vR2 appears in Fig. 21.49., 870, , Chapter 21, , pnpn and Other Devices
Page 897 :
υR 2 (V), , 3.65 V, , τ = (RB1 + R2) C, , 2V, 0, , t, , 5.0916 ms, , 5.05 ms, 41.6 µs, , Figure 21.49, , The voltage vR2 for the relaxation oscillator of Fig. 21.46., , 21.14 PHOTOTRANSISTORS, The fundamental behavior of photoelectric devices was introduced earlier with the, description of the photodiode. This discussion will now be extended to include the, phototransistor, which has a photosensitive collector–base p-n junction. The current, induced by photoelectric effects is the base current of the transistor. If we assign the, notation I for the photoinduced base current, the resulting collector current, on an, approximate basis, is, IC hfe I, , (21.18), , A representative set of characteristics for a phototransistor is provided in Fig., 21.50 with the symbolic representation of the device. Note the similarities between, these curves and those of a typical bipolar transistor. As expected, an increase in light, intensity corresponds with an increase in collector current. To develop a greater degree of familiarity with the light-intensity unit of measurement, milliwatts per square, centimeter, a curve of base current versus flux density appears in Fig. 21.51a. Note, the exponential increase in base current with increasing flux density. In the same figure, a sketch of the phototransistor is provided with the terminal identification and, the angular alignment., , Figure 21.50 Phototransistor:, (a) collector characteristics, (MRD300); (b) symbol. (Courtesy, Motorola, Inc.), , 21.14 Phototransistors, , 871
Page 898 :
Figure 21.51 Phototransistor: (a) base current versus flux density; (b) device;, (c) terminal identification; (d) angular alignment. (Courtesy Motorola, Inc.), , Some of the areas of application for the phototransistor include punch-card readers, computer logic circuitry, lighting control (highways, etc.), level indication, relays,, and counting systems., A high-isolation AND gate is shown in Fig. 21.52 using three phototransistors and, three LEDs (light-emitting diodes). The LEDs are semiconductor devices that emit, light at an intensity determined by the forward current through the device. With the, aid of discussions in Chapter 1, the circuit behavior should be relatively easy to understand. The terminology high isolation simply refers to the lack of an electrical connection between the input and output circuits., , Figure 21.52 High-isolation, AND gate employing phototransistors and light-emitting diodes, (LEDs)., , 872, , Chapter 21, , pnpn and Other Devices
Page 899 :
21.15 OPTO-ISOLATORS, The opto-isolator is a device that incorporates many of the characteristics described, in the preceding section. It is simply a package that contains both an infrared LED, and a photodetector such as a silicon diode, transistor Darlington pair, or SCR. The, wavelength response of each device is tailored to be as identical as possible to permit the highest measure of coupling possible. In Fig. 21.53, two possible chip configurations are provided, with a photograph of each. There is a transparent insulating, cap between each set of elements embedded in the structure (not visible) to permit, the passage of light. They are designed with response times so small that they can be, used to transmit data in the megahertz range., , Figure 21.53, , Two Litronix opto-isolators. (Courtesy Siemens Components, Inc.), , The maximum ratings and electrical characteristics for the IL-1 model are provided in Fig. 21.54. Note that ICEO is measured in nanoamperes and that the power, dissipation of the LED and transistor are about the same., The typical optoelectronic characteristic curves for each channel are provided in, Figs. 21.55 through 21.59. Note the very pronounced effect of temperature on the output current at low temperatures but the fairly level response at or above room temperature (25°C). As mentioned earlier, the level of ICEO is improving steadily with, improved design and construction techniques (the lower the better). In Fig. 21.55, we, do not reach 1 A until the temperature rises above 75°C. The transfer characteristics of Fig. 21.56 compare the input LED current (which establishes the luminous, 21.15 Opto-Isolators, , 873
Page 900 :
(a) Maximum Ratings, Gallium arsenide LED (each channel) IL-1, Power dissipation @ 25°C, Derate linearly from 25°C, Continuous forward current, Detector silicon phototransistor (each channel) IL-1, Power dissipation @ 25°C, Derate linearly from 25°C, Collector-emitter breakdown voltage, Emitter-collector breakdown voltage, Collector-base breakdown voltage, Package IL-1, Total package dissipation at 25°C ambient (LED plus detector), Derate linearly from 25°C, Storage temperature, Operating temperature, , 200 mW, 2.6 mW/°C, 150 mA, 200 mW, 2.6 mW/°C, 30 V, 7V, 70 V, 250 mW, 3.3 mW/°C, −55°C to +150°C, −55°C to +100°C, , (b) Electrical Characteristics per Channel (at 25°C Ambient), Parameter, Gallium arsenide LED, Forward voltage, Reverse current, Capacitance, Phototransistor detector, BVCEO, ICEO, Collector-emitter capacitance, BVECO, Coupled characteristics, dc current transfer ratio, Capacitance, input to output, Breakdown voltage, Resistance, input to output, Vsat, Propagation delay, tD on, tD off, , Figure 21.54, , Figure 21.55 Dark current, (ICEO) versus temperature., , 874, , Min., , Max., , Unit, , 1.3, 0.1, 100, , 1.5, 10, , V, µA, pF, , IF = 60 mA, VR = 3.0 V, VR = 0 V, , 5.0, 2.0, , 50, , V, nA, pF, V, , IC = 1 mA, VCE = 10 V, IF = 0 A, VCE = 0 V, IE = 100 µA, , 30, , 7, 0.2, , 100, 0.5, 6.0, 25, , Test Conditions, , IF = 10 mA, VCE = 10 V, , 0.35, 0.5, , 2500, , pF, V, GΩ, V, µs, µs, , DC, IC = 1.6 mA, IF = 16 mA, RL = 2.4 kΩ, VCE = 5 V, IF = 16 mA, , Litronix IL-1 opto-isolator., , Figure 21.56 Transfer, characteristics., , Chapter 21, , Typ., , pnpn and Other Devices, , Figure 21.57 Detector output, characteristics.
Page 901 :
Relative output current, , 1.2, 1.0, 0.8, 0.6, 0.4, 0, −50 −25, , Figure 21.58 Switching time, versus collector current., , 0 25 50 75 100, Case temperature (°C), , Figure 21.59 Relative output, versus temperature., , flux) to the resulting collector current of the output transistor (whose base current is, determined by the incident flux). In fact, Fig. 21.57 demonstrates that the VCE voltage affects the resulting collector current only very slightly. It is interesting to note, in Fig. 21.58 that the switching time of an opto-isolator decreases with increased current, while for many devices it is exactly the reverse. Consider that it is only 2 s for, a collector current of 6 mA and a load RL of 100 . The relative output versus temperature appears in Fig. 21.59., The schematic representation for a transistor coupler appears in Fig. 21.53. The, schematic representations for a photodiode, photo-Darlington, and photo-SCR optoisolator appear in Fig. 21.60., , Figure 21.60, , Opto-isolators: (a) photodiode; (b) photo-Darlington; (c) photo-SCR., , 21.16 PROGRAMMABLE UNIJUNCTION, TRANSISTOR, Although there is a similarity in name, the actual construction and mode of operation, of the programmable unijunction transistor (PUT) is quite different from the unijunction transistor. The fact that the I—V characteristics and applications of each are, similar prompted the choice of labels., As indicated in Fig. 21.61, the PUT is a four-layer pnpn device with a gate connected directly to the sandwiched n-type layer. The symbol for the device and the basic biasing arrangement appears in Fig. 21.62. As the symbol suggests, it is essentially an SCR with a control mechanism that permits a duplication of the characteristics, of the typical SCR. The term programmable is applied because RBB, , and VP as defined for the UJT can be controlled through the resistors RB1, RB2, and the supply voltage VBB. Note in Fig. 21.62 that through an application of the voltage-divider rule,, when IG 0:, 21.16 Programmable Unijunction Transistor, , Figure 21.61, UJT (PUT)., , Programmable, , 875
Page 902 :
Figure 21.62 Basic biasing, arrangement for the PUT., , VG , , RB1, VBB VBB, RB1 RB2, , , , where, , (21.19), , RB1, RB1 RB2, , as defined for the UJT., The characteristics of the device appear in Fig. 21.63. As noted on the diagram,, the “off” state (I low, V between 0 and VP) and the“on” state (I IV, V VV), are separated by the unstable region as occurred for the UJT. That is, the device, cannot stay in the unstable state—it will simply shift to either the “off” or “on” stable, states., VAK, VP, , Unstable, region (−R), Off state, , VF, VV, On state, IP, , IV, , IA, , IF, , Figure 21.63 PUT, characteristics., , The firing potential (VP) or voltage necessary to “fire” the device is given by, VP VBB VD, , (21.20), , as defined for the UJT. However, VP represents the voltage drop VAK in Fig. 21.61, (the forward voltage drop across the conducting diode). For silicon, VD is typically, 0.7 V. Therefore,, VAK VAG VGK, VP VD VG, , and, 876, , Chapter 21, , VP VBB 0.7 V, pnpn and Other Devices, , silicon, , (21.21)
Page 903 :
We noted above, however, that VG VBB with the result that, VP VG 0.7, , (21.22), , silicon, , Recall that for the UJT both RB1 and RB2 represent the bulk resistance and ohmic, base contacts of the device—both inaccessible. In the development above, we note, that RB1 and RB2 are external to the device, permitting an adjustment of and hence, VG above. In other words, the PUT provides a measure of control on the level of VP, required to turn on the device., Although the characteristics of the PUT and UJT are similar, the peak and valley, currents of the PUT are typically lower than those of a similarly rated UJT. In addition, the minimum operating voltage is also less for a PUT., If we take a Thévenin equivalent of the network to the right of the gate terminal, in Fig. 21.62, the network of Fig. 21.64 will result. The resulting resistance RS is important because it is often included in specification sheets since it affects the level, of IV., G, IG, , RS =, , RB1 RB2, RB1+ RB2, , VS = ηVBB, , Figure 21.64 Thévenin, equivalent for the network to the, right of the gate terminal in, Fig. 21.62., , Thevenin, ´, equivalent, , The basic operation of the device can be reviewed through reference to Fig. 21.63., A device in the “off” state will not change state until the voltage VP as defined by VG, and VD is reached. The level of current until IP is reached is very low, resulting in an, open-circuit equivalent since R V (high)/I (low) will result in a high resistance level., When VP is reached, the device will switch through the unstable region to the “on”, state, where the voltage is lower but the current higher, resulting in a terminal resistance R V (low)/I(high), which is quite small, representing short-circuit equivalent, on an approximate basis. The device has therefore switched from essentially an opencircuit to a short-circuit state at a point determined by the choice of RB1, RB2, and VBB., Once the device is in the “on” state, the removal of VG will not turn the device off., The level of voltage VAK must be dropped sufficiently to reduce the current below a, holding level., Determine RB1 and VBB for a silicon PUT if it is determined that, V, and RB2 5 k., , 0.8, VP 10.3, , EXAMPLE 21.2, , Solution, Eq. (21.4):, , , , RB1, 0.8, RB1 RB2, , RB1 0.8(RB1 RB2), 0.2RB1 0.8RB2, RB1 4RB2, RB1 4(5 k) 20 k, 21.16 Programmable Unijunction Transistor, , 877
Page 904 :
Eq. (21.20): VP VBB VD, 10.3 V (0.8)(VBB) 0.7 V, 9.6 V 0.8VBB, VBB 12 V, One popular application of the PUT is in the relaxation oscillator of Fig. 21.65., The instant the supply is connected, the capacitor will begin to charge toward VBB, volts since there is no anode current at this point. The charging curve appears in Fig., 21.66. The period T required to reach the firing potential VP is given approximately by, T RCloge, , VBB, VBB VP, , (21.23), , or when VP VBB, , , , T RC loge 1 , , Figure 21.65, oscillator., , RB1, RB2, , , , (21.24), , Figure 21.66 Charging wave, for the capacitor C of Fig. 21.65., , PUT relaxation, , The instant the voltage across the capacitor equals VP, the device will fire and a, current IA IP will be established through the PUT. If R is too large, the current IP, cannot be established and the device will not fire. At the point of transition,, IPR VBB VP, and, , Rmax , , VBB VP, IP, , (21.25), , The subscript is included to indicate that any R greater than Rmax will result in a current less than IP. The level of R must also be such to ensure it is less than IV if oscillations are to occur. In other words, we want the device to enter the unstable region and then return to the “off ” state. From reasoning similar to that above:, Rmin , , VBB VV, IV, , (21.26), , The discussion above requires that R be limited to the following for an oscillatory system:, Rmin, 878, , Chapter 21, , pnpn and Other Devices, , R, , Rmax
Page 905 :
The waveforms of vA, vG, and vK appear in Fig. 21.67. Note that T determines the, maximum voltage vA can charge to. Once the device fires, the capacitor will rapidly, discharge through the PUT and RK, producing the drop shown. Of course, vK will, peak at the same time due to the brief but heavy current. The voltage vG will rapidly, drop down from VG to a level just greater than 0 V. When the capacitor voltage drops, to a low level, the PUT will once again turn off and the charging cycle will be repeated. The effect on VG and VK is shown in Fig. 21.67., , υA, VP, , 0, , t, , T, υK, , VK = VA − VV, , 0, υG, , t, , VG = ηVBB, , 0, , t, , Figure 21.67 Waveforms, for PUT oscillator of Fig. 21.65., , If VBB 12 V, R 20 k, C 1 F, RK 100 , RB1 10 k, RB2 5 k, IP , 100 A, VV 1 V, and IV 5.5 mA, determine:, (a) VP., (b) Rmax and Rmin., (c) T and frequency of oscillation., (d) The waveforms of vA, vG, and vK., , EXAMPLE 21.3, , Solution, (a) Eq. 21.20: VP VBB VD, RB1, , VBB 0.7 V, RB1 RB2, 10 k, (12 V) 0.7 V, , 10 k 5 k, (0.67)(12 V) 0.7 V 8.7 V, (b) From Eq. (21.25): Rmax , , , VBB VP, IP, 12 V 8.7 V, 33 k, 100 A, 21.16 Programmable Unijunction Transistor, , 879
Page 906 :
VBB VV, IV, 12 V 1 V, , 2 k, 5 . 5 mA, R: 2 k 20 k 33 k, , From Eq. (21.26): Rmin , , (c) Eq. (21.23): T RCloge, , VBB, VBB VP, , 12 V, 12 V 8.7 V, 20 103 loge (3.64), 20 103(1.29), 25.8 ms, 1, 1, f , 38.8 Hz, T, 25.8 ms, (20 k)(1 F) loge, , (d) As indicated in Fig. 21.68., υA, 8.7 V, , 0, , υK, , 25.8 ms, VK = VA − VV = 8.7 V − 1 V = 7.7 V, , 0, υG, , t, , VG = η VBB = 8 V, , 0, , PROBLEMS, , t, , t, , Figure 21.68 Waveforms for, the oscillator of Example 21.3., , § 21.3 Basic Silicon-Controlled Rectifier Operation, 1. Describe in your own words the basic behavior of the SCR using the two-transistor equivalent, circuit., 2. Describe two techniques for turning an SCR off., 3. Consult a manufacturer’s manual or specification sheet and obtain a turn-off network. If possible, describe the turn-off action of the design., , § 21.4 SCR Characteristics and Ratings, *, , 880, , 4. (a) At high levels of gate current, the characteristics of an SCR approach those of what twoterminal device?, , Chapter 21, , pnpn and Other Devices
Page 907 :
(b) At a fixed anode-to-cathode voltage less than V(BR)F*, what is the effect on the firing of the, SCR as the gate current is reduced from its maximum value to the zero level?, (c) At a fixed gate current greater than IG 0, what is the effect on the firing of the SCR as, the gate voltage is reduced from V(BR)F*?, (d) For increasing levels of IG, what is the effect on the holding current?, 5. (a), (b), (c), (d), , Using Fig. 21.8, will a gate current of 50 mA fire the device at room temperature (25°C)?, Repeat part (a) for a gate current of 10 mA., Will a gate voltage of 2.6 V trigger the device at room temperature?, Is VG 6 V, IG 800 mA a good choice for firing conditions? Would VG 4 V, IG , 1.6 A be preferred? Explain., , § 21.6 SCR Applications, 6. In Fig. 21.11b, why is there very little loss in potential across the SCR during conduction?, 7. Fully explain why reduced values of R1 in Fig. 21.12 will result in an increased angle of conduction., *, , 8. Refer to the charging network of Fig. 21.13., (a) Determine the dc level of the full-wave rectified signal if a 11 transformer were employed., (b) If the battery in its uncharged state is sitting at 11 V, what is the anode-to-cathode voltage, drop across SCR1?, (c) What is the maximum possible value of VR (VGK 0.7 V)?, (d) At the maximum value of part (c), what is the gate potential of SCR2?, (e) Once SCR2 has entered the short-circuit state, what is the level of V2?, , § 21.7 Silicon-Controlled Switch, 9. Fully describe in your own words the behavior of the networks of Fig. 21.17., , § 21.8 Gate Turn-Off Switch, 10. (a) In Fig. 21.23, if VZ 50 V, determine the maximum possible value the capacitor C1 can, charge to (VGK 0.7 V)., (b) Determine the approximate discharge time (5) for R3 20 k., (c) Determine the internal resistance of the GTO if the rise time is one-half the decay period, determined in part (b)., , § 21.9 Light-Activated SCR, 11. (a) Using Fig. 21.25b, determine the minimum irradiance required to fire the device at room, temperature (25°C)., (b) What percent reduction in irradiance is allowable if the junction temperature is increased, from 0°C (32°F) to 100°C (212°F)?, , § 21.10 Shockley Diode, 12. For the network of Fig. 21.29, if VBR 6 V, V 40 V, R 10 k, C 0.2 F, and VGK (firing potential) 3 V, determine the time period between energizing the network and the turning on of the SCR., , § 21.11 Diac, 13. Using whatever reference you require, find an application of a diac and explain the network behavior., 14. If VBR2 is 6.4 V, determine the range for VBR1 using Eq. (21.1)., , § 21.12 Triac, 15. Repeat Problem 13 for the triac., Problems, , 881
Page 908 :
§ 21.13 Unijunction Transistor, 16. For the network of Fig. 21.41, in which V 40 V, 0.6, VV 1 V, IV 8 mA, and, IP 10 A, determine the range of R1 for the triggering network., 17. For a unijunction transistor with VBB 20 V,, determine:, (a) RB2., (b) RBB., (c) VRB ., (d) VP., , 0.65, RB1 2 k (IE 0), and VD 0.7 V,, , 1, , *, , 18. Given the relaxation oscillator of Fig. 21.69:, (a) Find RB1 and RB2 at IE 0 A., (b) Determine VP, the voltage necessary to turn on the UJT., (c) Determine whether R1 is within the permissible range of values defined by Eq. (21.8)., (d) Determine the frequency of oscillation if RB1 200 during the discharge phase., (e) Sketch the waveform of vC for two full cycles., (f) Sketch the waveform of vR2 for two full cycles., (g) Determine the frequency using Eq. (21.17) and compare to the value determined in part (d)., Account for any major differences., , Figure 21.69, , Problem 18, , § 21.14 Phototransistors, 19. For a phototransistor having the characteristics of Fig. 21.51, determine the photoinduced base, current for a radiant flux density of 5 mW/cm2. If hfe 40, find IC., *, , 20. Design a high-isolation OR-gate employing phototransistors and LEDs., , § 21.15 Opto-Isolators, 21. (a) Determine an average derating factor from the curve of Fig. 21.59 for the region defined, by temperatures between 25°C and 50°C., (b) Is it fair to say that for temperatures greater than room temperature (up to 100°C), the output current is somewhat unaffected by temperature?, 22. (a) Determine from Fig. 21.55 the average change in ICEO per degree change in temperature, for the range 25 to 50°C., (b) Can the results of part (a) be used to determine the level of ICEO at 35°C? Test your, theory., 23. Determine from Fig. 21.56 the ratio of LED output current to detector input current for an, output current of 20 mA. Would you consider the device to be relatively efficient in its purpose?, *, , 882, , 24. (a) Sketch the maximum-power curve of PD 200 mW on the graph of Fig. 21.57. List any, noteworthy conclusions., (b) Determine dc (defined by IC /IF) for the system at VCE 15 V, IF 10 mA., (c) Compare the results of part (b) with those obtained from Fig. 21.56 at IF 10 mA. Do, they compare? Should they? Why?, Chapter 21, , pnpn and Other Devices
Page 909 :
*, , 25. (a) Referring to Fig. 21.58, determine the collector current above which the switching time, does not change appreciably for RL 1 k and RL 100 ., (b) At IC 6 mA, how does the ratio of switching times for RL 1 k and RL 100 compare to the ratio of resistance levels?, , § 21.16 Programmable Unijunction Transistor, 26. Determine, , and VG for a PUT with VBB 20 V and RB1 3RB2., , 27. Using the data provided in Example 21.3, determine the impedance of the PUT at the firing, and valley points. Are the approximate open- and short-circuit states verified?, 28. Can Eq. (21.24) be derived exactly as shown from Eq. (21.23)? If not, what element is missing in Eq. (21.24)?, *, , 29. (a) Will the network of Example 21.3 oscillate if VBB is changed to 10 V? What minimum value, of VBB is required (VV a constant)?, (b) Referring to the same example, what value of R would place the network in the stable “on”, state and remove the oscillatory response of the system?, (c) What value of R would make the network a 2-ms time-delay network? That is, provide a, pulse vK 2 ms after the supply is turned on and then stay in the “on” state., *Please Note: Asterisks indicate more difficult problems., , Problems, , 883
Page 910 :
CHAPTER, , 22, , Oscilloscope and, Other Measuring, Instruments, 22.1 INTRODUCTION, One of the basic functions of electronic circuits is the generation and manipulation, of electronic waveshapes. These electronic signals may represent audio information,, computer data, television signals, timing signals (as used in radar), and so on. The, common meters used in electronic measurement are the multimeter—analog or digital, to enable measuring dc or ac voltages, currents, or impedances. Most meters provide ac measurements that are correct for nondistorted sinusoidal signals only. The, oscilloscope, on the other hand, displays the exact waveform, and the viewer can decide what to make of the various readings observed., The cathode ray oscilloscope (CRO) provides a visual presentation of any waveform applied to the input terminals. A cathode ray tube (CRT), much like a television, tube, provides the visual display showing the form of the signal applied as a waveform on the front screen. An electron beam is deflected as it sweeps across the tube, face, leaving a display of the signal applied to input terminals., While multimeters provide numeric information about an applied signal, the oscilloscope allows the actual form of the waveform to be displayed. A wide range of, oscilloscopes is available, some suited to measure signals below a specified frequency,, others to provide measuring signals of the shortest time span. A CRO may be built, to operate from a few hertz up to hundreds of megahertz; CROs may also be used to, measure time spans from fractions of a nanosecond (109) to many seconds., , 22.2 CATHODE RAY TUBE — THEORY, AND CONSTRUCTION, The CRT is the “heart” of the CRO, providing visual display of an input signal’s waveform. A CRT contains four basic parts:, 1., 2., 3., 4., , An electron gun to produce a stream of electrons., Focusing and accelerating elements to produce a well-defined beam of electrons., Horizontal and vertical deflecting plates to control the path of the electron beam., An evacuated glass envelope with a phosphorescent screen, which glows visibly, when struck by the electron beam., , Figure 22.1 shows the basic construction of a CRT. We will first consider the device’s basic operation. A cathode (K) containing an oxide coating is heated indirectly, 884
Page 911 :
Figure 22.1 Cathode ray tube: basic construction., , by a filament, resulting in the release of electrons from the cathode surface. A control grid (G) provides for control of the number of electrons passing farther into the, tube. A voltage on the control grid determines how many of the electrons freed by, heating are allowed to continue moving toward the face of the tube. After the electrons pass the control grid, they are focused into a tight beam and accelerated to a, higher velocity by the focusing and accelerating anodes. The parts discussed so far, comprise the electron gun of the CRT., The high-velocity, well-defined electron beam then passes through two sets of deflection plates. The first set of plates is oriented to deflect the electron beam vertically, up or down. The direction of the vertical deflection is determined by the voltage polarity applied to the deflecting plates. The amount of deflection is set by the, magnitude of the applied voltage. The beam is also deflected horizontally (left or, right) by a voltage applied to the horizontal deflecting plates. The deflected beam is, then further accelerated by very high voltages applied to the tube, with the beam finally striking a phosphorescent material on the inside face of the tube. This phosphor, glows when struck by the energetic electrons—the visible glow seen at the front of, the tube by the person using the scope., The CRT is a self-contained unit with leads brought out through a base to pins., Various types of CRTs are manufactured in a variety of sizes, with different phosphor, materials and deflection electrode placement. We can now consider how the CRT is, used in an oscilloscope., , 22.3 CATHODE RAY OSCILLOSCOPE, OPERATION, For operation as an oscilloscope, the electron beam is deflected horizontally by a, sweep voltage and vertically by the voltage to be measured. While the electron beam, is moved across the face of the CRT by the horizontal sweep signal, the input signal, deflects the beam vertically, resulting in a display of the input signal waveform. One, sweep of the beam across the face of the tube, followed by a “blank” period during, which the beam is turned off while being returned to the starting point across the tube, face, constitutes one sweep of the beam., A steady display is obtained when the beam repeatedly sweeps across the tube, with exactly the same image each sweep. This requires a synchronization, starting the, sweep at the same point in a repetitive waveform cycle. If the signal is properly synchronized, the display will be stationary. In the absence of sync, the picture will appear to drift or move horizontally across the screen., 22.3 Cathode Ray Oscilloscope Operation, , 885
Page 912 :
Basic Parts of a CRO, The basic parts of a CRO are shown in Fig. 22.2. We will first consider the CRO’s, operation for this simplified block diagram. To obtain a noticeable beam deflection, from a centimeter to a few centimeters, the usual voltage applied to the deflection, plates must be on the order of tens to hundreds of volts. Since the signals measured, using a CRO are typically only a few volts, or even a few millivolts, amplifier circuits are needed to increase the input signal to the voltage levels required to operate, the tube. There are amplifier sections for both the vertical and the horizontal deflection of the beam. To adjust the level of a signal, each input goes through an attenuator circuit, which can adjust the amplitude of the display., , Figure 22.2 Cathode ray oscilloscope: general block diagram., , 22.4 VOLTAGE SWEEP OPERATION, When the vertical input is 0 V, the electron beam may be positioned at the vertical, center of the screen. If 0 V is also applied to the horizontal input, the beam is then, at the center of the CRT face and remains a stationary dot. The vertical and horizontal positioning controls allow moving the dot anywhere on the tube face. Any dc voltage applied to an input will result in shifting the dot. Figure 22.3 shows a CRT face, with a centered dot and with a dot moved by a positive horizontal voltage (to the, right) and a negative vertical input voltage (down from center)., , Figure 22.3 Dot on CRT screen, due to stationary electron beam:, (a) centered dot due to stationary, electron beam; (b) off-center, stationary dot., , 886, , Chapter 22, , Oscilloscope and Other Measuring Instruments
Page 913 :
Horizontal Sweep Signal, To view a signal on the CRT face, it is necessary to deflect the beam across the CRT, with a horizontal sweep signal so that any variation of the vertical signal can be observed. Figure 22.4 shows the resulting straight-line display for a positive voltage applied to the vertical input using a linear (sawtooth) sweep signal applied to the horizontal channel. With the electron beam held at a constant vertical distance, the, horizontal voltage, going from negative to zero to positive voltage, causes the beam, to move from the left side of the tube, to the center, to the right side. The resulting, display is a straight line above the vertical center with the dc voltage properly displayed as a straight line., , Figure 22.4 Scope display, for dc vertical signal and linear, horizontal sweep signal., , The sweep voltage is shown to be a continuous waveform, not just a single sweep., This is necessary if a long-term display is to be seen. A single sweep across the tube, face would quickly fade out. By repeating the sweep, the display is generated over, and over, and if enough sweeps are generated per second, the display appears present, continuously. If the sweep rate is slowed down (as set by the time-scale controls of, the scope), the actual travel of the beam across the tube face can be observed., Applying only a sinusoidal signal to the vertical inputs (no horizontal sweep) results in a vertical straight line as shown in Fig. 22.5. If the sweep speed (frequency, , Figure 22.5 Resulting scope, display for sinusoidal vertical, input and no horizontal input., , 22.4 Voltage Sweep Operation, , 887
Page 914 :
of the sinusoidal signal) is reduced, it is possible to see the electron beam moving up, and down along a straight-line path., , Use of Linear Sawtooth Sweep to Display Vertical, Input, To view a sinusoidal signal, it is necessary to use a sweep signal on the horizontal, channel so that the signal applied to the vertical channel can be seen on the tube face., Figure 22.6 shows the resulting CRO display from a horizontal linear sweep and a sinusoidal input to the vertical channel. For one cycle of the input signal to appear as, shown in Fig. 22.6a, it is necessary that the signal and linear sweep frequencies be, synchronized. If there is any difference, the display will appear to move (not be synchronized) unless the sweep frequency is some multiple of the sinusoidal frequency., Lowering the sweep frequency allows more cycles of the sinusoidal signal to be displayed, whereas increasing the sweep frequency results in less of the sinusoidal vertical input to be displayed, thereby appearing as a magnification of a part of the input signal., , Figure 22.6 Display of, sinusoidal vertical input and, horizontal sweep input: (a) display, of vertical input signal using linear, sweep signal for horizontal, deflection; (b) scope display for a, sinusoidal vertical input and a, horizontal sweep speed equal to, one-half that of the vertical signal., , 888, , Chapter 22, , Oscilloscope and Other Measuring Instruments
Page 915 :
Determine how many cycles of a 2-kHz sinusoidal signal are viewed if the sweep frequency is:, (a) 2 kHz., (b) 4 kHz., (c) 1 kHz., , EXAMPLE 22.1, , Solution, (a) When the two signals have the same frequency, a full cycle will be seen., (b) When the sweep frequency is increased to 4 kHz, a half-cycle will be seen., (c) When the sweep frequency is reduced to 1 kHz, two cycles will be seen., , Figure 22.7 shows a pulse-type waveform applied as vertical input with a horizontal sweep, resulting in a scope display of the pulse signal. The numbering at each, waveform permits following the display for variation of input and sweep voltage during one cycle., , Figure 22.7 Use of the linear, sweep for a pulse-type waveform., , 22.5 SYNCHRONIZATION AND, TRIGGERING, A CRO display can be adjusted by setting the sweep speed (frequency) to display, either one cycle, a number of cycles, or part of a cycle. This is a very valuable feature of the CRO. Figure 22.8 shows the display resulting for a few cycles of the, sweep signal. Each time the horizontal sawtooth sweep voltage goes through a linear sweep cycle (from maximum negative to zero to maximum positive), the electron beam is caused to move horizontally across the tube face, from left to center to, right. The sawtooth voltage then drops quickly back to the negative starting voltage,, with the beam back to the left side. During the time the sweep voltage goes quickly, 22.5 Synchronization and Triggering, , 889
Page 916 :
Figure 22.8 Steady scope, display—input and sweep, signals synchronized., , negative (retrace), the beam is blanked (the grid voltage prevents the electrons from, hitting the tube face)., To see a steady display each time the beam is swept across the face of the tube,, it is necessary to start the sweep at the same point in the input signal cycle. In Fig., 22.9, the sweep frequency is too low and the CRO display will have an apparent “drift”, to the left. Figure 22.10 shows the result of setting the sweep frequency too high, with, an apparent drift to the right., It should be obvious that adjusting the sweep frequency to exactly the same as, the signal frequency to obtain a steady sweep is impractical. A more practical proce-, , Figure 22.9 Sweep frequency, too low—apparent drift to left., , 890, , Chapter 22, , Oscilloscope and Other Measuring Instruments
Page 917 :
Vertical input signal, , t, , Horizontal sweep signal, , t, , Each waveform is 3/4, of a sine wave (0 2π)., Each waveform is, determined by that, section of vertical, input between dashed, lines determined by, sweep signal., ←, , Figure 22.10 Sweep frequency too high—apparent drift to right., , dure is to wait until the signal reaches the same point in a cycle to start the trace. This, triggering has a number of features, as described next., , Triggering, The usual method of synchronizing uses a portion of the input signal to trigger a, sweep generator so that the sweep signal is locked or synchronized to the input signal. Using a portion of the same signal to be viewed to provide the synchronizing signal assures synchronization. Figure 22.11 shows a block diagram of how a trigger signal is derived in a single-channel display. The trigger signal source is obtained from, the line frequency (60 Hz) for viewing signals related to the line voltage, from an external signal (one other than that to be viewed), or more likely, from a signal derived, , Figure 22.11 Block diagram showing trigger operation of scope., , 22.5 Synchronization and Triggering, , 891
Page 918 :
from that applied as vertical input. The selector switch on the scope being set to INTERNAL will provide a part of the input signal to the trigger generator circuit. The, output of the trigger generator is a trigger signal that is used to start the main sweep, of the scope, which lasts a time set by the time/cm adjustment. Figure 22.12 shows, triggering being started at various points in a signal cycle., , Figure 22.12 Triggering at various points of signal level (Note:, sine starts at same point in cycle, each sweep and is therefore synchronized): (a) positive-going, zero level; (b) negative-going zero, level; (c) positive-voltage trigger, level; (d) negative-voltage trigger, level., , The trigger sweep operation can also be seen by looking at some of the resulting, waveforms. From a given input signal, a trigger waveform is obtained to provide for, a sweep signal. As seen in Fig. 22.13, the sweep is started at a time in the input signal cycle and lasts a period set by the sweep length controls. Then the scope waits, until the input reaches an identical point in its cycle before starting another sweep operation. The length of the sweep determines how many cycles will be viewed, while, the triggering assures that synchronization takes place., , Figure 22.13 Triggered sweep., , 892, , Chapter 22, , Oscilloscope and Other Measuring Instruments
Page 919 :
22.6 MULTITRACE OPERATION, Most modern oscilloscopes provide for viewing two or more traces on the scope face, at the same time. This allows comparing amplitude, special waveform features, and, other important waveform characteristics. A multiple trace can be obtained using more, than one electron gun, with the separate beams creating separate displays. More often, however, a single electron beam is used to create the multiple images., Two methods of developing two traces are CHOPPED and ALTERNATE. With, two input signals applied, an electronic switch first connects one input, then the other,, to the deflection circuitry. In the ALTERNATE mode of operation, the beam is swept, across the tube face displaying however many cycles of one input signal are to be displayed. Then the input switches (alternates) to the second input and displays the same, number of cycles of the second signal. Figure 22.14a shows the operation with alternate display. In the CHOPPED mode of operation (Fig. 22.14b), the beam repeatedly, switches between the two input signals during one sweep of the beam. As long as the, signal is of relatively low frequency, the action of switching is not visible and two, separate displays are seen., , Figure 22.14 Alternate and chopped mode displays for dual-trace operation: (a), alternate mode for dual-trace using single electron beam; (b) chopped mode for, dual-trace using single electron beam., , 22.7 MEASUREMENT USING CALIBRATED, CRO SCALES, The oscilloscope tube face has a calibrated scale to use in making amplitude or time, measurements. Figure 22.15 shows a typical calibrated scale. The boxes are divided, into centimeters (cm), 4 cm on each side of center. Each centimeter (box) is further, divided into 0.2-cm intervals., 22.7 Measurement Using Calibrated CRO Scales, , 893
Page 920 :
Figure 22.15 Calibrated, scope face., , Amplitude Measurements, The vertical scale is calibrated in either volts per centimeter (V/cm) or millivolts per, centimeter (mV/cm). Using the scale setting of the scope and the signal measured off, the face of the scope, one typically can measure peak-to-peak or peak voltages for an, ac signal., , EXAMPLE 22.2, , Calculate the peak-to-peak amplitude of the sinusoidal signal in Fig. 22.16 if the scope, scale is set to 5 mV/cm., , Figure 22.16 Waveform for, Example 22.2., , Solution, The peak-to-peak amplitude is, 2 2.6 cm 5 mV/cm 26 mV, , Note that a scope provides easy measurement of peak-to-peak values, whereas, a multimeter typically provides measurement of rms (for a sinusoidal waveform)., 894, , Chapter 22, , Oscilloscope and Other Measuring Instruments
Page 921 :
Calculate the amplitude of the pulse signal in Fig. 22.17 (scope setting 100 mV/cm)., , EXAMPLE 22.3, , Figure 22.17 Waveform for, Example 22.3., , Solution, The peak-to-peak amplitude is, (2.8 cm 2.4 cm) 100 mV/cm 520 mV 0.52 V, , Time Measurements, PERIOD, The horizontal scale of the scope can be used to measure time, in seconds (s),, milliseconds (ms), microseconds (s), or nanoseconds (ns). The interval of a pulse, from start to end is the period of the pulse. When the signal is repetitive, the period, is one cycle of the waveform., Calculate the period of the waveform shown in Fig. 22.18 (scope setting at 20 s/cm)., , EXAMPLE 22.4, , Figure 22.18 Waveform for, Example 22.4., , 22.7 Measurement Using Calibrated CRO Scales, , 895
Page 922 :
Solution, For the waveform of Fig. 22.18,, period T 3.2 cm 20 s/cm 64 s, , FREQUENCY, The measurement of a repetitive waveform’s period can be used to calculate the, signal’s frequency. Since frequency is the reciprocal of the period,, 1, f , T, , EXAMPLE 22.5, , (22.1), , Determine the frequency of the waveform shown in Fig. 22.18 (scope setting at, 5 s/cm)., , Solution, From the waveform, period T 3.2 cm 5 s/cm 16 s, 1, 1, f , T, 16 s, 62.5 kHz, , PULSE WIDTH, The time interval that a waveform is high (or low) is the pulse width of the signal. When the waveform edges go up and down instantly, the width is measured from, start (leading edge) to end (trailing edge) (see Fig. 22.19a). For a waveform with edges, that rise or fall over some time, the pulse width is measured between the 50% points, as shown in Fig. 22.19b., , Figure 22.19 Pulse-width, measurement., , 896, , Chapter 22, , Oscilloscope and Other Measuring Instruments
Page 923 :
Determine the pulse width of the waveform in Fig. 22.20., , Scope setting:, 2 µs/cm, , EXAMPLE 22.6, , Figure 22.20 Waveform for, Example 22.6., , Solution, For a reading of 4.6 cm at the midpoint of the waveform, the pulse width is, TPW 4.6 cm 2 s/cm 9.2 s, PULSE DELAY, The time interval between pulses is called the pulse delay. For waveforms, as, shown in Fig. 22.21, the pulse delay is measured between the midpoint (50% point), at the start of each pulse., , Figure 22.21 Waveform for, Example 22.7., , Determine the pulse delay for the waveforms of Fig. 22.21., , EXAMPLE 22.7, , Solution, From the waveforms in Fig. 22.21,, pulse delay TPD 2 cm 50 s/cm 100 s, , 22.7 Measurement Using Calibrated CRO Scales, , 897
Page 924 :
22.8 SPECIAL CRO FEATURES, The CRO has become more sophisticated and specialized in use. The range of amplitude measurements, the scales of time measurements, the number of traces displayed, the methods of providing sweep triggering, and the types of measurements, are different depending on the area of specialized scope usage., , Delayed Sweep, A useful CRO feature uses two time bases to provide selection of a small part of the, signal for viewing. One time base selects the overall signal viewed on the scope, while, a second permits selecting a small part of the viewed signal to be displayed in an expanded mode. The main time base is referred to as the A time base, while the second, time base, referred to as B, displays the signal after a selected delay time., Figure 22.22 provides a block diagram showing the operation of the two time, bases. With front-panel controls set to operate from the A sweep, a main sweep signal is set to view a number of cycles of the input signal. The controls then allow setting the B sweep using a variable setting dial, with the B sweep usually an intensified interval that can be moved over the face of the displayed sweep. When the desired, portion of the displayed sweep is set, the controls are moved to display the delayed, part of the signal, which is seen at the second time base setting as a magnified display. Figure 22.23 shows a pulse-type signal first viewed using the A sweep and then, the selected portion on a magnified sweep setting., Figure 22.22 Operation of delayed sweep—block diagram., , Figure 22.23 Main and, delayed sweeps., , 898
Page 925 :
22.9 SIGNAL GENERATORS, A signal generator provides an ac signal of adjustable amplitude and varying frequency, to use when operating an amplifier or other linear circuit. The frequency can typically, be adjusted from a few hertz to a few megahertz. The signal amplitude can be adjusted, from millivolts to a few volts of amplitude. While the signal is typically a sinusoidal, waveform, pulse waveforms or even triangular waveforms are often available., , Waveform Generator IC(8038), A precision waveform generator is provided by the 8038 IC unit shown in Fig. 22.24., The single 14-pin IC is capable of producing highly accurate sinusoidal, square, or, triangular waveforms to use in operating or testing other equipment. Consideration of, the IC’s operation will help understand how any commercially available signal generator operates. This particular IC can provide output frequency that may be adjusted, from less than 1 Hz up to about 300 kHz. The range of commercial units can be considerably higher. As indicated in Fig. 22.24, the IC provides three types of output, waveform, and all at the same frequency, the frequency being selected by the user., V_, Sine, adjust (gnd), NC, , NC, , 14, , 13, , 12, , 11, , C, , FM sweep, input, , 10, , 9, , 8, , 5, , 6, , 7, , 8038, , 1, , 2, , 3, , 4, , Freq., adjust, , Sine, adjust, , +, , V, , FM, bias, , Figure 22.24 8038 waveform, generator IC., , Figure 22.25 shows the connection of the IC when used to provide an adjustable, frequency output. The frequency of the unit would then be, 0.15, f , RC, , (22.2), , V + (+9 V), R, 10 kΩ, 4, , RL, 1 kΩ, 5, , 6, 9, , 7, 8, , 8038, 10, , C, 0.5 µF, , 11, , 3, 12, , 2, , 82 kΩ, , Figure 22.25 Connection of, 8038 as variable frequency, generator., , 22.9 Signal Generators, , 899
Page 926 :
EXAMPLE 22.8, , Referring to Fig. 22.25, determine the lowest and highest frequencies obtained when, varying the 10-k potentiometer from its minimum to its maximum setting., , Solution, Using Eq. (22.2), for a potentiometer set at 0, R 10 :, 0.15, f 30 kHz, (10 )(0.5 F), For a potentiometer set to its maximum,, 0.15, f 30 Hz, (10 k)(0.5 F), , ADJUSTABLE OUTPUT AMPLITUDE, The connection of Fig. 22.26 shows how to provide adjustment of the sinusoidal, waveform amplitude with the sinusoidal output provided through a buffered driver., The 310 op-amp is a unity-gain buffer providing the sinusoidal output from a lowimpedance output. [The 310 has a voltage gain near unity (1), with an output impedance of about 1 .] The output frequency is adjustable over a range from about, 30 Hz to 30 kHz, with an amplitude adjustable up to about 9 V peak., , Figure 22.26 Sinusoidal waveform generator with adjustable frequency and amplitude., , 5-V (TTL) PULSE GENERATOR, A circuit providing a 5-V pulse waveform for use with TTL digital circuits is, shown in Fig. 22.27. The 8038 IC provides a rectangular or pulse waveform at a fixed, output between 0 and 5 V. The frequency of the output can be varied from about, 30 Hz to 30 kHz when adjusting the value of the 10-k potentiometer. A commercial signal generator would probably include switched capacitors to provide frequency, over a range of values. As long as the supply uses an IC regulator to provide the 5V supply voltage, the output will be a well-defined value, as is typically used in TTL, circuits. The 310 unity follower provides the output from a low-impedance source,, making it possible to connect the output to a number of loads without affecting the, amplitude or frequency of the signal waveform., 900, , Chapter 22, , Oscilloscope and Other Measuring Instruments
Page 927 :
Figure 22.27 TTL signal waveform generator., , 22.9 Signal Generators, , 901
Page 928 :
Preface, As we approached the 30th anniversary of the text it became increasingly clear that, this Seventh Edition should continue to include the major revision work that went, into the Sixth Edition. The growing use of computer software, packaged IC units, and, the expanded range of coverage necessary in the basic courses which contributed to, the refinement of the last edition have continued to be driving factors affecting the, content of the new edition as well. Over the years, we have learned that improved, readability can be attained through the general appearance of the text, so we have become committed to the format you will find in the Seventh Edition to make the text, material appear “friendlier” to a broad range of students. As in the past, we continue, to be committed to the strong pedagogical sense of the text, accuracy, and a broad, range of ancillary materials that support the educational process., , PEDAGOGY, Without question, one of the most important improvements retained from the Sixth, Edition is the manner in which the content lends itself to the typical course syllabus., The resequencing of concept presentation which affected the last edition has been retained in this new edition. Our teaching experience with this presentation has reinforced our belief that the material now has an improved pedagogy to support the instructor’s lecture and help students build the foundation necessary for their future, studies. The number of examples, which were substantially increased in the previous, edition, have been retained. Isolated boldfaced (“bullet”) statements identify important statements and conclusions. The format has been designed to establish a friendly, appearance to the student and ensure that the artwork is as close to the reference as, possible. An additional color is employed in a manner that helps define important, characteristics or isolate specific quantities in a network or on a characteristic. Icons,, developed for each chapter of the text, facilitate referencing a particular area of the, text as quickly as possible. Problems, which have been developed for each section of, the text, progress from the simple to the more complex. In addition, an asterisk identifies the more difficult exercises. The title of each section is also reproduced in the, problem section to clearly identify the exercises of interest for a particular topic of, study., , xiii
Page 929 :
SYSTEMS APPROACH, On numerous visits to other schools, technical institutes, and meetings of various societies it was noted that a more “systems approach” should be developed to support, a student’s need to become adept in the application of packaged systems. Chapters 8,, 9, and 10 are specifically organized to develop the foundation of systems analysis to, the degree possible at this introductory level. Although it may be easier to consider, the effects of Rs and RL with each configuration when first introduced, the effects of, Rs and RL also provide an opportunity to apply some of the fundamental concepts of, system analysis. The later chapters on op-amps and IC units further develop the concepts introduced in these early chapters., , ACCURACY, There is no question that a primary goal of any publication is that it be as free of errors as possible. Certainly, the intent is not to challenge the instructor or student with, planned inconsistencies. In fact, there is nothing more distressing to an author than, to hear of errors in a text. We believe this text will enjoy the highest level of accuracy obtainable for a publication of this kind., , TRANSISTOR MODELING, BJT transistor modeling is an area that is approached in various ways. Some institutions employ the re model exclusively, while others lean toward the hybrid approach, or a combination of these two. The Seventh Edition will emphasize the re model with, sufficient coverage of the hybrid model to permit comparison between models and, the application of both. An entire chapter (Chapter 7) has been devoted to the introduction of the models to ensure a clear, correct understanding of each and the relationships that exist between the two., , PSpice, The last few years have seen a continuing growth of the computer content in introductory courses. Not only is the use of word-processing appearing in the first semester, but spreadsheets and the use of a software analysis package such as PSpice, are also being introduced in numerous educational institutions., PSpice was chosen as the package to appear throughout this text because it is most, frequently employed. Other possible packages include Micro-Cap III and Breadboard., The coverage of PSpice provides sufficient content to permit drawing the schematic, for the majority of networks analyzed in this text. No prior knowledge of computer, software packages is presumed. PSpice permits entering the circuit schematic, which, can then be analyzed with output results provided as text files or as probe graphic, displays., , ELECTRONICS WORKBENCH, The EWB CD-ROM included with this text also contains a fully functional EWB, demo that will operate circuits from throughout the text. In addition, the CD-ROM, contains a tutorial that instructs students how to operate EWB and how to simulate, circuits. The CD-ROM also includes a locked version of Electronics Workbench®Stuxiv, , Preface
Page 930 :
dent Version 5.0 that can be unlocked by calling Interactive Image Technologies. Instructions for unlocking the software are included on the CD-ROM., , TROUBLESHOOTING, Troubleshooting is undoubtedly one of the most difficult abilities to introduce, develop, and demonstrate in a text mode. It is an art that can be introduced using a variety of techniques, but experience and exposure are obviously the key elements in, developing the necessary skills. The content is essentially a review of situations that, frequently occur in the laboratory environment. Some general hints as to how to isolate a problem area are introduced along with a list of typical causes. This is not to, suggest that the student will become proficient in the debugging of networks introduced in this text, but at the very least the reader will have some understanding of, what is involved with the troubleshooting process., , ANCILLARIES, The range of ancillary material is comprehensive. In addition to a Laboratory Manual with an associated Solutions Manual (with typical data), there is an Instructor’s, Manual with more than 150 Transparency Masters, a Test Item File, PowerPoint Transparencies, and a Prentice Hall Custom Test (Windows). The Instructor’s Manual, with Transparency Masters and the Solutions Manual have been carefully prepared, and reviewed to ensure the highest level of accuracy. In fact, a majority of the solutions were tested using PSpice., , USE OF TEXT, In general the text is divided into two main components: the dc analysis and the ac, or frequency response. For some schools the dc section is sufficient for a one-semester, sequence, while for others the entire text may be covered in one semester by choosing specific topics. In any event the text is one that “builds” from the early chapters., Superfluous material is relegated to the later chapters to avoid excessive content on, a particular subject early in the development stage. For each device the text covers a, majority of the important configurations and applications. By choosing specific examples and applications the instructor can reduce the content of a course without losing the progressive building characteristics of the text. Then again, if an instructor, feels that a specific area is particularly important, the detail is provided for a more, extensive review., ROBERT BOYLESTAD, LOUIS NASHELSKY, , Preface, , xv
Page 931 :
Glossary, acceptor atom Atom with three valence electrons added to a, semiconductor to reduce the number of electrons in it,, thus creating holes in the semiconductor’s valence band., , candela Unit of light intensity in SI., , active region Area on a device characteristic where the ratio, between applied voltage and resulting current is constant., That is, the device is not operating in regions such as saturation, cutoff, or ohmic., , cascode amplifier High frequency amplifier made up of a common-emitter amplifier with a common-base amplifier in its, collector network., , amplification Process of changing the amplitude of a signal, with minimum alteration in its shape., amplifier Assembly that produces an output quantity such as, voltage or current in linear proportion to an applied input, quantity. The output quantity is not necessarily larger than, the input quantity., analog-to-digital converter (ADC) Circuit that converts an, analog signal to a digital signal whose binary value represents the amplitude of the original analog signal., anode Positive terminal of a bipolar device., astable multivibrator Oscillator circuit that produces a rectangular wave output., bandwidth Range of frequencies for which the gain is at least, 0.707 of midband gain., bias line Graphical technique in circuit analysis which describes, the bias circuit, external to a device, on the device transfer, characteristic curve., bias(ing) Fixed dc voltage applied to a circuit that is intended, to set a device’s operation at a particular point on its characteristic curve., bipolar Type of device whose functioning involves both majority and minority charge carriers., bipolar junction transistor. See BJT, BJT Bipolar junction transistor is a 3-layer device containing, both types of semiconductor material (either in p-n-p or np-n form). It typically has three terminals., Bode plot Graph of gain or phase shift versus frequency for a, circuit., body resistance Inherent resistance of the block(s) of material, composing an electronic device—one aspect of how a, practical device deviates from ideal., bridge Network of four components arranged in a square with, identical opposite pairs of elements. The input is attached, across one diagonal, and the output across the other., , cascade amplifier Amplifier with two or more stages in which, the output of one stage serves as the input to the next., , cathode Negative terminal of a bipolar device., characteristics Set of graphs that display any operating feature, of an electronic device, such as collector current vs. collector-emitter voltage for a set of different base currents., chip Common name for an integrated circuit. Many chips are, cut from a single wafer of silicon that has been doped and, etched to form many elements and components., clamping Process of shifting an input ac signal to a different, zero point., clipper Circuit that cuts off some portion of an input signal., clipping Failure of a circuit to respond to signals above a certain amplitude, causing distortion of the output signal., CMOS Complimentary MOS: digital integrated circuitry in, which both n- and p-channel MOSFETs are used., common Path for current returning to the power supply from a, circuit., common base (emitter, etc.) Configuration in which the base, (emitter, etc.) the terminal of a three-terminal device is, common to both the input and output loops of the circuit., common-mode rejection Ratio of the differential gain of an, op-amp to its common-mode gain., comparator Op-amp circuit that compares two input voltages and, provides a DC output that indicates which input is greater., conduction angle Portion of a half wave, expressed in degrees,, during which a silicon-controlled rectifier is conducting., constant-current source Circuit that provides constant current, to a changing load., contact resistance Resistance at the contacts with the material, of an electronic device—one aspect of how a practical device deviates from ideal., conversion efficiency For an amplifier, the ratio of output ac, power to input dc power., corner frequency Frequency at which the gain of an amplifier, has dropped to 0.707 of midband value., , G1
Page 932 :
G2, , Glossary, , crystal oscillator An oscillator with a piezoelectric crystal in its, feedback network to maintain a stable frequency of oscillations., current mirror Circuit consisting of two matching transistors, with the collector of one connected to the bases of both,, thus producing the same collector current in each transistor., current-limiting circuit Protection circuitry that prevents the, output current from exceeding a maximum value under an, overload or short-circuit condition., cut-off State of a semiconductor device in which the current is, a minimum., cut-off frequency See corner frequency, , equivalent circuit Combination of elements intended to mimic, the characteristics of an electronic device with mathematical aspects that are simpler than those of the actual device. See also model, extrinsic material Semiconducting material that has had its, conducting properties altered by doping; n-type material, contains extra electrons; p-type material contains extra, holes., feedback Application of a portion of an amplifier’s output to its, input. It is used to improve amplifier performance or to, cause oscillation., feedback pair Two bipolar junction transistors with the collector of the npn connected the emitter of the pnp and the, collector of the pnp connected the base of the npn., , Darlington pair connection Two bipolar junction transistors, with their collectors connected together and the emitter of, one connected to the base of the other., , FET Field-effect transistor, , demodulation Process of extracting a signal that has been impressed on a carrier wave., , filter Part of a power supply that converts the rectified sine, wave from the rectifier into a dc voltage with ripple., , depletion Application of an electric field that repels majority, carriers in a volume of semiconductor material., , foldback limiting Protection circuitry that causes the output, current to decrease to a low value under an overload or, short-circuit condition., , depletion region Region near the junction of a semiconducting, device that has few free carriers because electrons and, holes have combined., detection See Demodulation, die Another term for chip., differential amplifier Amplifier in which the output voltage is, proportional to the difference between the voltages applied, to its two input terminals., digital-to-analog converter (DAC) Circuit that converts a digital signal to an analog signal whose amplitude is proportional to the binary value of the digital signal., diode Two-terminal device that conducts unidirectionally., discrete component Package containing only a single electrical, or electronic component., donor atom Atom with five valence electrons added to a semiconductor to increase the number of electrons in it., donor level Energy level of the valence band in a semiconductor with doping, which reduces the energy gap between, the valence band and the conduction band., doping Process of adding small quantities of particular impurities to an intrinsically pure semiconductor in order to alter, its conducting properties., dropout voltage Minimum value by which the input voltage of, a voltage regulator must exceed the output voltage for regulation to occur., , follower Voltage amplifier whose output “follows” the input,, and so has a gain of approximately one., forward-bias Voltage applied to a p-n junction (positive to p,, negative to n) that diminishes the depletion region and increases the flow of majority carriers., Fourier analysis Mathematical technique for describing a complex waveform as the sum of the harmonics of a fundamental., free Of electrons, those that are only loosely bound to an atom, or ion—they are able to migrate readily through a material, under the application of small electric fields., frequency modulation Process of varying the frequency of a, signal such that the instantaneous value of the frequency, is proportional to the amplitude of a control voltage or, signal., frequency-shift keying Form of frequency modulation in which, the value of a digital signal sets the frequency at one of, two values., full-wave rectification Converting ac to dc using both halves of, each ac input cycle., fundamental Lowest frequency component of a waveform., gain Amplification factor of an amplifier, the ratio of output to, input., , efficacy Measure of the ability of a device to produce a desired, effect., , gain margin Value in decibels of the amplitude of the βA factor, of a feedback amplifier at the frequency for which the, phase shift of βA is 180°., , electroluminescence Emission of light by a device when electrical energy is supplied., , gain-bandwidth product Transistor parameter that indicates the, maximum possible product of gain and bandwidth., , electron volt Energy required to move a charge of one, electron through a potential difference of 1 V; equals, 1.602 1019J., , gradient Regular change in a quantity along a given line or dimension; a the rate of change of such quantity., , enhancement Application of an electric field that attracts majority carriers to a volume of semiconductor material., , half-wave rectification Converting ac to dc using only half the, input of each full ac cycle., , half-power frequency See corner frequency
Page 933 :
Glossary, , harmonic A sine wave that is an integral multiple of a fundamental frequency. See also fundamental, hole Vacancy in a normally filled site in a valence shell or band,, created by doping with an acceptor atom. A hole is mobile, and conducts as if it were a positive charge., hybrid Involving the combination of unlike quantities or materials, as for example, voltage and current., hybrid IC Integrated circuit that is composed of monolithic, components and either thin-film or thick-film components., IC component Package containing more than one electrical or, electronic component in a single package., ideal device Device that performs its function perfectly; e.g., an, ideal transducer converts without loss all the energy applied to it., ideal diode Diode that conducts perfectly in one direction and, not at all in the opposite direction (zero resistance in one, direction and infinite resistance in the opposite direction)., integrated circuit (IC) Collection of solid-state devices combined with other circuit elements printed on a single chip., , mesa transistor Transistor produced by etching away a part of, the area above the collector region to form a plateau on, which the base and emitter regions are then formed., minority carriers Charge carriers that are deficient in extrinsic, material—holes in n-type material or electrons in p-type, material., model Representation of a system (either concrete or abstract), intended to assist in understanding the system, either by, simplifying or emphasizing particular features of the system. Consider the differences among “model airplane,”, “atomic model,” and “fashion model.” See also equivalent, circuit, modulation Process of combining a signal with a carrier wave, (which is usually at a much higher frequency)., monolithic IC Circuit in which all components are formed as, pn junctions on or within a semiconductor substrate., monostable multivibrator Circuit with one stable output state, that, when triggered, switches to an unstable state for a, fixed period of time and then returns to the stable state., , interface circuit Circuit that links input and output signals of, different types of logic families with each other or with, analog signals., , MOSFET Metal-oxide-semiconductor field-effect transistor., , intrinsic carriers Charges constituting a current that are able to, move simply because of the nature of the material and its, temperature. see also extrinsic, , no-bias Circuit that contains no fixed applied voltage., , ionization Process by which an electron is removed from an, atom by the application of some form of energy., ionization potential Electrical potential that is just sufficient to, remove an electron from a shell of its atom., JFET Junction field-effect transistor, , negative feedback Circuitry in which a feedback signal is 180°, out of phase with the input signal., Nyquist diagram Plot of the βA factor of a feedback amplifier, as a vector on the complex plane for frequencies from, zero to infinity., offset potential Potential difference at which a diode or transistor begins to conduct at significant currents. It is also, called the firing potential or threshold potential, and is, symbolized as VT., , lattice Regular spacing in three-dimensions of atoms in a crystal., , op-amp Operational amplifier, a high-gain amplifier with an, output that corresponds to the difference between two input signals., , leakage current Minority carrier current in a reverse-biased, junction in the absence of injected minority carriers., , oscillator Electronic circuit that produces a periodic output, waveform with no voltage other than dc applied., , light-emitting diode Diode that will emit light when forward, biased., , parallel resonance Condition occurring in a parallel RLC network at the frequency where the reactance of the inductor, equals the reactance of the capacitor., , junction The area of contact between volumes of n- and p-type, extrinsic material., , linear circuit Circuit in which one quantity changes in direct, proportion to another quantity., load line Graphical technique in circuit analysis which describes the output circuit, external to a device, on the device output characteristic., load-line analysis Method of describing the operation of an, electronic device using the intersection of a line representing the load on the device and a graph line of the device’s, characteristics. The intersection is called the Q-point., , peak inverse voltage See PIV, phase margin 180° minus the phase shift at the frequency at, which the gain is 0 dB., phase-locked loop Circuit in which the phase of the output signal is compared to the phase of the input signal and, adjustments made such that the output signal will lock, onto and track the input signal., , load regulation Measure of the change in load voltage as load, current changes from no-load to full-load value., , phase-shift oscillator Oscillator with a feedback network consisting of three RC high-pass networks connected in series, that produce 180° phase shift., , majority carriers Charge carriers made abundant in the doping, process of extrinsic material—electrons in n-type material, or holes in p-type material., , piecewise linear equivalent circuit Equivalent circuit with elements chosen to approximate the device’s characteristic, with straight-line segments., , G3
Page 934 :
G4, , Glossary, , piezoelectric effect Property of a crystal that produces a voltage, across opposite faces due to mechanical stress and vice, versa., PIV Peak inverse voltage, the maximum reverse-bias potential, that can be applied to a diode before entering the Zener, region; also called PRV., planar transistor Transistor produced by forming the base and, emitter regions within the collector region rather than, above it., port A pair of terminals., power supply Circuit that converts a sinusoidal voltage into a, dc voltage., Q-point Point on a device’s characteristic from which it operates. Set by the dc components in the circuit, the quiescent point sets the zero for ac variations. It is the, intersection of the load line with a characteristic curve., quiescent point See Q-point, rectification Process of converting ac to dc., reverse-bias Voltage applied to a p-n junction (negative to p,, positive to n) that enlarges the depletion region and increases the flow of minority carriers., ripple Ratio of the ripple voltage to the dc voltage expressed as, a percentage., ripple voltage Small variations in the amplitude of the voltage, at the output of the filter in a power supply., saturation (1) Condition in a semiconductor in which no further increase in current results, no matter how much additional voltage is applied. (2) In a BJT, the state in which, the voltage from collector to emitter is a minimum, typically 100 mV. (3) In an FET, the state in which an increase in the voltage from drain to source does not result, in a significant increase in non-zero drain current., semiconductor Any material that possesses a resistivity much, higher than good conductors and much lower than good, insulators., series regulator Voltage regulator in which the control element, is in series with the output voltage., , strobe Control signal whose value determines whether a circuit, is enabled or disabled., switching regulator Regulator in which regulation is maintained by switching the power control devices between on, and off states., temperature coefficient Number that expresses the rate of, change of a quantity with temperature as, for example, the, temperature coefficient of resistance., tetravalent atom Atom containing four electrons in its (outer), valence shell., thick-film IC Integrated circuit with passive elements deposited, on a substrate using screening and firing processes and active elements added on the surface as discrete components., thin-film IC Integrated circuit with passive elements deposited, on a substrate using a sputtering or vacuum process and active elements added on the surface as discrete components., threshold voltage Voltage level for a diode or transistor that results in a significant increase in drain current. See also, offset potential, tilt Measure of the loss in amplitude of a pulse from the leading, edge to the trailing edge of the pulse., transconductance factor For an FET, the ratio of the change in, drain current to the change in gate voltage that induced it;, symbol, gm; unit, siemen., transfer characteristic Graph that displays the relationship between the input and output quantities of a device., transistor Semiconductor device useful for amplifying or, switching electrical signals., tuned oscillator Oscillator in which component values in an LC, network determine the frequency of oscillations., two-port network Generalized model of a linear circuit that has, two input and two output terminals., unipolar Device whose functioning involves only majority, charge carriers., valence Outer shell of an atom containing the electrons that determine the element’s chemical characteristics., , series resonance Condition occurring in a series RLC network, at the frequency where the reactance of the inductor, equals the reactance of the capacitor., , voltage-controlled oscillator (VCO) Oscillator whose output, frequency varies with a modulating input voltage., , shunt voltage regulator Voltage regulator in which the control, element is in parallel with the output voltage., , wafer Thin slice of semiconductor crystal on which many IC, circuits (chips) are formed., , signal Electrical waveform that contains information, varying, according to (for example) an audio or video input., , Wien bridge oscillator Oscillator with a feedback network consisting of a series RC network and a parallel RC network, in a bridge circuit., , single-crystal Any material composed only of the repetitive, structure of one kind of unit crystal., small signal AC operation of an electronic device in a small, enough vicinity around the q-point that the slope of the, device transfer characteristic in that vicinity can be considered constant., source regulation Measure of the change in load voltage as, source voltage changes., , yield rate Percentage of the chips obtained from a single wafer, that meet specifications., Zener potential The reverse-bias voltage at which a diode will, experience a sharp increase in reverse current., Zener region Portion of the current-voltage characteristic of a, diode which shows a sharp increase in reverse current at, the Zener potential.
