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Experiment No:6, , Multiplexer and Demultiplexer, MULTIPLEXER, , BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:, , DESIGN:, 4:1 MUX FUNCTION TABLE:, SELECT, S1, S0, INPUTS, 0, 0, 0, 1, , DATA INPUTS, D0 D1 D2 D3, 1, X x, x, x, 1, x, x, , min, , OUTPUT, , term, , Y, 1, 1, , 1, , 0, , x, , X, , 1, , x, , 1, , 1, , 1, , x, , X, , x, , 1, , 1, , SOP expression for the OUTPUT is, , Logic circuit diagram of a 1:4 Multiplexer (USING BASIC GATES):

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1:4 DEMUX FUNCTION TABLE, DATA, , SELECT, , INPUT, , INPUTS, , OUTPUTS, , S1, , S0, , Y0, , Y1, , Y2, , Y3, , D, , 0, , 0, , D, , 0, , 0, , 0, , D, , 0, , 1, , 0, , D, , 0, , 0, , D, , 0, , 1, , 0, , 0, , D, , 0, , D, , 1, , 1, , 0, , 0, , 0, , D, , From the table, the output logic can be expressed as min terms and are given, below., , Where D is the input data, Y0 to Y3 are output lines and S0 & S1 are, select lines., By applying double inversion rule to each output above, DEMUX circuit, diagram using NAND gates only can be realized., , 4:1 DEMUX USING BASIC GATES

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4:1 DEMUX USING NAND GATES, , Pin diagrams of IC 7411(3 input AND gate) and 7410( 3 input NAND gate)