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f, , , , a [ais Digital Electronics: Principles and Applications, , s, , , , the first clock pulse, When the second clock pulse is COM eg ee, apptied, Q, becomes 1 and outputs of other flip-flops % os r, are 0. On the application of third clock pulse, Q, is 1 __s “!, Land O."0,"0,"0,-0. Similarly, Ql when fourth ma —— a, , , , , , clock pulse is applied and O.<0,-0,-0,-0. So that, , we can verify that "I" is always retained in the counter, , but simply shifting around the ring afer application, -» of path clock pulse,, , , , , , Fig. 8.40 Timing diagram five-bit Ring counter, , , , , , 2) s4s counrer, Ss When a group of flip-flops are connected in cascade, the counting operation is performed, THen, this, so "sequential circuit is most commonly used for counting purpose, and this circuit is called as counter. The, “pk counter is also a memory system as any counter circuit must remember its past states and it p, <= data in memory. In this chapter, the connections of flip-flops to make, any type of counter and t, CEA, operations have been explained. Counters are mostly used, in digital computers, digital telephone and, =~ digital instruments. A number of flip-flops are required for different asynchronous and synchronous, a, , , , counters, divide by 'n' counters, and their connection diagram and the numbers of sequential states are, explained. The design of synchronous counters, cascade counters and self-starting art self-correcting, counters wre also discussed in this chapter, . ., , 8.16 CLASSIFICATION OF COUNTER, , ‘There are several types of counters, which are able to count binary numbers. Counters can be classified’, based on application of clack, number of flip-flops (stages) and sequential states: According to, application of clock to Mip-flops, counter is divided into two broad categories namely asynchronous, and synchronous counters, As per number of flip-flops (stages) counters are 2 bit, 3 bit, 4 bit and » bit., Counters can also be used as count up or count down based on sequential states., , Asynchronous (Ripple) Counters In asynchronous counter, the gxternal clock pulse ¢locks ;, , the first flip-flop, Then, the output of first Gip-flop (Q or Q) is connected as clock of the next flip-fiop., Similarly, each successive flip-flop is clocked by the Q or O of the previous one. All flip-flops do not, change states in exact synchronism with the applied ¢lock pulses. There is some propagation delay between, responses of successive flip-flops, The asynchronous counter is also called as tipple counter duc to the, way of flip-flop response one after another in a kind of rippling effect. ‘The maximum clock frequency, , _ of an asynchronous counter decreases with the increase af number of flip-flops or bits. Asynchronous, counter can generate glitches in decoding gates due tu Propagation delays, Therefore, strobing technique, should be used for eliminating the effects of glitches., , Synchronous Counters In synchronous counter, the clock input tenninals of all flip-flops are, commonly connected, Therefore, the same clock pulse simultaneously triggers all flip-flops of the counters, and the problem caused by the flip-flop propagation delay has been climinaled in these counters, For a, synchronous counter, the maximum frequency remains same, regardless of the number of bits,, , Count Down Counter Synchronous and asynchronous counters are able to count either in ine: sing oF, decreasing order. Incouat down counter, the counter value sequentially decreases. Ina three Slage down caunter,, the counting sequence is 7, 6, 5, 4, 3,2, 1, and 0. This counter can be made by J-X or Tor D flip-flops. , ' Count Up Counter In count up counter, the counter value sequentially increases, The caunting sequence of, three-stage counter is 0, 1, 2,3, 4, 5, 6, and 7. This counter can also be designed by J-K of Tor D flip-flops., , , , , , , , , , , , ACT NAL aes ontewmanin matt
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|, , Sequential Circuits 1 9 ||, ST CA pt TT}, , 8.17, ASYNCHRONOUS (RIPPLE) COUNTERS, , The sequence of binary counter follows 9 divide-by-two pattern. This means that the freque, each bit, from least significant bit (LSB) to most significant bit (MSB), follows a divide by-two pattern, Therefore, the LSB is half of the clock frequency and the highest frequency among all stapes. The, frequency of the next bit is one-half the LSB's frequency. The counter circuit can be, flip-flops or J-X flip-Nlops when operate in the toggle mode to count in a binary seque, , r fe, ney for, , , , ipned using 7, , , , , , , , , , , , a4 Sis act 8.17.1 1 bit Ripple Counter, a s One bit ripple counter using J-X flip-flops is shown in, J Q a Fig. 8.41. When J and K inputs are made high, J-€ flipflop is operating in toggle mode. As a result, after each, , A a . Positive edge clock pulse, output of flip flop is changed, : Ky a 3 Here, the signal Ais clock pulse and 2 represents the, ' output of J-K flip-flop. The count sequence is from 0 to, , , , , , , , . 1 and | to 0. Timing diagram of one bit asynchronous, ; Fig. 8.41 One bit asynchronous counter counter is depicted in Fig. 8.42., , Clock Ao }4 oft Loft Lost Lo 1 Loft], 1, Outputs ait 1(6 6/4 tlo_of1 1 Lo, , , , , , , , Fig. 8.42 Timing diagram of one bit asynchronous counter, , 8.17.2 2-bit Ripple Up Counter, , , , , , , , , , , , , , , , A two-bil ayynchronous counter is shown inedigg@@™S. Usually, all, , * a a the CLEAR inputs are connected together, so that a single pulse can, 2 os E42 clear all the flip-flops before counting stans. The external clock is, , = sTtl |e connected to the clock input of the first flip-flop (FF) only. Sa, fF,, , = changes state at the negative edge of each clock pulse, but FF, changes, , a | 7 I only when triggered by the falling edge of the Q output of FF, Due, , to propagation delay the transition of the input clock pulse and a, , "Fig. 8.43 2-bityipple counter transition of the Q output of FF, can never occur at exactly the same, , , , , , , , , , , , , , , , A time. Therefore, all flip-flops cannot be triggered simultaneously, eux 9 PL PLBLLL and an asynchronous operation is performed. The transitions of, » Oo é ig fie) 1 CLK, Q,, and Q, are shown in the timing diagram as shown in, : Ye ert Fig. 8.44, Truly, there is some small delay between the CLA, O,, " * @t23 0 and Q, transitions,, {3 Fig. 8:44 Timing diagram of 2-bit The 2-bitripple cou- Table 8.8 State sequence for 2-bit, ms’ Binary up counter nter circuit has four dif- ripple up counter, =i ferent states as depicted in Table 8.8. The relationship between Clock pulse] 0, 0,, 3 humber- of bits (flip-flops) and number of states is that a coun- 7 a, mer with n flip-flops can have 2° states. The number of states Oo 1 |, Ein a Counter is known as its modulo number or mod number, 2 te, cordingly, a°2-bit counter is a mod-4 counter. The timing pert
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\j s20 Digital Electronics: Principles and Applications, , diagram of two bit asynchronous counter is illustrated in (% of" ), Fig. 8.44 and state transition diagram of 2-bit counter is a Z, depicted in Fig. 8.45. : | |, , ey—_®, , a ate ; eli Fig. 8.45 State transition diagram of A, 8.17.3 2-bit Ripple Down Counter 29-bit up-counter binary, ov Vv 5, , A two-bit ripple down counter is shown in Fig. 8.46. The ., , at ° oe extemal clock is applied to the clock input of the flip-flop, FF,, }e— only. The output of FF, is used as clock of FF,. In count down, CLK. TL counter, outputs Q, and Q, are taken from complement output, a oO of FF, and FF, respectively. Timing diagram of two-bit ripple +, down counter is depicted in Fig. 8.47. The state sequence of, FFo FF ii counting is 3, Table 8.9, Figure 8.48 ;, %, , SeGsyigtns: St, , a“, , , , Bei, , 2, 1, and 0 is given in, 4, shows the state transition of 2-bit ripple down counter., ' i, , Fig. 8.46 2-bit ripple down counter (+) (+), , 2s. 2. 2, a ZU ' ; 3, % TLo fT Los, 7 7 1o_of7, o 4297 0 3 CG) ' C), , Fig. 8.47 Timing own counter diagram 2-bit ripple Fig. 8.48 State transition diagram of 2-bit ,, binary down counter *, , sting 2, , fone, , , , , , , , Table 8.9 State sequence for 2-bit ripple down counter, , , , , , , , , , , , , , , , Clock pulse, L, > P, re], 0, 8.17.4 3-bit Ripple Up Counter pany» Vie., Figure 8.49 shows the 3-bit ripple counter, which is implemented anf Le 4 ', using three J-K flip-flops. The counter is capable to count up us et, to 2=8. This counter is also called as module 8 or divide by 8 FF, FF, en ie ae of 3-bit counter is given in Table 8.10. Oo eras “ Oo, en the clock pulse is applied to the counter, the counter value Fig. 8.49 3-bit p, sequentially increases state by state and the output of flip-flops ." 423 wo : r : i ., indicates the count of pulses in counter, Waveform of three-bit * St 4 SAAAAAAL 1, binary ripple counter is shown in Fig. 8,50. ® jority, 8 5, , At the positive edge of the first clock i, , pulse, flip-flop FF, sets % g—sS Lt, and the output Q, becomes | and this output Ain affect on a : :, the output of FF,. So the counter output will be updated to 001, from 000 as shown in row 2 of Table 8.10, When the second, , (ST as 4s 7?, Fig. 8.50 Timing of 3-bit ripple up, counter 3
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Sequential Circuits 321 i, , clock:pulse, is applied, flip-flop FF, is reset and the output of FF,, , Table 8.10 Truth table of 3-bit :, aa =n 0. After the second clock pulse, flip-flop FF, is, , ripple up counter — changes from | to, , set and the output of FF, changes from 0 to 1, Then counter output, See will be 010 as depicted in third row. When the third clock pulse is, , d output becomes 1. At this time, the, ange. At that moment, the output of, pulse is applied, flip-flop FF,, m I to 0. In this time flipwill be 0, which changes, , La ae ' applied, FF, flip-flop sets an, state of FF, and FF, do not c, the counter is OL. Ifthe fourth clock, resets and the output of FF, changes fro!, flop FF, resets and the output of FF,, Q,, , the flip-flop FF, to |. ae, ; : ‘As soon as the fifth clock pulse given in FF,, the said flip-flop, sets and output Q, becomes 1, while the output of flip-flop FF, and FF, are not affected. After fifth, _ pulse, the counter output'is 101. In the next pulse, flip-flop FF, resets and flip-flop FF, and FF, are set,, During the 7* pulse, all flip-flops, FF,, FF, and FF,, are set and the counter output will be 111, When, the eighth pulse is applied, all flip-flops are reset and then counter output is 000. In this way, the counter, , * counts 0 to 7 sequentially., , , , 8.17.5 3-bit Ripple Down Counter, , Figure 8.51. stiows the circuit diagram of 3-bit down counter. In up counter, the output Q,, Q, and Q, are, taken from output Q of flip-flops FF, FF, andFF,respectively,, o by 3 but in down counter, the complement output 0 of flip-flop FF,, = r FF,, and FF, are connected to Q,, Q, and Q,. Truth table of 3bit ripple down counter is shown in Table 8.11., , ov: ov ow, , , , , , , , , , , , , , , , , , 3 5, = * Initially, consider that all flip-flops are reset and the counter, in fa o, Output will be 111, As soon as the first clock pulse is applied, i to the flip-flop FF,, it will be set. The complement output of, , Fig. 8.51 ‘ 3-bit ripple down counter FF, is,0. The output of FF, will be 0 and it complement is, 2 1. The output of FF, will also be 0 and its complement is I., , Table 8.12 —S— ripple Therefore, the counter output is 110., , - After application of second clock pulse, FF, flip-flop will, State be reset. The complement output of FF, is 1, which affects the, FF flip-flop. So the counter output is 101. Similarly, it is depicted from table that the counter sequentially decreases one, by one after applying each clock pulse. After applying sixth, clock pulse counter value is 001 and at the end of seventh, clock pulse the, , 12348 67 8, , output of coun- a PULL rk, , , , , , ae 28. : ter is 000, Figure, , 8.52 shows the waveform ‘of 3-bit ripple down counter. SS, : : ES % . . Pe, , 8.17.6,-4-bit Ripple Up Counter . me fee rrr, , t diagram of 4-bit ripple"up Fig. 8.52 Timing diagram of 3-bit ripple, , Figure-53 shows the circuit, p-flops. Truth table down counter, , counter, which is made by four J-K fli, , |, {, {
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Digital Electronics: Principles and Applications, , , , , of 4-bit ripple Up counter is depicted in Table 8.12. This, , —9 la ~t, i }*) counter counts sequentially from 0000 to W111 like three, {_ She fs bit ripple Up counter. The state transition d m is given, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , rs — in Fig. 8.54. Figure 8.55 shows the w 1 of 4-bit, a : a, ~ pple up counter. It can be viewed that th put of each, Fig. 8.53 _4 bit ripple up counter flip-flop divides the input clock frequency by 2, BOG, 2 121M YF, eA UU, ‘Lu Lr oe., Or, % 6 Se, & 4 |, o> Leen, o123 465 6€ 7 &S wr 2D 4 HG, Fig. 8.54 Waveform of 4-bit Fig. 8.55 State transition diagram of 4-bit ripple up counter, ripple up counter . t, i, Table 8.12 Truth table of 4-bit ripple up counter, State 0, 0, eo Q), 0, |_.0_, 0, 0,, |, 1, _ 1, A, o, 0, a |, = I, 1, 1, |, Figuyé 8.56 shows the circuit diagram of 4-bit ripple ev Vv ov ov, down counter, which is made by four J-X flip-flops. ° \2 oly 40, Truth table of 4-bit down counter is depicted in CX q 4 4, Table 8.13. This counter counts sequentially from a wf i: ilk, 1111 to 0000. The state transition diagram is given FFo FF, FF, FF, in Figure 8.57. Figure 8.58 shows the waveform of = on = eteg, 4-bit ripple down counter. Fig. 8.56 4-bit ripple down counter, i— 4 , ‘, . % .
